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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57932 )
Change subject: soc/intel/{skl,cnl,dnv,xeon_sp}: disable PM ACPI timer if chosen
......................................................................
Patch Set 33:
(1 comment)
File src/soc/intel/xeon_sp/pmc.c:
https://review.coreboot.org/c/coreboot/+/57932/comment/cc97b33a_dbe07ea1
PS33, Line 60: Disabling ACPI PM timer also switches off TCO.
> I didn't find any documentation mention disable PM timer will stop TCO, any link please?
You already found it in FSP bsf ;) Check the refcode and BIOS spec. https://review.coreboot.org/c/coreboot/+/57933/33
Or just test it :-)
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Ronak Kanabar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58289
to look at the new patch set (#2).
Change subject: soc/intel/adl: Skip sending MBP hob to save boot time
......................................................................
soc/intel/adl: Skip sending MBP hob to save boot time
MBP Hob is being generated by FSP after getting data from ME.
coreboot does not consume this Hob and FSP provides an option
for bootloader to skip generation of this Hob.
This will help in saving ~14 ms of boot time.
Here is the data from Brya P1 Board:
Before: 955 returning from FspSiliconInit 879,432 (99,156)
After: 955 returning from FspSiliconInit 1,177,513 (84,506)
BUG=b:188577893
BRANCH=None
TEST=No function impact on Brya system and boot time is reduced with
this patch.
Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58289/2
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Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58289 )
Change subject: soc/intel/adl: Skip sending MBP hob to save boot time
......................................................................
soc/intel/adl: Skip sending MBP hob to save boot time
MBP Hob is being generated by FSP after getting data from ME.
Coreboot does not consume this Hob and FSP provides an option
for bootloader to skip generation of this Hob.
This will help in saving ~14 ms of boot time.
Here is the data from Brya P1 Board:
Before: 955 returning from FspSiliconInit 879,432 (99,156)
After: 955 returning from FspSiliconInit 1,177,513 (84,506)
BUG=b:188577893
BRANCH=None
TEST=No function impact on Brya system and Boot time is lesser with
this patch.
Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/58289/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 698cff6..567883b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -203,6 +203,9 @@
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
+
+ /* Skip sending MBP HOB from FSP */
+ m_cfg->SkipMbpHob = 1;
}
static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57934 )
Change subject: soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig
......................................................................
Patch Set 27:
(1 comment)
Patchset:
PS27:
> What I mean is seems current linux kernel do not have any extra action base on this flag, maybe wind […]
Well, the OS is not required to honor the flag if it never uses the PM timer as clock. Still, we should it correctly.
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 )
Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58242/comment/db7cae09_657b7e7a
PS3, Line 9: framewok
> framework
Done
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I'd like you to reexamine a change. Please visit
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Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.
Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
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---
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/configs/config.unit-tests
A payloads/libpayload/tests/Makefile.inc
A payloads/libpayload/tests/drivers/Makefile.inc
A payloads/libpayload/tests/drivers/speaker-test.c
A payloads/libpayload/tests/include/mocks/x86_io.h
A payloads/libpayload/tests/include/tests/test.h
M util/testing/Makefile.inc
9 files changed, 544 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/58242/4
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