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Change subject: mb/siemens/mc_ehl2: Adjust PCH serial IO settings
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Patch Set 1: Code-Review+2
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Change subject: mb/siemens/mc_ehl2: Adjust USB settings
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Change subject: mb/siemens/mc_ehl2: Enable PCI devices
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Change subject: mb/siemens/mc_ehl2: Set coreboot ready LED
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Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
......................................................................
Patch Set 1: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58298/comment/ee9d8eff_e9b63a95
PS1, Line 7: sending
creating
https://review.coreboot.org/c/coreboot/+/58298/comment/34ae2d54_011488f0
PS1, Line 7: hob
Please use `HOB` in uppercase (also in the rest of the commit message).
File src/soc/intel/cannonlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/58298/comment/9a90b950_e2e03441
PS1, Line 154: sending
creating
https://review.coreboot.org/c/coreboot/+/58298/comment/2e17554d_0a10006c
PS1, Line 154:
Add `to reduce boot time`
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Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
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Patch Set 1: Code-Review+2
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Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 5:
(2 comments)
File payloads/libpayload/Makefile:
https://review.coreboot.org/c/coreboot/+/58242/comment/d4802c0b_62e4bfb5
PS4, Line 120: # 3. when make distclean is run
> Please update the comments.
Done. Thanks
I also fixed comments on line 305
File payloads/libpayload/tests/Makefile.inc:
PS4:
> Looks like most of the content is copied from coreboot/tests/Makefile.inc.
Yes, it does not differ much. It is easier to just copy this framework, than to configure coreboot/tests/Makefile.inc to run tests from both the coreboot, and the libpayload. Libpayload is a separate project inside coreboot repo after all.
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58298 )
Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
......................................................................
[WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
MBP Hob is being generated by FSP after getting data from ME.
coreboot does not consume this Hob and FSP provides an option
for bootloader to skip generation of this Hob.
Needs test.
Change-Id: I199259cf1141b9eaf3724895adc0955f2003e4db
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/58298/1
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2bb3024..c57d21d 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -151,6 +151,9 @@
/* Set HECI1 PCI BAR address */
m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
+ /* Skip sending MBP HOB from FSP */
+ tconfig->SkipMbpHob = 1;
+
mainboard_memory_init_params(mupd);
}
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Hello build bot (Jenkins), Nico Huber, Paul Fagerburg, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58242
to look at the new patch set (#5).
Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
libpayload: Add unit-tests framework and first test case
This commit adds a unit-tests framework ported from coreboot, and test
for drivers/speaker. Usage of the unit-tests framework is same as for
the coreboot one.
Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/configs/config.unit-tests
A payloads/libpayload/tests/Makefile.inc
A payloads/libpayload/tests/drivers/Makefile.inc
A payloads/libpayload/tests/drivers/speaker-test.c
A payloads/libpayload/tests/include/mocks/x86_io.h
A payloads/libpayload/tests/include/tests/test.h
M util/testing/Makefile.inc
9 files changed, 548 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/58242/5
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55262 )
Change subject: cpu/x86/lapic: Support switching to X2APIC mode
......................................................................
Patch Set 8: -Code-Review
(1 comment)
Patchset:
PS8:
I tested X2APIC_ONLY on my Asrock B85M Pro4 and it hangs around SMM setup. XAPIC case still works fine. Any ideas?
XAPIC log: https://paste.flashrom.org/view.php?id=3514
X2APIC log: https://paste.flashrom.org/view.php?id=3515
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