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Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58298/comment/5f238a86_935f506f
PS1, Line 7: to save boot time
> See the rest of the commit message: […]
But yes, I understand that your comment's intention is to specify how much time is saved in the commit message, and I agree.
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Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58298/comment/2563273f_c1943916
PS1, Line 7: to save boot time
See the rest of the commit message:
> Needs test.
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Change subject: mb/google/sarien: Add default fmap for non-ChromeOS builds
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58184/comment/a9725ab9_36443131
PS2, Line 9: Tianocore
> What is the hash? Also, did you boot an OS?
coreboot default options for the Tianocore payload. I don't own this device, but the user I built the firmware for did say it booted / they were able to boot Linux/Windows
File src/mainboard/google/sarien/default.fmd:
PS2:
> nit: It seems that there are no gaps and that they all follow one another. […]
I just copied the SI_ALL section directly from the chromeos.fmd, since it needs to be the same as the stock firmware
https://review.coreboot.org/c/coreboot/+/58184/comment/705c8034_d30d355c
PS2, Line 7: SI_PDR(PRESERVE)@0x3fc000 0x4000
> What is this region for?
absolutely no idea, this device is a weird franken-Dell Chromebook.
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Change subject: [WIP]soc/intel/cnl: Skip sending MBP hob to save boot time
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Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58298/comment/a23dc1f4_f6d63a98
PS1, Line 7: to save boot time
How much?
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Change subject: cpu/x86/lapic: Support switching to X2APIC mode
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Patch Set 8: Code-Review+1
(1 comment)
Patchset:
PS8:
Looks like it's some serialization issue. With X2APIC_RUNTIME, `is_x2apic_mode()` never returns false. And if I unconditionally execute the `rdmsr()` call inside `is_x2apic_mode()` by moving it before the `if (CONFIG(X2APIC_ONLY))` check, X2APIC_ONLY suddenly works just fine.
I think it's related to the 2nd note in this part of document 493770 (Haswell BWG): https://imgur.com/osj2JvP.png
> Note: The WRMSR instruction serializing semantic is relaxed for writes to the extended xAPIC MSRs. Software must not use WRMSR instructions which access extended xAPIC MSRs as a serializing instruction.
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Change subject: mb/google/sarien: Add default fmap for non-ChromeOS builds
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58184/comment/93969789_2a77389c
PS2, Line 9: Tianocore
What is the hash? Also, did you boot an OS?
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Change subject: cpu/x86/lapic: Support switching to X2APIC mode
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> I tested X2APIC_ONLY on my Asrock B85M Pro4 and it hangs around SMM setup. […]
OK, looks like CB:55198 breaks stuff because IA32_APIC_BASE is a thread-scoped MSR. Without that patch, X2APIC_ONLY still doesn't work, but X2APIC_RUNTIME boots successfully.
X2APIC_ONLY: https://paste.flashrom.org/view.php?id=3516
X2APIC_RUNTIME: https://paste.flashrom.org/view.php?id=3517
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Change subject: [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once
......................................................................
Patch Set 12: Code-Review-1
(2 comments)
Patchset:
PS12:
Breaks booting with X2APIC_RUNTIME on Haswell (X2APIC_ONLY didn't work before).
File src/cpu/x86/lapic/lapic.c:
https://review.coreboot.org/c/coreboot/+/55198/comment/de1e4b2a_272840fb
PS12, Line 20: msr = rdmsr(LAPIC_BASE_MSR);
This MSR is thread-specific on Haswell (no idea about other processors).
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