Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58117 )
Change subject: mb/google/guybrush: Override SPI Fast speeds
......................................................................
mb/google/guybrush: Override SPI Fast speeds
Add support to override SPI fast speeds based on board version from both
bootblock and verstage. Overrides apply for Guybrush only and SPI speed
is overridden from 66 MHz to 100 MHz starting board version 4. This will
help to improve the boot time on board version by ~60 ms and still allow
the old boards to boot with 66 MHz.
BUG=b:199779306
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/Makefile.inc
M src/mainboard/google/guybrush/chromeos.c
3 files changed, 26 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index c259d25..e5f1382 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -111,6 +111,22 @@
config ALT_SPI_SPEED
default 0 # 66MHz
+config OVERRIDE_EFS_SPI_SPEED
+ int
+ default 3 if EM100
+ default 4 # 100MHz
+ help
+ Override EFS SPI Speed Configuration to be applied based on certain
+ board version.
+
+config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD
+ hex
+ default 0x4 if BOARD_GOOGLE_GUYBRUSH
+ default 0xffffffff
+ help
+ Minimum board version starting which the Override EFS SPI Speed
+ configuration has to be applied.
+
endif # !EM100
config VARIANT_DIR
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc
index f3140dd..6bc3288 100644
--- a/src/mainboard/google/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/Makefile.inc
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),)
$(info APCB sources present.)
diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c
index c1621d9..a43b303 100644
--- a/src/mainboard/google/guybrush/chromeos.c
+++ b/src/mainboard/google/guybrush/chromeos.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <amdblocks/spi.h>
#include <baseboard/gpio.h>
#include <boardid.h>
#include <boot/coreboot_tables.h>
@@ -36,3 +37,11 @@
/* EC is trusted if not in RW. */
return !gpio_get(GPIO_EC_IN_RW);
}
+
+void mainboard_spi_fast_speed_override(uint8_t *fast_speed)
+{
+ uint32_t board_ver = board_id();
+
+ if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD)
+ *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED;
+}
--
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Gerrit-Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
Gerrit-Change-Number: 58117
Gerrit-PatchSet: 10
Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58114 )
Change subject: soc/amd/common/block/espi_util: Refactor eSPI Setup
......................................................................
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/cezanne/bootblock.c
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/picasso/early_fch.c
5 files changed, 17 insertions(+), 22 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index fc1c5e7c..c3cb138 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -92,12 +92,6 @@
set_caching();
write_resume_eip();
enable_pci_mmconf();
- /*
- * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
- * routing as early as possible
- */
- if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
- configure_port80_routing_early();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 7782d43..69458b6 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -32,22 +32,16 @@
sb_reset_i2c_peripherals(&reset_info);
}
-/* Initialize port80h routing early if needed */
-void configure_port80_routing_early(void)
-{
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
- mb_set_up_early_espi();
- espi_setup();
- }
-}
-
/* Before console init */
void fch_pre_init(void)
{
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
+ /* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
+ /* Setup eSPI to enable port80 routing. */
+ configure_espi();
fch_spi_early_init();
fch_smbus_init();
fch_enable_cf9_io();
@@ -80,7 +74,4 @@
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
-
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
- espi_setup();
}
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 8a1150e..8813707 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -111,7 +111,6 @@
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
-void configure_port80_routing_early(void);
void fch_pre_init(void);
void fch_early_init(void);
void fch_init(void *chip_info);
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index 9a563f9..7e49ea0 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -131,4 +131,15 @@
/* Run mainboard configuration needed to set up eSPI */
void mb_set_up_early_espi(void);
+/* Setup eSPI with any mainboard specific initialization. */
+static inline void configure_espi(void)
+{
+ /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform
+ port80h routing as early as possible. */
+ if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+ mb_set_up_early_espi();
+ espi_setup();
+ }
+}
+
#endif /* AMD_BLOCK_ESPI_H */
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index 3d1cd1b..8771e38 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -45,7 +45,10 @@
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
+ /* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
+ /* Setup eSPI to enable port80 routing. */
+ configure_espi();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
@@ -81,7 +84,4 @@
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
-
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
- espi_setup();
}
--
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Gerrit-Change-Number: 58114
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Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57782 )
Change subject: soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
......................................................................
soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/picasso/early_fch.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 9 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index bddcbee..7782d43 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -44,9 +44,11 @@
/* Before console init */
void fch_pre_init(void)
{
+ /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
+ the GPIO registers. */
+ enable_acpimmio_decode_pm04();
lpc_early_init();
fch_spi_early_init();
- enable_acpimmio_decode_pm04();
fch_smbus_init();
fch_enable_cf9_io();
fch_enable_legacy_io();
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index ae3aed2..3d1cd1b 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -42,13 +42,15 @@
/* Before console init */
void fch_pre_init(void)
{
+ /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
+ the GPIO registers. */
+ enable_acpimmio_decode_pm04();
lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
fch_spi_early_init();
- enable_acpimmio_decode_pm04();
fch_smbus_init();
fch_enable_cf9_io();
fch_enable_legacy_io();
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 7493770..de27ac5 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -328,6 +328,9 @@
{
int reboot = 0;
+ /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
+ the GPIO registers. */
+ enable_acpimmio_decode_pm04();
lpc_enable_rom();
sb_enable_lpc();
lpc_enable_port80();
@@ -335,7 +338,6 @@
lpc_enable_spi_prefetch();
sb_init_spi_base();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
- enable_acpimmio_decode_pm04();
fch_smbus_init();
fch_enable_cf9_io();
setup_spread_spectrum(&reboot);
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58236 )
Change subject: mb/google/hatch/var/scout: set correct i2c configuration
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/common/acpi: drop `RTC_EN` from static wake bits mask
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel: drop P_BLK support
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Attention is currently required from: Nico Huber, Paul Fagerburg, Julius Werner, Yu-Ping Wu.
Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58242 )
Change subject: libpayload: Add unit-tests framework and first test case
......................................................................
Patch Set 5:
(1 comment)
File payloads/libpayload/tests/Makefile.inc:
PS4:
> Changes you make in tests/Makefile.inc (to fix bugs, to add features) must now be synced up with this Makefile
True, but libpayload has separate build system. Look at coreboot/Makefile and libpayload/Makefile. Event tests of libpayload in util/testing/Makefile.inc are executed with `cd` at the beginning.
Moreover, in the near future libpayload might require vboot (in some builds), so it will complicate things when it comes to test targets generation and their dependencies.
For me it is easier to keep a copy of a test Makefile.inc in libpayload than to combine them both in one place. I cannot see more pros of merging those two, than (arguably) simpler maintenance. But if you have other arguments in favor of single framework for coreboot and libpayload, then tell me :)
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