coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/volteer: Update copano device tree
by Tim Wawrzynczak (Code Review) 06 Jan '21

06 Jan '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48952 ) Change subject: mb/google/volteer: Update copano device tree ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072 Gerrit-Change-Number: 48952 Gerrit-PatchSet: 7 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 06 Jan 2021 17:54:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/mandolin/mainboard: Remove unused pirq_data
by Raul Rangel (Code Review) 06 Jan '21

06 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48667 ) Change subject: mb/amd/mandolin/mainboard: Remove unused pirq_data ...................................................................... mb/amd/mandolin/mainboard: Remove unused pirq_data This table was wrong. It's also produced by the SoC now. BUG=b:170595019 TEST=None Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac --- M src/mainboard/amd/mandolin/mainboard.c 1 file changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48667/1 diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index b509282..0d208da 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -29,30 +29,6 @@ _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), "PIC and APIC FCH interrupt tables must be the same size"); -/* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; @@ -100,9 +76,6 @@ static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac Gerrit-Change-Number: 48667 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/mainboard: Remove unused pirq_data
by Raul Rangel (Code Review) 06 Jan '21

06 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48666 ) Change subject: mb/google/zork/mainboard: Remove unused pirq_data ...................................................................... mb/google/zork/mainboard: Remove unused pirq_data This table was wrong. It's also produced by the SoC now. BUG=b:170595019 TEST=Verify PCI IRQ: log messages Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536 --- M src/mainboard/google/zork/mainboard.c 1 file changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48666/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 824a87d..94a64bd 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -51,30 +51,6 @@ "PIC and APIC FCH interrupt tables must be the same size"); /* - * This table doesn't actually perform any routing. It only populates the - * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified - * in fch_apic_routing. The linux kernel only looks at this field as a backup - * if ACPI routing fails to describe the PCI routing correctly. The linux kernel - * also uses the APIC by default, so the value coded into the registers will be - * wrong. - * - * This table is also confusing because PCI Interrupt routing happens at the - * device/slot level, not the function level. - */ -static const struct pirq_struct mainboard_pirq_data[] = { - { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi - { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD - { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME - { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, - { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, -}; - -/* * This controls the device -> IRQ routing. * * Hardcoded IRQs: @@ -133,9 +109,6 @@ static void pirq_setup(void) { init_tables(); - - pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = fch_apic_routing; picr_data_ptr = fch_pic_routing; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536 Gerrit-Change-Number: 48666 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB PG for s0ix qualification
by Maulik V Vaghela (Code Review) 06 Jan '21

06 Jan '21

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB PG for s0ix qualification ...................................................................... Patch Set 3: -Code-Review (1 comment) https://review.coreboot.org/c/coreboot/+/49012/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/49012/2//COMMIT_MSG@9 PS2, Line 9: Enable USBSUSPGQDIS for s0ix qualification. > Description does not add more details than the commit message. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-Comment-Date: Wed, 06 Jan 2021 17:30:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB PG for s0ix qualification
by Maulik V Vaghela (Code Review) 06 Jan '21

06 Jan '21

Maulik V Vaghela has uploaded a new patch set (#3) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB PG for s0ix qualification ...................................................................... soc/intel/jasperlake: Enable USB PG for s0ix qualification USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB is not power gated. Disabling this bit will ensure that USB is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/49012/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Correctly populate the PCI interrupt line register
by Raul Rangel (Code Review) 06 Jan '21

06 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48665 ) Change subject: soc/amd/picasso: Correctly populate the PCI interrupt line register ...................................................................... soc/amd/picasso: Correctly populate the PCI interrupt line register The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 --- M src/soc/amd/picasso/fch.c A src/soc/amd/picasso/include/soc/pci.h M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48665/1 diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index cda509b..85e7788 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -22,6 +22,7 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> +#include <soc/pci.h> #include <soc/pci_devs.h> #include <soc/nvs.h> #include <types.h> @@ -251,6 +252,9 @@ /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + /* Write IRQs for all devicetree enabled devices */ write_pci_cfg_irqs(); } diff --git a/src/soc/amd/picasso/include/soc/pci.h b/src/soc/amd/picasso/include/soc/pci.h new file mode 100644 index 0000000..b6ff349 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/pci.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_PCI_H +#define AMD_PICASSO_PCI_H + +void populate_pirq_data(void); + +#endif /* AMD_PICASSO_PCI_H */ diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 1b65118..ca368f9 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -2,10 +2,12 @@ #include <acpi/acpigen.h> #include <assert.h> +#include <amdblocks/amd_pci_util.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <soc/pci.h> #include <soc/pci_devs.h> #include <stdio.h> @@ -34,6 +36,26 @@ {PCIE_GPP_B_DEVFN, 7, "CDAB"}, }; +/* + * This data structure is populated from the raw data above. It is used + * by amd/common/block/pci/amd_pci_util to write the PCI_INT_LINE register + * to each PCI device. + */ +static struct pirq_struct pirq_data[] = { + { PCIE_GPP_0_DEVFN }, + { PCIE_GPP_1_DEVFN }, + { PCIE_GPP_2_DEVFN }, + { PCIE_GPP_3_DEVFN }, + { PCIE_GPP_4_DEVFN }, + { PCIE_GPP_5_DEVFN }, + { PCIE_GPP_6_DEVFN }, + { PCIE_GPP_A_DEVFN }, + { PCIE_GPP_B_DEVFN }, +}; + +_Static_assert(ARRAY_SIZE(pci_routing_table) == ARRAY_SIZE(pirq_data), + "PCI and PIRQ tables must be the same size"); + static const struct pci_routing *get_pci_routing(unsigned int devfn) { for (size_t i = 0; i < ARRAY_SIZE(pci_routing_table); ++i) { @@ -53,6 +75,29 @@ return irq_index; } +void populate_pirq_data(void) +{ + const struct pci_routing *pci_routing; + struct pirq_struct *pirq; + unsigned int irq_index; + + for (size_t i = 0; i < ARRAY_SIZE(pirq_data); ++i) { + pirq = &pirq_data[i]; + pci_routing = get_pci_routing(pirq->devfn); + if (!pci_routing) + die("%s: devfn %u not found\n", __func__, pirq->devfn); + + for (size_t j = 0; j < 4; ++j) { + irq_index = calculate_irq(pci_routing, j); + + pirq->PIN[j] = irq_index % 8; + } + } + + pirq_data_ptr = pirq_data; + pirq_data_size = ARRAY_SIZE(pirq_data); +} + static const char *pcie_gpp_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) -- To view, visit https://review.coreboot.org/c/coreboot/+/48665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Gerrit-Change-Number: 48665 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Enable USBSUSPGQDIS for s0ix qualification
by Karthik Ramasubramanian (Code Review) 06 Jan '21

06 Jan '21

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USBSUSPGQDIS for s0ix qualification ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/49012/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/49012/2//COMMIT_MSG@9 PS2, Line 9: Enable USBSUSPGQDIS for s0ix qualification. Description does not add more details than the commit message. Can you please mention what this bit does? -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-Comment-Date: Wed, 06 Jan 2021 17:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Fix PCI routing table
by Raul Rangel (Code Review) 06 Jan '21

06 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48632 ) Change subject: soc/amd/picasso: Fix PCI routing table ...................................................................... soc/amd/picasso: Fix PCI routing table The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e --- M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/pci_int.asl M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 153 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48632/1 diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index a81d3b2..f6e198f 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -26,18 +26,6 @@ Package() { 0x0000FFFF, 0, INTC, 0 }, Package() { 0x0000FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridges */ - Package() { 0x0001FFFF, 0, INTA, 0 }, - Package() { 0x0001FFFF, 1, INTB, 0 }, - Package() { 0x0001FFFF, 2, INTC, 0 }, - Package() { 0x0001FFFF, 3, INTD, 0 }, - - /* Bus 0, Dev 0x08 - F[1:PCI Bridge to Bus A, 2: PCI Bridge to Bus B] */ - Package() { 0x0008FFFF, 0, INTA, 0 }, - Package() { 0x0008FFFF, 1, INTB, 0 }, - Package() { 0x0008FFFF, 2, INTC, 0 }, - Package() { 0x0008FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 0x14 - F[0:SMBus 3:LPC] */ Package() { 0x0014FFFF, 0, INTA, 0 }, Package() { 0x0014FFFF, 1, INTB, 0 }, diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/picasso/acpi/pci_int.asl index 2a2a561..4f723e9 100644 --- a/src/soc/amd/picasso/acpi/pci_int.asl +++ b/src/soc/amd/picasso/acpi/pci_int.asl @@ -104,3 +104,7 @@ PCI_LINK(INTB, PIRB, IORB) PCI_LINK(INTC, PIRC, IORC) PCI_LINK(INTD, PIRD, IORD) +PCI_LINK(INTE, PIRE, IORE) +PCI_LINK(INTF, PIRF, IORF) +PCI_LINK(INTG, PIRG, IORG) +PCI_LINK(INTH, PIRH, IORH) diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 96d33f2..80ef7e7 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <assert.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> @@ -8,6 +9,44 @@ #include <soc/pci_devs.h> #include <stdio.h> +/** + * Each PCI bridge has its INTx lines routed to one of the 8 GNB IOAPIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the + * interrupt are reduced modulo 8 on 8 interrupts (INTA-INTH) and forwarded to + * the FCH IOAPIC. + **/ +struct pci_routing { + unsigned int devfn; + unsigned int group; + const char intx[5]; +}; + +/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ +static const struct pci_routing pci_routing_table[] = { + {PCIE_GPP_0_DEVFN, 0, "ABCD"}, + {PCIE_GPP_1_DEVFN, 1, "ABCD"}, + {PCIE_GPP_2_DEVFN, 2, "ABCD"}, + {PCIE_GPP_3_DEVFN, 3, "ABCD"}, + {PCIE_GPP_4_DEVFN, 4, "ABCD"}, + {PCIE_GPP_5_DEVFN, 5, "ABCD"}, + {PCIE_GPP_6_DEVFN, 6, "ABCD"}, + {PCIE_GPP_A_DEVFN, 7, "ABCD"}, + {PCIE_GPP_B_DEVFN, 7, "CDAB"}, +}; + +static const struct pci_routing *get_pci_routing(const struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(pci_routing_table); ++i) { + printk(BIOS_ERR, "%s %s %d , %d\n", __func__, dev_path(dev), + dev->path.pci.devfn, pci_routing_table[i].devfn); + if (dev->path.pci.devfn == pci_routing_table[i].devfn) + return &pci_routing_table[i]; + } + + return NULL; +} + static const char *pcie_gpp_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) @@ -37,6 +76,114 @@ return NULL; } +static void acpigen_write_PRT(const struct device *dev) +{ + char link_template[] = "\\_SB.INTX"; + unsigned int irq_index; + + const struct pci_routing *pci_routing = get_pci_routing(dev); + if (pci_routing == NULL) { + printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); + return; + } + + acpigen_write_method("_PRT", 0); + acpigen_emit_byte(RETURN_OP); + + acpigen_write_package(4); + for (unsigned int i = 0; i < 4; ++i) { + irq_index = pci_routing->group * 4; + irq_index += pci_routing->intx[i] - 'A'; + + link_template[8] = 'A' + (irq_index % 8); + + acpigen_write_package(4); + acpigen_write_dword(0x0000FFFF); + acpigen_write_byte(i); + acpigen_emit_namestring(link_template); + acpigen_write_dword(0); + acpigen_pop_len(); + } + acpigen_pop_len(); /* Package */ + + acpigen_pop_len(); /* Method */ +} + +/* + * This function writes a PCI device with _ADR, _STA, and _PRT objects: + * Example: + * Scope (\_SB.PCI0) + * { + * Device (PBRA) + * { + * Name (_ADR, 0x0000000000080001) // _ADR: Address + * Method (_STA, 0, NotSerialized) // _STA: Status + * { + * Return (0x0F) + * } + * + * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.INTE, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.INTF, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.INTG, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.INTH, + * 0x00000000 + * } + * }) + * } + * } + * } + */ +static void acpi_device_write_gpp_pci_dev(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(dev->path.type == DEVICE_PATH_PCI); + assert(name); + assert(scope); + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_write_PRT(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + + static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -44,7 +191,7 @@ .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const unsigned short pci_device_ids[] = { @@ -66,7 +213,7 @@ .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const struct pci_driver external_pcie_gpp_driver __pci_driver = { -- To view, visit https://review.coreboot.org/c/coreboot/+/48632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Gerrit-Change-Number: 48632 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/root_complex: add missing set_resources
by Felix Held (Code Review) 06 Jan '21

06 Jan '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49120 ) Change subject: soc/amd/picasso/root_complex: add missing set_resources ...................................................................... soc/amd/picasso/root_complex: add missing set_resources The set_resources field in the root_complex_operations struct shouldn't be NULL, but a pointer to noop_set_resources instead. This fixes the error "PCI: 00:00.0 missing set_resources". Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/root_complex.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/49120/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 7ca44b0..045f30c 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -264,6 +264,7 @@ static struct device_operations root_complex_operations = { .read_resources = read_resources, + .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = root_complex_fill_ssdt, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/49120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070 Gerrit-Change-Number: 49120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/gpio_banks: fix sequence in gpio_output
by Felix Held (Code Review) 06 Jan '21

06 Jan '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49119 ) Change subject: soc/amd/common/block/gpio_banks: fix sequence in gpio_output ...................................................................... soc/amd/common/block/gpio_banks: fix sequence in gpio_output When configuring a GPIO pin as output the value should be written before it gets configures as an output to avoid a possible glitch on the output when the GPIO pin was an input before and the output value was different from the one that got written afterwards. Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/49119/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 03804d5..bdc243f 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -162,8 +162,9 @@ void gpio_output(gpio_t gpio_num, int value) { - gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); + /* set GPIO output value before setting the direction to output to avoid glitches */ gpio_set(gpio_num, value); + gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); } const char *gpio_acpi_path(gpio_t gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/49119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9 Gerrit-Change-Number: 49119 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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