coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/clevo/l140cu: Move FSP-M config hook to mainboard level
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49077 ) Change subject: mb/clevo/l140cu: Move FSP-M config hook to mainboard level ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/49077/4/src/mainboard/clevo/cml-u/… File src/mainboard/clevo/cml-u/romstage.c: https://review.coreboot.org/c/coreboot/+/49077/4/src/mainboard/clevo/cml-u/… PS4, Line 6: ry_init_params(FSPM_UPD *memupd) : { : variant_configure_fspm(memupd); : } : > I can put this into the commit message, if you want. agreed -- To view, visit https://review.coreboot.org/c/coreboot/+/49077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Gerrit-Change-Number: 49077 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Jan 2021 19:47:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: > Patch Set 3: -Code-Review > > > Patch Set 3: Code-Review-1 > > > > > Patch Set 3: Code-Review+2 > > > > > > wait... did I really forget SKL? 😮 > > > > It was using PMC, not LPIT. Is that a problem? > > No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine? No, I reworked that. PMC/LPID/LPIT was actually confusing. PEP(D) is the "right" (or more correct) device name for this, so I cleaned this up but obviously forgot to add it to SKL as well 😄 LPIT is related but a (very) different table, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Jan 2021 19:38:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Move MAX_CPUS from mb to SoC
by Felix Singer (Code Review) 06 Jan '21

06 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49122 ) Change subject: soc/intel/broadwell: Move MAX_CPUS from mb to SoC ...................................................................... soc/intel/broadwell: Move MAX_CPUS from mb to SoC Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/purism/librem_bdw/Kconfig 3 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/49122/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 8e49255..5301e32 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -58,10 +58,6 @@ default "samus" if BOARD_GOOGLE_SAMUS default "" -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 5955565..b04cc46 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -39,10 +39,6 @@ default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config MAX_CPUS - int - default 8 - config VGA_BIOS_FILE string default "pci8086,0406.rom" diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 275594b..ad764b7 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -52,10 +52,6 @@ default "1.0" if BOARD_PURISM_LIBREM13_V1 default "2.0" if BOARD_PURISM_LIBREM15_V2 -config MAX_CPUS - int - default 8 - config PRE_GRAPHICS_DELAY int default 50 -- To view, visit https://review.coreboot.org/c/coreboot/+/49122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Gerrit-Change-Number: 49122 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Configure MAX_CPUS
by Felix Singer (Code Review) 06 Jan '21

06 Jan '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49105 ) Change subject: soc/intel/skylake: Configure MAX_CPUS ...................................................................... soc/intel/skylake: Configure MAX_CPUS Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/Kconfig M src/mainboard/asrock/h110m/Kconfig M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/soc/intel/skylake/Kconfig 14 files changed, 4 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/49105/1 diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index 824e8b3..efd21da 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -28,10 +28,6 @@ string default "51nb/x210" -config MAX_CPUS - int - default 8 - config VGA_BIOS_ID string default "8086,5917" diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index d923c30..8b32ac6 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -29,10 +29,6 @@ string default "H110M" -config MAX_CPUS - int - default 8 - config DEVICETREE string default "devicetree.cb" diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index ed0600a..d854db4 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -55,10 +55,6 @@ # default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB # default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index ece0119..af5f8cd 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -62,10 +62,6 @@ string default "Google_Eve" -config MAX_CPUS - int - default 8 - config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_RT5514 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 548f2eb..afa8f90 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -60,10 +60,6 @@ default "Google_Kalista" if BOARD_GOOGLE_KARMA default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 144fe97..bd4e649 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -65,10 +65,6 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 2656d28..134246c 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -108,10 +108,6 @@ default "Rammus" if BOARD_GOOGLE_RAMMUS default "Soraka" if BOARD_GOOGLE_SORAKA -config MAX_CPUS - int - default 8 - config OEM_BIN_FILE string "OEM ID table" default "" diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 5dccdae..fcce402 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -43,10 +43,6 @@ string default "Intel_Kblrvp" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index b9b7d5a..cf67ca1 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -41,10 +41,6 @@ string default "Intel_Kunimitsu" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 873f257..e7aaae5 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -32,10 +32,6 @@ string default "Intel_SaddleBrook" -config MAX_CPUS - int - default 8 - config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index 437c5a3..8297929 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -46,10 +46,6 @@ hex default 0x600000 if BOARD_SIEMENS_BOXER26 -config MAX_CPUS - int - default 8 - config DIMM_MAX int default 2 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index cd8fc66..c59f7fa 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -47,10 +47,6 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config MAX_CPUS - int - default 8 - config VGA_BIOS_ID string default "8086,1916" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 533899d..b7057b0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -75,10 +75,6 @@ int default 18 -config MAX_CPUS - int - default 8 - config CONSOLE_POST bool default y diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index cfc7c52..0a14bc7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -80,6 +80,10 @@ select UDELAY_TSC select UDK_2015_BINDING +config MAX_CPUS + int + default 8 + config FSP_HYPERTHREADING bool "Enable Hyper-Threading" default y -- To view, visit https://review.coreboot.org/c/coreboot/+/49105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Gerrit-Change-Number: 49105 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8
by Angel Pons (Code Review) 06 Jan '21

06 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46952 ) Change subject: mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 ...................................................................... mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 Haswell and Broadwell have at most 8 threads. Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/wtm2/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46952/1 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 61d7657..bb0fdf4 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -29,7 +29,7 @@ config MAX_CPUS int - default 16 + default 8 config VGA_BIOS_FILE string -- To view, visit https://review.coreboot.org/c/coreboot/+/46952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Gerrit-Change-Number: 46952 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 06 Jan '21

06 Jan '21

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: -Code-Review > Patch Set 3: Code-Review-1 > > > Patch Set 3: Code-Review+2 > > > > wait... did I really forget SKL? 😮 > > It was using PMC, not LPIT. Is that a problem? No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine? -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Jan 2021 19:11:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Benjamin Doron (Code Review) 06 Jan '21

06 Jan '21

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: Code-Review-1 > Patch Set 3: Code-Review+2 > > wait... did I really forget SKL? 😮 It was using PMC, not LPIT. Is that a problem? -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Jan 2021 19:05:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

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Change in coreboot[master]: mb/google/volteer/var/voema: Update Aux settings for Port 0
by David Wu (Code Review) 06 Jan '21

06 Jan '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48976 ) Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ...................................................................... mb/google/volteer/var/voema: Update Aux settings for Port 0 On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48976/1 diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index f612beb..640f57d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,6 +5,10 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Disable WLAN PCIE 7 register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" @@ -104,8 +108,6 @@ chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn -- To view, visit https://review.coreboot.org/c/coreboot/+/48976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Gerrit-Change-Number: 48976 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49125 ) Change subject: soc/intel/{common,adl}: drop unneeded Kconfig PMC_LOW_POWER_MODE_PROGRAM ...................................................................... Abandoned ok... now I know why this was introduced... could be fixed by implementing pmc_mmio_regs in APL or just using (uint32_t *)soc_read_pmc_base() -- I expect ADL to gain the Tco fsp option later, when Fsp get's released, so this code will probably vanish anyways. -- To view, visit https://review.coreboot.org/c/coreboot/+/49125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1ffb0ee0078e923fbaeaca640d215408b8f4ec8 Gerrit-Change-Number: 49125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit January 2021