coreboot-gerrit January 2021

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Change in coreboot[master]: chmod -x
by Yu-Ping Wu (Code Review) 06 Jan '21

06 Jan '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48199 ) Change subject: chmod -x ...................................................................... chmod -x Change-Id: I101ab3ed5a31d8ef008bcf198ef13373455cbddf --- M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/include/soc/dramc_param.h M src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h 4 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/48199/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c old mode 100755 new mode 100644 diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c old mode 100755 new mode 100644 diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h old mode 100755 new mode 100644 diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h old mode 100755 new mode 100644 -- To view, visit https://review.coreboot.org/c/coreboot/+/48199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I101ab3ed5a31d8ef008bcf198ef13373455cbddf Gerrit-Change-Number: 48199 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: rtc: Use `bool` as return type
by Yidi Lin (Code Review) 06 Jan '21

06 Jan '21

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49137 ) Change subject: soc/mediatek: rtc: Use `bool` as return type ...................................................................... soc/mediatek: rtc: Use `bool` as return type TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot boot to shell on Asurada BUG=b:176307061 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24 --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8173/include/soc/rtc.h M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8192/include/soc/rtc.h M src/soc/mediatek/mt8192/rtc.c 8 files changed, 61 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/49137/1 diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 7ddb8df..4a86431 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -6,6 +6,7 @@ #include <bcd.h> #include <console/console.h> #include <rtc.h> +#include <stdbool.h> #define RTCTAG "[RTC]" #define rtc_info(fmt, arg ...) printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \ @@ -94,14 +95,13 @@ }; /* external API */ -int rtc_busy_wait(void); -int rtc_write_trigger(void); -int rtc_writeif_unlock(void); -int rtc_xosc_write(u16 val); -int rtc_lpen(u16 con); -int rtc_reg_init(void); +bool rtc_write_trigger(void); +bool rtc_writeif_unlock(void); +bool rtc_xosc_write(u16 val); +bool rtc_lpen(u16 con); +bool rtc_reg_init(void); void rtc_osc_init(void); -int rtc_powerkey_init(void); +bool rtc_powerkey_init(void); void rtc_boot_common(void); #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index 95bd13b..f36bbc5 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -5,7 +5,7 @@ #include <timer.h> /* ensure rtc write success */ -int rtc_busy_wait(void) +static bool rtc_busy_wait(void) { struct stopwatch sw; u16 bbpu; @@ -17,30 +17,30 @@ /* Time > 1sec, time out and set recovery mode enable.*/ if (stopwatch_expired(&sw)) { rtc_info("BBPU CBUSY time out !!\n"); - return 0; + return false; } } while (bbpu & RTC_BBPU_CBUSY); - return 1; + return true; } -int rtc_write_trigger(void) +bool rtc_write_trigger(void) { rtc_write(RTC_WRTGR, 1); return rtc_busy_wait(); } /* unlock rtc write interface */ -int rtc_writeif_unlock(void) +bool rtc_writeif_unlock(void) { rtc_write(RTC_PROT, RTC_PROT_UNLOCK1); if (!rtc_write_trigger()) - return 0; + return false; rtc_write(RTC_PROT, RTC_PROT_UNLOCK2); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } /* set rtc time */ @@ -71,20 +71,20 @@ } /* set rtc xosc setting */ -int rtc_xosc_write(u16 val) +bool rtc_xosc_write(u16 val) { u16 bbpu; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); if (!rtc_busy_wait()) - return 0; + return false; rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); if (!rtc_busy_wait()) - return 0; + return false; rtc_write(RTC_OSC32CON, val); if (!rtc_busy_wait()) - return 0; + return false; rtc_read(RTC_BBPU, &bbpu); bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD; @@ -94,31 +94,31 @@ } /* enable lpd subroutine */ -int rtc_lpen(u16 con) +bool rtc_lpen(u16 con) { con &= ~RTC_CON_LPRST; rtc_write(RTC_CON, con); if (!rtc_write_trigger()) - return 0; + return false; con |= RTC_CON_LPRST; rtc_write(RTC_CON, con); if (!rtc_write_trigger()) - return 0; + return false; con &= ~RTC_CON_LPRST; rtc_write(RTC_CON, con); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } /* initialize rtc related registers */ -int rtc_reg_init(void) +bool rtc_reg_init(void) { u16 irqsta; @@ -136,7 +136,7 @@ rtc_write(RTC_DIFF, 0); rtc_write(RTC_CALI, 0); if (!rtc_write_trigger()) - return 0; + return false; rtc_read(RTC_IRQ_STA, &irqsta); /* read clear */ @@ -153,7 +153,7 @@ } /* write powerkeys to enable rtc functions */ -int rtc_powerkey_init(void) +bool rtc_powerkey_init(void) { rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h index bb9425f..e82d514 100644 --- a/src/soc/mediatek/mt8173/include/soc/rtc.h +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -5,6 +5,7 @@ #include <soc/pmic_wrap_common.h> #include <soc/rtc_common.h> +#include <stdbool.h> #include <stdint.h> #include "mt6391.h" diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 94ec421..d60f722 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -10,7 +10,7 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) /* initialize rtc related gpio */ -static int rtc_gpio_init(void) +static bool rtc_gpio_init(void) { u16 con; @@ -41,21 +41,21 @@ } /* low power detect setting */ -static int rtc_lpd_init(void) +static bool rtc_lpd_init(void) { pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0); if (!rtc_write_trigger()) - return 0; + return false; pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0); if (!rtc_write_trigger()) - return 0; + return false; pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } /* rtc init check */ diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index f7c189f..7ca054a 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -5,6 +5,7 @@ #include <soc/pmic_wrap_common.h> #include <soc/rtc_common.h> +#include <stdbool.h> /* RTC registers */ enum { @@ -205,7 +206,7 @@ /* external API */ void rtc_bbpu_power_on(void); int rtc_init(int recover); -int rtc_gpio_init(void); +bool rtc_gpio_init(void); void rtc_boot(void); u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); void mt6358_dcxo_disable_unused(void); diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 41dc5c0..e90aa9d 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -11,7 +11,7 @@ #define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) /* initialize rtc setting of using dcxo clock */ -static int rtc_enable_dcxo(void) +static bool rtc_enable_dcxo(void) { u16 bbpu, con, osc32con, sec; @@ -22,7 +22,7 @@ mdelay(1); if (!rtc_writeif_unlock()) { rtc_info("rtc_writeif_unlock() failed\n"); - return 0; + return false; } rtc_read(RTC_OSC32CON, &osc32con); @@ -32,7 +32,7 @@ | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; if (!rtc_xosc_write(osc32con)) { rtc_info("rtc_xosc_write() failed\n"); - return 0; + return false; } rtc_read(RTC_CON, &con); @@ -40,11 +40,11 @@ rtc_read(RTC_AL_SEC, &sec); rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec); - return 1; + return true; } /* initialize rtc related gpio */ -int rtc_gpio_init(void) +bool rtc_gpio_init(void) { u16 con; @@ -115,7 +115,7 @@ rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); if (stopwatch_expired(&sw)) { rtc_info("get frequency time out !!\n"); - return 0; + return false; } } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); @@ -143,7 +143,7 @@ } /* low power detect setting */ -static int rtc_lpd_init(void) +static bool rtc_lpd_init(void) { u16 con, sec; @@ -152,19 +152,19 @@ sec |= RTC_LPD_OPT_F32K_CK_ALIVE; rtc_write(RTC_AL_SEC, sec); if (!rtc_write_trigger()) - return 0; + return false; /* init XOSC32 to detect 32k clock stop */ rtc_read(RTC_CON, &con); con |= RTC_CON_XOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; /* init EOSC32 to detect rtc low power */ rtc_read(RTC_CON, &con); con |= RTC_CON_EOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; rtc_read(RTC_CON, &con); con &= ~RTC_CON_XOSC32_LPEN; @@ -176,9 +176,9 @@ sec |= RTC_LPD_OPT_EOSC_LPD; rtc_write(RTC_AL_SEC, sec); if (!rtc_write_trigger()) - return 0; + return false; - return 1; + return true; } static bool rtc_hw_init(void) diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h index a26f893..440c30c 100644 --- a/src/soc/mediatek/mt8192/include/soc/rtc.h +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_RTC_H #include <soc/pmif.h> +#include <stdbool.h> /* RTC registers */ enum { @@ -226,7 +227,7 @@ void rtc_write(u16 addr, u16 wdata); void rtc_bbpu_power_on(void); int rtc_init(int recover); -int rtc_gpio_init(void); +bool rtc_gpio_init(void); void rtc_boot(void); u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); void mt6359_dcxo_disable_unused(void); diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c index ffb9a5c..f978202 100644 --- a/src/soc/mediatek/mt8192/rtc.c +++ b/src/soc/mediatek/mt8192/rtc.c @@ -42,11 +42,11 @@ } /* initialize rtc setting of using dcxo clock */ -static int rtc_enable_dcxo(void) +static bool rtc_enable_dcxo(void) { if (!rtc_writeif_unlock()) { rtc_info("rtc_writeif_unlock() failed\n"); - return 0; + return false; } u16 bbpu, con, osc32con, sec; @@ -59,18 +59,18 @@ if (!rtc_xosc_write(osc32con)) { rtc_info("rtc_xosc_write() failed\n"); - return 0; + return false; } rtc_read(RTC_CON, &con); rtc_read(RTC_OSC32CON, &osc32con); rtc_read(RTC_AL_SEC, &sec); rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec); - return 1; + return true; } /* initialize rtc related gpio */ -int rtc_gpio_init(void) +bool rtc_gpio_init(void) { u16 con; @@ -135,7 +135,7 @@ rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); if (stopwatch_expired(&sw)) { rtc_info("get frequency time out!\n"); - return 0; + return false; } } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); @@ -163,7 +163,7 @@ } /* low power detect setting */ -static int rtc_lpd_init(void) +static bool rtc_lpd_init(void) { u16 con, sec; @@ -173,26 +173,26 @@ rtc_write(RTC_AL_SEC, sec); if (!rtc_write_trigger()) - return 0; + return false; /* init XOSC32 to detect 32k clock stop */ rtc_read(RTC_CON, &con); con |= RTC_CON_XOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; /* init EOSC32 to detect rtc low power */ rtc_read(RTC_CON, &con); con |= RTC_CON_EOSC32_LPEN; if (!rtc_lpen(con)) - return 0; + return false; rtc_read(RTC_CON, &con); rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con); - return 1; + return true; } static bool rtc_hw_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24 Gerrit-Change-Number: 49137 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Angel Pons (Code Review) 06 Jan '21

06 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… PS5, Line 12: - eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD > I will have to rebase and check. (They worked on Linux, which was good enough for me. […] I suspect the backlight is currently controlled through i915's own backlight interface in sysfs. https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/gpio.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 98: PAD_NC(GPP_C20, UP_20K), // UART2_RXD (test point) : PAD_NC(GPP_C21, UP_20K), // UART2_TXD (test point) > Changing these back to NF. Should I move them to early_gpio. […] Yes please, for the sake of completeness https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 25: 0 > What do you mean by synchronized? […] Ideally, this would be set in SoC code depending on ONBOARD_VGA_IS_PRIMARY. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Jan 2021 00:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
by Tim Crawford (Code Review) 06 Jan '21

06 Jan '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49172 ) Change subject: soc/intel/cannonlake: Allow RP#1 usage for ClkSrc ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/49172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Gerrit-Change-Number: 49172 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jan 2021 00:12:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 06 Jan '21

06 Jan '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 5: (8 comments) https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… File Documentation/mainboard/system76/oryp5.md: https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… PS5, Line 12: - eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD > Does backlight control work properly? I'd suggest testing under Windows. […] I will have to rebase and check. (They worked on Linux, which was good enough for me.) https://review.coreboot.org/c/coreboot/+/47892/5/Documentation/mainboard/sy… PS5, Line 15: 2666 MHz > DDR4-2666 runs at 1333 MHz, or 2666 MT/s. These are from the marketing material, which it seems most vendors use MHz instead of MT/s. I will probably change this to the channel 0/1 format used in the lemp0 documentation. https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/Kconfig: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 12: HAVE_SMI_HANDLER > Isn't this selected elsewhere? Selected by the SOC, will remove. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 26: register "SaGv" = "SaGv_Enabled" > Halo is the name of high-performance BGA CPUs. That is, the models ending in H, such as i7-9750H. […] SaGv is enabled on the RVP. (It was copied from CNL RVP, so a chance it was just overlooked?) https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 41: WARNING: must then be mapped from FSP value to PCH value > Did you (or whoever originally wrote this) mean `from PCH value to FSP value`? Potentially. But I'm more inclined to just remove the comments like this. They may be useful in a guide for porting a board, but not really as comments in *every* board (what we currently have). https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/gpio.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 98: PAD_NC(GPP_C20, UP_20K), // UART2_RXD (test point) : PAD_NC(GPP_C21, UP_20K), // UART2_TXD (test point) > This conflicts with the devicetree setting Changing these back to NF. Should I move them to early_gpio.c as well? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/hda_verb.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 25: // Enable DMIC microphone on ALC1220 : 0x02050036, : 0x02042a6a, > I guess people put these here because the cim_verb_data format only allows groups of 4 DWORDs. […] The ALC1220 spec we got doesn't have the supported verbs, so I can't even confirm what these actually do. https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/5/src/mainboard/system76/ory… PS5, Line 25: 0 > Shouldn't this be synchronized with ONBOARD_VGA_IS_PRIMARY in SoC code? What do you mean by synchronized? I probably don't need this set at all. Will remove it if default of AUTO works. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Jan 2021 00:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB PG for s0ix qualification
by Furquan Shaikh (Code Review) 06 Jan '21

06 Jan '21

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB PG for s0ix qualification ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/c/coreboot/+/49012/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/49012/3//COMMIT_MSG@10 PS3, Line 10: USB is not power gated "USB PHY SUS well" since there are more than one qualification bits for USB. Also, is this USB2 or both USB2 and USB3? https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/f… File src/soc/intel/jasperlake/finalize.c: https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/f… PS3, Line 69: * Can you please add a comment here indicating why this is required? It will be helpful when someone looks at this code later. https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/f… PS3, Line 71: USBSUSPGQDIS Not for this change, but I think we should do the configuration of disqualification bits (CPPMVRIC1/2/3) in coreboot for all platforms. On every platform, we keep running into this and tweak a couple of bits to make things work. Instead we should evaluate all the bits and determine when one would want to set a particular bit. https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/i… File src/soc/intel/jasperlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/i… PS3, Line 125: Use space like other entries here. https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/i… PS3, Line 126: Use space like other entries and align like XTALSDQDIS above. -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Jan 2021 21:35:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Enable USB PG for s0ix qualification
by Karthik Ramasubramanian (Code Review) 06 Jan '21

06 Jan '21

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 ) Change subject: soc/intel/jasperlake: Enable USB PG for s0ix qualification ...................................................................... Patch Set 3: Code-Review+2 Ensured that the system enters S0ix under all the following scenarios: 1) No USB peripherals attached 2) USB Type-C to Ethernet dongle and servo attached on both USB-C ports 3) USB Keyboard connected 4) USB Storage connected (USB2, USB 3.0, USB 3.1) 5) BT mouse connected 6) With all the peripherals in 2), 3), 4) & 5). Ensured that under all the above conditions system can wake to the following wake sources: 1) Internal Keyboard 2) USB Keyboard 3) RTC Alarm 4) BT 5) AC connect/disconnect 6) Trackpad 7) WLAN -- To view, visit https://review.coreboot.org/c/coreboot/+/49012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Gerrit-Change-Number: 49012 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Vaidya <deepti.vaidya(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Jan 2021 21:23:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 06 Jan '21

06 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: -Code-Review > > > > > Patch Set 3: Code-Review-1 > > > > > > > Patch Set 3: Code-Review+2 > > > > > > > > wait... did I really forget SKL? 😮 > > > > > > It was using PMC, not LPIT. Is that a problem? > > > > No, vendor firmware for my Skylake board uses both devices as well. So this seems to be fine? > > No, I reworked that. PMC/LPID/LPIT was actually confusing. PEP(D) is the "right" (or more correct) device name for this, so I cleaned this up but obviously forgot to add it to SKL as well 😄 > > LPIT is related but a (very) different table, though. Öh oh well, actually that PMC that you mean (src/soc/intel/skylake/acpi/pmc.asl) is the "real" PMC. The "pmc.asl" (iirc the name correctly) was implementing LPID/PEPD. That was what I cleaned up. -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Jan 2021 20:00:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation
by Furquan Shaikh (Code Review) 06 Jan '21

06 Jan '21

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49134 ) Change subject: mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigation ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/49134/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/49134/5//COMMIT_MSG@17 PS5, Line 17: correct value has been programmed and slew rate measurement : is correct on scope. What about the noise? https://review.coreboot.org/c/coreboot/+/49134/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/49134/5/src/mainboard/google/deded… PS5, Line 70: 1 Can you please add enums for this in chip.h? I think it is much simpler to read and understand what the settings are. -- To view, visit https://review.coreboot.org/c/coreboot/+/49134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Gerrit-Change-Number: 49134 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Jan 2021 20:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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