coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/dedede/var/magolor: Enable EC keyboard backlight
by Tim Chen (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Tim Chen. Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49340 to review the following change. Change subject: mb/google/dedede/var/magolor: Enable EC keyboard backlight ...................................................................... mb/google/dedede/var/magolor: Enable EC keyboard backlight BUG=b:177288782 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/49340/1 diff --git a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h index 08870e0..27c930d 100644 --- a/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h +++ b/src/mainboard/google/dedede/variants/magolor/include/variant/ec.h @@ -5,4 +5,7 @@ #include <baseboard/ec.h> +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/49340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7 Gerrit-Change-Number: 49340 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add SPI QUP driver
by Ravi kumar (Code Review) 12 Jan '21

12 Jan '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49339 ) Change subject: sc7280: Add SPI QUP driver ...................................................................... sc7280: Add SPI QUP driver This implements the SPI driver for the QUP core. Change-Id: If586970c20da97f3385cc68c4204ac8217b0f617 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/include/soc/qupv3_spi.h A src/soc/qualcomm/sc7280/qupv3_spi.c M src/soc/qualcomm/sc7280/spi.c 4 files changed, 249 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/49339/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index acbb36d..b0aa8b2 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += qupv3_spi.c bootblock-$(CONFIG_SC7280_QSPI) += qspi.c bootblock-y += clock.c bootblock-y += gpio.c @@ -16,6 +17,7 @@ ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += qupv3_spi.c verstage-$(CONFIG_SC7280_QSPI) += qspi.c verstage-y += clock.c verstage-y += gpio.c @@ -31,6 +33,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-y += qupv3_spi.c romstage-$(CONFIG_SC7280_QSPI) += qspi.c romstage-y += clock.c romstage-y += gpio.c @@ -43,6 +46,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-y += qupv3_spi.c ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ramstage-y += clock.c ramstage-y += gpio.c diff --git a/src/soc/qualcomm/sc7280/include/soc/qupv3_spi.h b/src/soc/qualcomm/sc7280/include/soc/qupv3_spi.h new file mode 100644 index 0000000..87c81fa --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qupv3_spi.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SPI_QUP_QCOM_HEADER___ +#define __SPI_QUP_QCOM_HEADER___ + +#include <spi-generic.h> + +int qup_spi_claim_bus(const struct spi_slave *slave); +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in); +void qup_spi_release_bus(const struct spi_slave *slave); +void qup_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /*__SPI_QUP_QCOM_HEADER___*/ diff --git a/src/soc/qualcomm/sc7280/qupv3_spi.c b/src/soc/qualcomm/sc7280/qupv3_spi.c new file mode 100644 index 0000000..d086a27 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qupv3_spi.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <lib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/qcom_qup_se.h> +#include <soc/qupv3_config.h> +#include <soc/qupv3_spi.h> +#include <types.h> + +/* SE_SPI_LOOPBACK register fields */ +#define LOOPBACK_ENABLE 0x1 + +/* SE_SPI_WORD_LEN register fields */ +#define WORD_LEN_MSK GENMASK(9, 0) +#define MIN_WORD_LEN 4 + +/* SPI_TX/SPI_RX_TRANS_LEN fields */ +#define TRANS_LEN_MSK GENMASK(23, 0) + +/* M_CMD OP codes for SPI */ +#define SPI_TX_ONLY 1 +#define SPI_RX_ONLY 2 +#define SPI_FULL_DUPLEX 3 +#define SPI_TX_RX 7 +#define SPI_CS_ASSERT 8 +#define SPI_CS_DEASSERT 9 +#define SPI_SCK_ONLY 10 + +/* M_CMD params for SPI */ +/* If fragmentation bit is set then CS will not toggle after each transfer */ +#define M_CMD_FRAGMENTATION BIT(2) + +#define BITS_PER_BYTE 8 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +#define IRQ_TRIGGER (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN | \ + M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN | \ + M_CMD_CANCEL_EN | M_CMD_ABORT_EN) + +static void setup_fifo_params(const struct spi_slave *slave) +{ + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + u32 word_len = 0; + + /* Disable loopback mode */ + write32(&regs->proto_loopback_cfg, 0); + + write32(&regs->spi_demux_sel, slave->cs); + word_len = ((BITS_PER_WORD - MIN_WORD_LEN) & WORD_LEN_MSK); + write32(&regs->spi_word_len, word_len); + + /* FIFO PACKING CONFIGURATION */ + write32(&regs->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); +} + +static void qup_setup_m_cmd(unsigned int se_bus, u32 cmd, u32 params) +{ + struct qup_regs *regs = qup[se_bus].regs; + u32 m_cmd = (cmd << M_OPCODE_SHFT); + + m_cmd |= (params & M_PARAMS_MSK); + write32(&regs->geni_m_cmd0, m_cmd); +} + +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + u32 m_cmd = 0; + u32 m_param = M_CMD_FRAGMENTATION; + int size; + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + + if ((bytes_in == 0) && (bytes_out == 0)) + return 0; + + setup_fifo_params(slave); + + if (!bytes_out) { + size = bytes_in; + m_cmd = SPI_RX_ONLY; + dout = NULL; + } else if (!bytes_in) { + size = bytes_out; + m_cmd = SPI_TX_ONLY; + din = NULL; + } else { + size = MIN(bytes_in, bytes_out); + m_cmd = SPI_FULL_DUPLEX; + } + + /* Check for maximum permissible transfer length */ + assert(!(size & ~TRANS_LEN_MSK)); + + if (bytes_out) { + write32(&regs->spi_tx_trans_len, size); + write32(&regs->geni_tx_watermark_reg, TX_WATERMARK); + } + if (bytes_in) + write32(&regs->spi_rx_trans_len, size); + + qup_setup_m_cmd(se_bus, m_cmd, m_param); + + if (qup_handle_transfer(se_bus, dout, din, size)) + return -1; + + qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0), + din + size, MAX((int)bytes_in - size, 0)); + + return 0; +} + +static int spi_qup_set_cs(const struct spi_slave *slave, bool enable) +{ + u32 m_cmd = 0; + u32 m_irq = 0; + unsigned int se_bus = slave->bus; + struct stopwatch sw; + + m_cmd = (enable) ? SPI_CS_ASSERT : SPI_CS_DEASSERT; + qup_setup_m_cmd(se_bus, m_cmd, 0); + + stopwatch_init_usecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(se_bus); + if (m_irq & M_CMD_DONE_EN) { + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + break; + } + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN)) { + printk(BIOS_INFO, "%s:Failed to %s chip\n", __func__, + (enable) ? "Assert" : "Deassert"); + qup_m_cancel_and_abort(se_bus); + return -1; + } + return 0; +} + +void qup_spi_init(unsigned int bus, unsigned int speed_hz) +{ + u32 m_clk_cfg = 0, div = DEFAULT_SE_CLK / speed_hz; + struct qup_regs *regs = qup[bus].regs; + + /* Make sure div can hit target frequency within +/- 1KHz range */ + assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); + qupv3_se_fw_load_and_init(bus, SE_PROTOCOL_SPI, MIXED); + clock_enable_qup(bus); + m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); + write32(&regs->geni_ser_m_clk_cfg, m_clk_cfg); + /* Mode:0, cpha=0, cpol=0 */ + write32(&regs->spi_cpha, 0); + write32(&regs->spi_cpol, 0); + + /* Serial engine IO initialization */ + write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(&regs->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(&regs->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(&regs->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(&regs->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(&regs->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(&regs->geni_rx_watermark_reg, 0); + write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_NO_PULL, + GPIO_6MA, GPIO_INPUT); /* MISO */ + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* MOSI */ + gpio_configure(qup[bus].pin[2], qup[bus].func[2], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CLK */ + gpio_configure(qup[bus].pin[3], qup[bus].func[3], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CS */ + + /* Select and setup FIFO mode */ + write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); + write32(&regs->geni_s_irq_clear, 0xFFFFFFFF); + write32(&regs->dma_tx_irq_clr, 0xFFFFFFFF); + write32(&regs->dma_rx_irq_clr, 0xFFFFFFFF); + write32(&regs->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(&regs->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits32(&regs->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +int qup_spi_claim_bus(const struct spi_slave *slave) +{ + return spi_qup_set_cs(slave, 1); +} + +void qup_spi_release_bus(const struct spi_slave *slave) +{ + spi_qup_set_cs(slave, 0); +} diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c index 61ccd86..bd832d7 100644 --- a/src/soc/qualcomm/sc7280/spi.c +++ b/src/soc/qualcomm/sc7280/spi.c @@ -3,6 +3,7 @@ #include <spi-generic.h> #include <spi_flash.h> #include <soc/qspi.h> +#include <soc/qupv3_spi.h> static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = sc7280_claim_bus, @@ -12,12 +13,24 @@ .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 15, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/49339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If586970c20da97f3385cc68c4204ac8217b0f617 Gerrit-Change-Number: 49339 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd: Create new folder for SPD files
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49338 ) Change subject: spd: Create new folder for SPD files ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: woops,link not allowed Report any symbolic links (lint-stable-018-symlinks): src/spd/ddr4/tgl src/spd/lp4x/adl src/spd/lp4x/jsl src/spd/lp4x/tgl test failed -- To view, visit https://review.coreboot.org/c/coreboot/+/49338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a871981642485020adaeaafd062f718c636a708 Gerrit-Change-Number: 49338 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 08:01:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voema: Add camera ACPI configuration
by Jim Lai (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: David Wu, Nick Vaccaro. Jim Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49302 ) Change subject: mb/google/volteer/var/voema: Add camera ACPI configuration ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e Gerrit-Change-Number: 49302 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Yeh <andy.yeh(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 08:00:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/pcie: Add helper function for getting mask of enable...
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48968 ) Change subject: soc/intel/common/pcie: Add helper function for getting mask of enabled ports ...................................................................... soc/intel/common/pcie: Add helper function for getting mask of enabled ports This change adds a helper function `pcie_rp_enable_mask()` that returns a 32-bit mask indicating the status (enabled/disabled) of PCIe root ports (in the groups table) as configured by the mainboard in the device tree. With this helper function, SoC chip config does not need to add another `PcieRpEnable[]` config to identify what root ports are enabled. Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie_helpers.c 3 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48968/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index ca50b13..264c43f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -3,6 +3,8 @@ #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H +#include <stdint.h> + /* * The PCIe Root Ports usually come in groups of up to 8 PCI-device * functions. @@ -34,4 +36,17 @@ */ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); +/* + * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in the same order + * as the root ports in pcie_rp_group groups table. + * + * Thus, the status of first root port in the groups table is indicated by bit 0 in the returned + * mask, second root port by bit 1 and so on. + + * 1 in the bit position indicates root port is enabled, whereas 0 indicates root port is + * disabled. This function assumes that the maximum count of root ports in the groups table is + * <= 32. + */ +uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index e2ad685..521ca6b 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,4 +1,7 @@ subdirs-y += ./* +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_helpers.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c new file mode 100644 index 0000000..dec786e --- /dev/null +++ b/src/soc/intel/common/block/pcie/pcie_helpers.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> +#include <intelblocks/pcie_rp.h> +#include <stdint.h> + +static uint32_t pcie_slot_enable_mask(int slot, int count) +{ + uint32_t mask = 0; + unsigned int i; + const struct device *dev; + + for (i = 0; i < count; i++) { + dev = pcidev_on_root(slot, i); + if (is_dev_enabled(dev)) + mask |= BIT(i); + } + + return mask; +} + +uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups) +{ + uint32_t mask = 0; + uint32_t offset = 0; + const struct pcie_rp_group *group; + + for (group = groups; group->count; ++group) { + if (group->count + offset >= sizeof(mask) * 8) { + printk(BIOS_ERR, "ERROR: %s: Root port count greater than mask size!\n", + __func__); + break; + } + mask |= pcie_slot_enable_mask(group->slot, group->count) << offset; + offset += group->count; + } + + return mask; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Gerrit-Change-Number: 48968 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd: Create new folder for SPD files
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49338 ) Change subject: spd: Create new folder for SPD files ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @Furquan, any name can replace set1/set2? Can we use the main attribute -- To view, visit https://review.coreboot.org/c/coreboot/+/49338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a871981642485020adaeaafd062f718c636a708 Gerrit-Change-Number: 49338 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 07:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: spd: Create new folder for SPD files
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49338 ) Change subject: spd: Create new folder for SPD files ...................................................................... spd: Create new folder for SPD files SPD file can share with different platforms if have the same MRC calculating. TGL and ADL can share the same SPD file generated by spd_tools. lp4x |_ set1/ |_ set2/ |_ jsl --> set1 |_ tgl --> set2 |_ adl --> set2 ddr4 |_ set1/ |_ tgl --> set1 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I3a871981642485020adaeaafd062f718c636a708 --- R src/spd/ddr4/set1/ddr4-spd-1.hex R src/spd/ddr4/set1/ddr4-spd-2.hex R src/spd/ddr4/set1/ddr4-spd-3.hex R src/spd/ddr4/set1/ddr4-spd-4.hex R src/spd/ddr4/set1/ddr4-spd-5.hex R src/spd/ddr4/set1/ddr4-spd-6.hex R src/spd/ddr4/set1/ddr4-spd-7.hex R src/spd/ddr4/set1/ddr4-spd-8.hex R src/spd/ddr4/set1/ddr4-spd-9.hex R src/spd/ddr4/set1/ddr4-spd-empty.hex R src/spd/ddr4/set1/ddr4_spd_manifest.generated.txt R src/spd/ddr4/set1/placeholder.spd.hex A src/spd/ddr4/tgl A src/spd/lp4x/adl A src/spd/lp4x/jsl R src/spd/lp4x/set1/lp4x-spd-1.hex R src/spd/lp4x/set1/lp4x-spd-2.hex R src/spd/lp4x/set1/lp4x-spd-3.hex R src/spd/lp4x/set1/lp4x-spd-4.hex R src/spd/lp4x/set1/lp4x-spd-5.hex R src/spd/lp4x/set1/lp4x-spd-6.hex R src/spd/lp4x/set1/lp4x-spd-7.hex R src/spd/lp4x/set1/lp4x_spd_manifest.generated.txt R src/spd/lp4x/set1/placeholder.spd.hex R src/spd/lp4x/set2/lp4x-spd-1.hex R src/spd/lp4x/set2/lp4x-spd-2.hex R src/spd/lp4x/set2/lp4x-spd-3.hex R src/spd/lp4x/set2/lp4x-spd-4.hex R src/spd/lp4x/set2/lp4x-spd-5.hex R src/spd/lp4x/set2/lp4x_spd_manifest.generated.txt C src/spd/lp4x/set2/placeholder.spd.hex A src/spd/lp4x/tgl 32 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/49338/1 diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-1.hex b/src/spd/ddr4/set1/ddr4-spd-1.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-1.hex rename to src/spd/ddr4/set1/ddr4-spd-1.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex b/src/spd/ddr4/set1/ddr4-spd-2.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-2.hex rename to src/spd/ddr4/set1/ddr4-spd-2.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-3.hex b/src/spd/ddr4/set1/ddr4-spd-3.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-3.hex rename to src/spd/ddr4/set1/ddr4-spd-3.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-4.hex b/src/spd/ddr4/set1/ddr4-spd-4.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-4.hex rename to src/spd/ddr4/set1/ddr4-spd-4.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-5.hex b/src/spd/ddr4/set1/ddr4-spd-5.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-5.hex rename to src/spd/ddr4/set1/ddr4-spd-5.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-6.hex b/src/spd/ddr4/set1/ddr4-spd-6.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-6.hex rename to src/spd/ddr4/set1/ddr4-spd-6.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-7.hex b/src/spd/ddr4/set1/ddr4-spd-7.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-7.hex rename to src/spd/ddr4/set1/ddr4-spd-7.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-8.hex b/src/spd/ddr4/set1/ddr4-spd-8.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-8.hex rename to src/spd/ddr4/set1/ddr4-spd-8.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-9.hex b/src/spd/ddr4/set1/ddr4-spd-9.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-9.hex rename to src/spd/ddr4/set1/ddr4-spd-9.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex b/src/spd/ddr4/set1/ddr4-spd-empty.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex rename to src/spd/ddr4/set1/ddr4-spd-empty.hex diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/spd/ddr4/set1/ddr4_spd_manifest.generated.txt similarity index 100% rename from src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt rename to src/spd/ddr4/set1/ddr4_spd_manifest.generated.txt diff --git a/src/soc/intel/tigerlake/spd/placeholder.spd.hex b/src/spd/ddr4/set1/placeholder.spd.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/placeholder.spd.hex rename to src/spd/ddr4/set1/placeholder.spd.hex diff --git a/src/spd/ddr4/tgl b/src/spd/ddr4/tgl new file mode 120000 index 0000000..c9d22dd --- /dev/null +++ b/src/spd/ddr4/tgl @@ -0,0 +1 @@ +set1 \ No newline at end of file diff --git a/src/spd/lp4x/adl b/src/spd/lp4x/adl new file mode 120000 index 0000000..6dc17fc --- /dev/null +++ b/src/spd/lp4x/adl @@ -0,0 +1 @@ +set2 \ No newline at end of file diff --git a/src/spd/lp4x/jsl b/src/spd/lp4x/jsl new file mode 120000 index 0000000..c9d22dd --- /dev/null +++ b/src/spd/lp4x/jsl @@ -0,0 +1 @@ +set1 \ No newline at end of file diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-1.hex b/src/spd/lp4x/set1/lp4x-spd-1.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-1.hex rename to src/spd/lp4x/set1/lp4x-spd-1.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-2.hex b/src/spd/lp4x/set1/lp4x-spd-2.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-2.hex rename to src/spd/lp4x/set1/lp4x-spd-2.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-3.hex b/src/spd/lp4x/set1/lp4x-spd-3.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-3.hex rename to src/spd/lp4x/set1/lp4x-spd-3.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-4.hex b/src/spd/lp4x/set1/lp4x-spd-4.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-4.hex rename to src/spd/lp4x/set1/lp4x-spd-4.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-5.hex b/src/spd/lp4x/set1/lp4x-spd-5.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-5.hex rename to src/spd/lp4x/set1/lp4x-spd-5.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-6.hex b/src/spd/lp4x/set1/lp4x-spd-6.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-6.hex rename to src/spd/lp4x/set1/lp4x-spd-6.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x-spd-7.hex b/src/spd/lp4x/set1/lp4x-spd-7.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x-spd-7.hex rename to src/spd/lp4x/set1/lp4x-spd-7.hex diff --git a/src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt b/src/spd/lp4x/set1/lp4x_spd_manifest.generated.txt similarity index 100% rename from src/soc/intel/jasperlake/spd/lp4x_spd_manifest.generated.txt rename to src/spd/lp4x/set1/lp4x_spd_manifest.generated.txt diff --git a/src/soc/intel/jasperlake/spd/placeholder.spd.hex b/src/spd/lp4x/set1/placeholder.spd.hex similarity index 100% rename from src/soc/intel/jasperlake/spd/placeholder.spd.hex rename to src/spd/lp4x/set1/placeholder.spd.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-1.hex b/src/spd/lp4x/set2/lp4x-spd-1.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x-spd-1.hex rename to src/spd/lp4x/set2/lp4x-spd-1.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-2.hex b/src/spd/lp4x/set2/lp4x-spd-2.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x-spd-2.hex rename to src/spd/lp4x/set2/lp4x-spd-2.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-3.hex b/src/spd/lp4x/set2/lp4x-spd-3.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x-spd-3.hex rename to src/spd/lp4x/set2/lp4x-spd-3.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-4.hex b/src/spd/lp4x/set2/lp4x-spd-4.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x-spd-4.hex rename to src/spd/lp4x/set2/lp4x-spd-4.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x-spd-5.hex b/src/spd/lp4x/set2/lp4x-spd-5.hex similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x-spd-5.hex rename to src/spd/lp4x/set2/lp4x-spd-5.hex diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/spd/lp4x/set2/lp4x_spd_manifest.generated.txt similarity index 100% rename from src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt rename to src/spd/lp4x/set2/lp4x_spd_manifest.generated.txt diff --git a/src/soc/intel/tigerlake/spd/placeholder.spd.hex b/src/spd/lp4x/set2/placeholder.spd.hex similarity index 100% copy from src/soc/intel/tigerlake/spd/placeholder.spd.hex copy to src/spd/lp4x/set2/placeholder.spd.hex diff --git a/src/spd/lp4x/tgl b/src/spd/lp4x/tgl new file mode 120000 index 0000000..6dc17fc --- /dev/null +++ b/src/spd/lp4x/tgl @@ -0,0 +1 @@ +set2 \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/49338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a871981642485020adaeaafd062f718c636a708 Gerrit-Change-Number: 49338 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP wi...
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49291 ) Change subject: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG ...................................................................... Patch Set 2: (1 comment) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/49291/comment/c7abb017_8e8b0517 PS2, Line 192: #if CONFIG(ENABLE_DISPLAY_OVER_DGPU) I don't think this works as you intend it to. Are you really seeing device .enabled being set differently in static.c depending upon the CONFIG() value? -- To view, visit https://review.coreboot.org/c/coreboot/+/49291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Gerrit-Change-Number: 49291 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 07:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49244/comment/2aee334e_d200a370 PS6, Line 138: 1 > This implementation would be for the whole Tigerlake platform. Right. But some mainboards for TGL might choose to not disable TCCold. Not volteer boards, but maybe other mainboards. -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:57:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:56:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2021