coreboot-gerrit January 2021

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz
by EricR Lai (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Frank Wu, Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49296 ) Change subject: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/zork/variants/baseboard/helpers.c: https://review.coreboot.org/c/coreboot/+/49296/comment/6b5c30c8_147e7bb0 PS6, Line 47: FW_CONFIG_MASK_SPI_SPEED = 0x1, Do we need this? @Furquan, maybe we can replace all, WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:39:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49244/comment/fc263f48_54365058 PS6, Line 9: while plugging USB devices into : the typec-to-a dongle. > Isn't it disabled *always* because of the UPD change? I think you want it disabled in this particula […] done. File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49244/comment/2797057e_a6d9c567 PS6, Line 138: 1 > I think we are going to have to do this via a mainboard setting. […] This implementation would be for the whole Tigerlake platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:39:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. John Zhao has uploaded a new patch set (#7) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... soc/intel/tigerlake: Disable TC cold support This change lets IOM consider all USB connected devices as device attached(DA) scenario. While connecting a typec-to-a dongle, IOM would disable TC cold and help to resolve enemuration failure after usb3 device is plugged into the dongle. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49244/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz
by Frank Wu (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes, EricR Lai. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49296 ) Change subject: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz ...................................................................... Patch Set 6: (2 comments) Patchset: PS6: Update SAR config from BIT[30..32] to BIT[23..25]. There is one BIT[26] left for SPI_SPEED. Here is the detail: https://partnerissuetracker.corp.google.com/issues/176858126#comment24 File src/mainboard/google/zork/variants/baseboard/helpers.c: https://review.coreboot.org/c/coreboot/+/49296/comment/41f9383b_6cadd283 PS5, Line 89: return !!extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR); > we don't want bool here. !! not needed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:35:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz
by Frank Wu (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Frank Wu, Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes. Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Kangheui Won, Rob Barnes, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49296 to look at the new patch set (#6). Change subject: mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz ...................................................................... mb/google/zork/var/vilboz: Add Wifi SAR for Vilboz BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/variant.c 3 files changed, 63 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/49296/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Gerrit-Change-Number: 49296 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: John Zhao, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49244/comment/f4b7b0b9_30b4a5eb PS6, Line 9: while plugging USB devices into : the typec-to-a dongle. Isn't it disabled *always* because of the UPD change? I think you want it disabled in this particular case so that the enumeration works properly. But, because of the UPD setting, TC cold is disabled always. If so, can you please update this message? File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/49244/comment/46256ea9_d08b05e5 PS6, Line 138: 1 I think we are going to have to do this via a mainboard setting. Not all mainboards might want to disable this. But, we can start with this for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 12 Jan 2021 06:06:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Use __pci_0_00_0_config in config_of_soc()
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49215 ) Change subject: device: Use __pci_0_00_0_config in config_of_soc() ...................................................................... device: Use __pci_0_00_0_config in config_of_soc() This change updates config_of_soc() to use __pci_0_00_0_config instead of accessing the config structure by referencing the struct device. This allows linker to optimize out unused portions of the device tree from early stages. With this change, bootblock .text section size drops as follows: Platform | Size without change | Size with change | Reduction | ------------------|---------------------|------------------|-------------| GLK (ampton) | 27112 bytes | 9832 bytes | 17280 bytes | APL (reef) | 26488 bytes | 17528 bytes | 8960 bytes | TGL (volteer2) | 47760 bytes | 21648 bytes | 26112 bytes | CML (hatch) | 40616 bytes | 22792 bytes | 17824 bytes | JSL (waddledee) | 37872 bytes | 19408 bytes | 18464 bytes | KBL (soraka) | 31840 bytes | 21568 bytes | 10272 bytes | Change-Id: I1fbf5b9817065e967e46188739978a1cc96c2c7e Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/device.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49215/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index d83cfe4..b8f2854 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -6,6 +6,7 @@ #include <device/path.h> #include <device/pci_type.h> #include <smbios.h> +#include <static.h> #include <types.h> struct fw_config; @@ -387,10 +388,10 @@ devtree_die(); } -/* config_of_soc() either returns a non-NULL pointer or dies in the config_of() call. */ static inline DEVTREE_CONST void *config_of_soc(void) { - return config_of(pcidev_on_root(0, 0)); + /* Returns pointer to config structure of root device (B:D:F = 0:00:0) */ + return __pci_0_00_0_config; } void enable_static_device(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/49215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbf5b9817065e967e46188739978a1cc96c2c7e Gerrit-Change-Number: 49215 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Disable TC cold support
by John Zhao (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Furquan Shaikh, John Zhao, Tim Wawrzynczak, Nick Vaccaro, Raj Astekar, Patrick Rudolph. John Zhao has uploaded a new patch set (#6) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/49244 ) Change subject: soc/intel/tigerlake: Disable TC cold support ...................................................................... soc/intel/tigerlake: Disable TC cold support This change disables IOM TC cold support while plugging USB devices into the typec-to-a dongle. This update help to resolve usb3 devices enumeration failure. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49244/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Gerrit-Change-Number: 49244 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add PCH ID 0x5182
by Subrata Banik (Code Review) 12 Jan '21

12 Jan '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49301 ) Change subject: soc/intel/alderlake: Add PCH ID 0x5182 ...................................................................... soc/intel/alderlake: Add PCH ID 0x5182 TEST=Able to build and boot ADLRVP. Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49301 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/lpc/lpc.c 3 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8ac29c5..0b78c9f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2959,6 +2959,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30 0x7a1e #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31 0x7a1f #define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32 0x5181 +#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33 0x5182 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0 0x7a80 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1 0x7a81 #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2 0x7a82 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index f0d8f2b..8cc81c1 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -79,6 +79,7 @@ { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, }; static struct { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 369b6b1..9eaf3c3 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -273,6 +273,8 @@ PCI_DEVICE_ID_INTEL_ADP_P_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, + PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, @@ -305,7 +307,6 @@ PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31, - PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/49301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Gerrit-Change-Number: 49301 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: make uart_max_index's value reflect what its name pretends
by Furquan Shaikh (Code Review) 12 Jan '21

12 Jan '21

Attention is currently required from: Felix Singer, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49305 ) Change subject: soc/intel: make uart_max_index's value reflect what its name pretends ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > agreed, max_index is awkward in the first place, that's why have ARRAY_SIZE, not ARRAY_MAX_INDEX 😉 +1. -- To view, visit https://review.coreboot.org/c/coreboot/+/49305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Gerrit-Change-Number: 49305 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Jan 2021 05:04:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2021