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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49317 )
Change subject: drivers/uart: Add ACPI SPCR table generation.
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/uart/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/49317/comment/056f55b6_3e60f554
PS3, Line 188: if ( config->spcr.pci_bus_number || config->spcr.pci_device_id ||
space prohibited after that open parenthesis '('
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Hello Lance Zhao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49317
to look at the new patch set (#3).
Change subject: drivers/uart: Add ACPI SPCR table generation.
......................................................................
drivers/uart: Add ACPI SPCR table generation.
The SPCR ACPI table is used to indicate whether a serial port or a
non-legacy UART interface is available for use with Microsoft
Windows Emergency Management Services (EMS).
It is also used by Linux and BITS to determine the serial port
configuration.
For more information, see the Reference Serial Port Console
Redirection Table.
https://web.archive.org/web/20210111235235/https://docs.microsoft.com/en-us…
BUG=b:74392237
TEST=Build
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a
---
M src/acpi/acpi.c
M src/drivers/uart/acpi/acpi.c
M src/drivers/uart/acpi/chip.h
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/include/acpi/acpi.h
M src/include/acpi/acpi_device.h
M src/include/console/uart.h
9 files changed, 247 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/49317/3
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49305 )
Change subject: soc/intel: make uart_max_index's value reflect what its name pretends
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Wouldn't it be even better to rename it to `uart_... […]
agreed, max_index is awkward in the first place, that's why have ARRAY_SIZE, not ARRAY_MAX_INDEX 😉
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Change subject: soc/intel/*: drop UART pad configuration from common code
......................................................................
Patch Set 9: Code-Review+1
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John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 )
Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 4: Code-Review+1
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John Zhao has uploaded a new patch set (#4) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/49244 )
Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
soc/intel/tigerlake: Enable TC Cold support
This change enables support for TC cold usb connect.
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/49244/4
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