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Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49244/comment/81d8bdc3_6d1e9472
PS3, Line 9: This change enables support for TC cold usb connect.
> Please go over https://chrome-internal-review.googlesource. […]
correct typo,
DisableTccoldOnUsbConnected=0 -> bit20 is NOT set (TCCold is not disabled)
DisableTccoldOnUsbConnected=1 -> bit20 is set (TCCold is disabled) which what we need to resolve the enumeration issue while plugging this usb3 into typec-to-a dongle.
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Change subject: drivers/uart: Add ACPI SPCR table generation.
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/uart/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/49317/comment/93eaf0fa_8825a701
PS2, Line 188: if ( config->spcr.pci_bus_number || config->spcr.pci_device_id ||
space prohibited after that open parenthesis '('
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Change subject: drivers/uart: Add ACPI SPCR table generation.
......................................................................
Patch Set 1:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/49317/comment/34a5dc61_a3cf2c4b
PS1, Line 1669: 1
> Though it may not matter that much, but from https://docs.microsoft. […]
Done. Thanks.
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Hello Lance Zhao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49317
to look at the new patch set (#2).
Change subject: drivers/uart: Add ACPI SPCR table generation.
......................................................................
drivers/uart: Add ACPI SPCR table generation.
The SPCR ACPI table is used to indicate whether a serial port or a
non-legacy UART interface is available for use with Microsoft
Windows Emergency Management Services (EMS).
It is also used by Linux and BITS to determine the serial port
configuration.
For more information, see the Reference Serial Port Console
Redirection Table.
https://web.archive.org/web/20210111235235/https://docs.microsoft.com/en-us…
BUG=b:74392237
TEST=Build
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a
---
M src/acpi/acpi.c
M src/drivers/uart/acpi/acpi.c
M src/drivers/uart/acpi/chip.h
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/include/acpi/acpi.h
M src/include/acpi/acpi_device.h
M src/include/console/uart.h
9 files changed, 241 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/49317/2
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Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/49244/comment/e9ecc78f_03984bb2
PS3, Line 137: Enable
> Is this enable or disable? The UPD is Disable...
It disables TCCold. The updated fsp is by default with DisableTccoldOnUsbConneced=0 (enable).
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Change subject: soc/intel/tigerlake: Enable TC Cold support
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49244/comment/b88f35a3_daaa8989
PS3, Line 9: This change enables support for TC cold usb connect.
> Can you please add some information as to why this change is required?
Please go over https://chrome-internal-review.googlesource.com/c/chromeos/third_party/inte….
if (TcssPeiConfig->IomConfig.DisableTccoldOnUsbConnected == 0) {
//
// CLEAR BIT 20 of IOM_TYPEC_SW_CONFIGURATION_1
// 0 - Enable TC cold if only have USB2 or lower speed connected.
//
IomTypecConfigValue &= (~DISABLE_TCCOLD_ON_USB_CONNECTED);
} else {
//
// SET BIT 20 of IOM_TYPEC_SW_CONFIGURATION_1
// 1 - Disable TC cold when any USB2/3 device connected.
//
IomTypecConfigValue |= DISABLE_TCCOLD_ON_USB_CONNECTED;
}
DisableTccoldOnUsbConnected=0 -> bit20 is NOT set (TCCold is not disabled)
DisableTccoldOnUsbConnected=1 -> bit21 is set (TCCold is disabled) which what we need to resolve the enumeration issue while plugging this usb3 into typec-to-a dongle.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49301 )
Change subject: soc/intel/alderlake: Add PCH ID 0x5182
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/49301/comment/ea2aff75_6b9e53d6
PS1, Line 308: PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32,
: PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33,
> nit: Place this up with rest of the ADP_P_ESPI above?
Done Furquan
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Change subject: soc/intel/adl: Add new Kconfig ENABLE_DISPLAY_OVER_DGPU for ADLRVP with DG
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Nico, Angel: can you please review, is this reasonable enough to select only DG from mainboard
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