Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40946 )
Change subject: nb/intel/sandybridge/raminit: Add ECC debug code
......................................................................
nb/intel/sandybridge/raminit: Add ECC debug code
* Add ECC test code when DEBUG_RAM_SETUP is enabled
* Move ECC scrubbing after set_scrambling_seed() to be able to observe
what has been cleared in the test routine.
* ECC scrubbing must happen after dram_dimm_set_mapping()
* Move method out of try_init_dram_ddr3()
Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_native.c
2 files changed, 25 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40946/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 6c8145d..ff563e7 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -366,10 +366,35 @@
set_scrambling_seed(&ctrl);
+ if (!s3resume && ctrl.ecc_enabled)
+ channel_scrub(&ctrl);
+
set_normal_operation(&ctrl);
final_registers(&ctrl);
+ /* can't do this earlier because it needs to be done in normal operation */
+ if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) {
+ uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB);
+
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n",
+ tseg);
+
+ /* Skip first MB to avoid special case for A-seg and test up to TSEG */
+ for (i = 1; i < tseg >> 20; i++) {
+ for (int j = 0; j < 1 * MiB; j += 4096) {
+ uintptr_t addr = i * MiB + j;
+ if (read32((u32 *)addr) == 0)
+ continue;
+
+ printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at"
+ " addr 0x%lx\n", addr);
+ break;
+ }
+ }
+ printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n");
+ }
+
/* Zone config */
dram_zones(&ctrl, 0);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 832391f..34299a3 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -685,9 +685,6 @@
err = channel_test(ctrl);
if (err)
return err;
-
- if (ctrl->ecc_enabled)
- channel_scrub(ctrl);
}
/* Set MAD-DIMM registers */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Gerrit-Change-Number: 40946
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Hello Philipp Deppenwiese,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42713
to review the following change.
Change subject: soc/intel/fsp_broadwell_de: examine ACM status at romstage entry
......................................................................
soc/intel/fsp_broadwell_de: examine ACM status at romstage entry
When INTEL_TXT is set, at romstage entry check if startup ACM worked correctly
by probing TXT_ERROR register.
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335
---
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42713/1
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 8438b10..9699927 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -38,6 +38,9 @@
#include <soc/ubox.h>
#include <build.h>
+#include <security/intel/txt/txt.h>
+#include <security/intel/txt/txt_register.h>
+
static void init_rtc(void)
{
u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3);
@@ -156,6 +159,12 @@
early_iio_hide();
timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x48);
+
+ if (CONFIG(INTEL_TXT)) {
+ printk(BIOS_DEBUG, "Check TXT_ERROR register\n");
+ intel_txt_log_acm_error(read32((void *)TXT_ERROR));
+ }
+
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
--
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: I6f423df8b05dc44220a9bad3674f687bac94e335
Gerrit-Change-Number: 42713
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-MessageType: newchange
Hello Andrey Petrov,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42711
to review the following change.
Change subject: mainboard/ocp/monolake: If memory is locked down, clear TPM and reset
......................................................................
mainboard/ocp/monolake: If memory is locked down, clear TPM and reset
Under certain conditions TXT can force system to come out of reset with
"locked" memory configuration. This manifests itself in IMC's SMBus
controller not being able to read and SPD. FSP does not seem to detect
this condition and simply fails with "no memory found" error. It turned
out IBB measurements are stored in PCR-0 on TPM and that is what TXT fw
seems to be using to determine if locking needs to be enforced.
This patch detects the locked condition and tries to clear TPM and
reboot the system.
TEST=take an OCP monolake running vendor BIOS that uses TXT.
Ungracefully shut down the system and reflash with coreboot image.
With this patch system manages to get out of bricked state.
Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe
Signed-off-by: Andrey Petrov <anpetrov(a)fb.com>
---
M src/mainboard/ocp/monolake/romstage.c
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42711/1
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c
index ef41b77..d4cd0ad 100644
--- a/src/mainboard/ocp/monolake/romstage.c
+++ b/src/mainboard/ocp/monolake/romstage.c
@@ -17,6 +17,7 @@
#include <stddef.h>
#include <soc/romstage.h>
+#include <soc/memory.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <drivers/vpd/vpd.h>
#include <cpu/x86/msr.h>
@@ -26,6 +27,9 @@
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/gpio.h>
+#include <security/tpm/tspi.h>
+#include <security/tpm/tis.h>
+
/* Define the strings for UPD variables that could be customized */
@@ -207,6 +211,23 @@
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset();
}
+
+ /*
+ * If system have been using TXT and has been ungracefully shutdown and reflashed,
+ * on next boot TXT fw compares IBB hash against PCR0 in TPM. On mismatch memory
+ * configuration is locked as a security measure. If we detect this condition we
+ * can try resetting and clearing TPM, which makes system usable again.
+ */
+ if (memory_config_is_locked()) {
+ console_init();
+ printk(BIOS_EMERG, "Memory configuration is locked! Clearing TPM.\n");
+ tpm_setup(false);
+ if (tpm_clear_and_reenable() != TPM_SUCCESS) {
+ printk(BIOS_EMERG, "TPM clear success, resetting\n");
+ full_reset();
+ }
+ die("TPM reset failed. Giving up\n");
+ }
}
/**
--
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: I89f87f6ce187c50334c2d3c477d3042528e27fbe
Gerrit-Change-Number: 42711
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37199 )
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage
......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache.
In most circumstances this memory is set up as UC, so to speed
up these operations like decompressing postcar, this has to be
set up as WB.
Note: This should only be attempted on platforms where some form
of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/mtrr/Makefile.inc
A src/cpu/x86/mtrr/cbmem_cache.c
M src/include/cpu/x86/mtrr.h
3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/1
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index 129d05d..2658388 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -11,3 +11,5 @@
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
+
+romstage-y += cbmem_cache.c
\ No newline at end of file
diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c
new file mode 100644
index 0000000..8753e9e
--- /dev/null
+++ b/src/cpu/x86/mtrr/cbmem_cache.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
+#include <program_loading.h>
+#include <commonlib/region.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+
+void setup_romstage_wb_cbmem_cache(void)
+{
+ int mtrr_num = get_free_var_mtrr();
+ uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t stage_cache_base, stage_cache_end;
+ size_t stage_cache_size;
+ size_t stage_cache_mtrr_size = 4 * KiB;
+
+ printk(BIOS_DEBUG, "Setting MTRR's for cbmem and stage cache\n");
+
+ /* postcar will do invd so we need a way to make sure things are in memory
+ which is only possible if clflush is supported. */
+ if (!clflush_supported()) {
+ printk(BIOS_WARNING, "CLFLUSH not supported, not caching cbmem!\n");
+ if (CONFIG(COMPRESS_POSTCAR))
+ printk(BIOS_WARNING, "Decompressing POSTCAR will be slow!\n");
+
+ return;
+ }
+ if (mtrr_num < 0) {
+ printk(BIOS_DEBUG, "No MTRR free to cache cbmem\n!");
+ return;
+ }
+ /* Often cbmem_top is chosen to be aligned already to optimize MTRR
+ usage in the postcar frame so this should not be too worrisome. */
+ top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
+ set_var_mtrr(mtrr_num, top_of_ram - 4 * MiB, 4 * MiB, MTRR_TYPE_WRBACK);
+
+ if (!CONFIG(TSEG_STAGE_CACHE))
+ return;
+ mtrr_num = get_free_var_mtrr();
+ if (mtrr_num < 0) {
+ printk(BIOS_DEBUG, "No MTRR free to cache TSEG stage cache\n!");
+ return;
+ }
+ stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size);
+ stage_cache_end = stage_cache_base + stage_cache_size;
+
+ /* Find MTRR to cover TSEG stage cache */
+ while (1) {
+ /* Do some sanity check before it gets absurdly. */
+ if (stage_cache_mtrr_size > 64 * MiB) {
+ printk(BIOS_WARNING, "Not caching stage cache, too large\n");
+ return;
+ }
+ if (ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size)
+ + stage_cache_mtrr_size > stage_cache_end)
+ break;
+ stage_cache_mtrr_size *= 2;
+ }
+ set_var_mtrr(mtrr_num, ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size),
+ stage_cache_mtrr_size, MTRR_TYPE_WRBACK);
+}
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 29256c8..abdecfe 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -95,6 +95,8 @@
void x86_setup_fixed_mtrrs_no_enable(void);
void x86_mtrr_check(void);
+void setup_romstage_wb_cbmem_cache(void);
+
/* Insert a temporary MTRR range for the duration of coreboot's runtime.
* This function needs to be called after the first MTRR solution is derived. */
void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
--
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Gerrit-Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc
Gerrit-Change-Number: 37199
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange