coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: mb/intel/jasperlake_rvp: Add user facing camera support
by Varshit B Pandya (Code Review) 31 Jul '20

31 Jul '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41538 ) Change subject: mb/intel/jasperlake_rvp: Add user facing camera support ...................................................................... mb/intel/jasperlake_rvp: Add user facing camera support 1. Configure GPIOs as per schematics 2. Add 1 Ports and 1 Endpoints 3. Add support for OTVI2740 UFC is on I2C4 using 2 data-lanes Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I5383fe6c65fcb44579f8d289f88c800630410464 --- A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 6 files changed, 261 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/41538/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl new file mode 100644 index 0000000..6acd6dd --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.I2C4) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable CLK0 */ + MCON(0, 1) /* Clock 0, 19.2MHz */ + /* Pull PWREN(GPIO D5) high */ + STXS(GPP_D5) + Sleep(5) /* 5 us */ + /* Pull RST(GPIO B14) low */ + CTXS(GPP_B14) + Sleep(5) /* 5 us */ + /* Pull RST high */ + STXS(GPP_B14) + Sleep(5) /* 5 us */ + STA = 1 + } + } + + Method (_OFF, 0, Serialized) /* _OFF: Power Off */ + { + If ((STA == One)) + { + /* Pull RST low */ + CTXS(GPP_B14) + /* Pull PWREN low */ + CTXS(GPP_D5) + /* Disable CLK0 */ + MCOF(0) // Clock 0 + /* STA = Zero */ + STA = 0 + } + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI2740") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 2740 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x15752A00 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl index 8e3a5ef..fae8e5d 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl @@ -3,4 +3,5 @@ #include "ipu_mainboard.asl" #include "ipu_endpoints.asl" +#include "cam0.asl" #include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl index e09021d5..b7b50f5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -3,6 +3,46 @@ Scope (_SB.PCI0.IPU0) { + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C4.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl index 159322d..e008bd5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -16,16 +16,45 @@ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) + Package (0x02) { Package (0x02) { + "port0", + "PRT0" + }, + + Package (0x02) + { "port1", "PRT1" } } }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (PRT1, Package (0x04) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 14ca4a5..9e4be39 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -91,7 +91,7 @@ [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" @@ -146,6 +146,9 @@ .sda_hold = 36, } }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, }, @@ -289,7 +292,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 Cam 0 + device pci 19.0 on end # I2C #4 Cam 0 device pci 19.1 on end # I2C #5 Cam 1 and VCM device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index d67f4a4..02ddcbe 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -31,6 +31,9 @@ /* PMC_PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), @@ -76,9 +79,18 @@ /* CAM2_PWREN */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* CAM1_PWREN */ + PAD_CFG_GPO(GPP_D5, 0, PLTRST), + /*LAN_RST_N*/ PAD_CFG_GPO(GPP_D6, 1, PLTRST), + /* I2C4B_SDA */ + PAD_CFG_NF(GPP_D12, NONE, PLTRST, NF3), + + /* I2C4B_SCL */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF3), + /* AVS_I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), @@ -97,6 +109,9 @@ /* I2C5_SCL */ PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + /* IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF2), + /* IMGCLKOUT_1 */ PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/41538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5383fe6c65fcb44579f8d289f88c800630410464 Gerrit-Change-Number: 41538 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: sb/intel/lynxpoint: Clean up code
by Angel Pons (Code Review) 31 Jul '20

31 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41943 ) Change subject: sb/intel/lynxpoint: Clean up code ...................................................................... sb/intel/lynxpoint: Clean up code Fix code and comment style, reflow lines and constify a few things. Tested with abuild --timeless with asrock/b85m_pro4 and google/slippy. Change-Id: Idb908d1a610c10897e1005ba024e433979347fa6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 26 files changed, 353 insertions(+), 417 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41943/1 diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d63af6c..7569f90 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -37,8 +37,7 @@ hpet->number = 0x00; hpet->min_tick = 0x0080; - header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); + header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 4122dbb..73a931b 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -18,9 +18,7 @@ /* Can support up to 4 codecs */ for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - cim_verb_data_size, - cim_verb_data); + hda_codec_init(base, i, cim_verb_data_size, cim_verb_data); } if (pc_beep_verbs_size) @@ -53,8 +51,7 @@ pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) reg32 &= ~(1UL << 31); @@ -138,7 +135,7 @@ } static struct pci_operations azalia_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index b015ea2..0f59d70 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -31,7 +31,7 @@ static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ + but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; RCBA32(GCS) = gcs; diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index ed362a2..fa87048 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -105,4 +105,4 @@ }; -#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e5ce3f5..c1503eb 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -125,10 +125,7 @@ pci_write_dword_ptr(&did, PCI_ME_H_GS); - /* - * The ME firmware does not respond with an ACK when NOMEM or ERROR - * are sent. - */ + /* The ME firmware does not respond with an ACK when NOMEM or ERROR are sent. */ if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR) return 0; diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 06ddd08..86abbe0 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -4,7 +4,8 @@ #include <device/pci_def.h> #include "pch.h" -/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index +/* + * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index * selects 0:1d.0 (PCH_EHCI1) for usbdebug use. */ #if CONFIG_USBDEBUG_HCD_INDEX != 2 @@ -16,11 +17,9 @@ #endif /* - * Setup USB controller MMIO BAR to prevent the - * reference code from resetting the controller. + * Setup USB controller MMIO BAR to prevent the reference code from resetting the controller. * - * The BAR will be re-assigned during device - * enumeration so these are only temporary. + * The BAR will be re-assigned during device enumeration so these are only temporary. */ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 2e4df72..d8fadf9 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -30,7 +30,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start) { /* GPE Bank 1 is GPIO 0-31 */ - u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); + u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg); u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en; int i; @@ -46,7 +46,7 @@ u16 pmbase = get_pmbase(); u32 gpe0_sts, gpe0_en; int gpe0_high_gpios[] = { - [0] = 27, + [0] = 27, [24] = 17, [25] = 19, [26] = 21, @@ -60,26 +60,23 @@ pch_log_standard_gpe(GPE0_EN, GPE0_STS); /* GPIO 0-15 */ - gpe0_en = inw(pmbase + GPE0_EN + 2); + gpe0_en = inw(pmbase + GPE0_EN + 2); gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; + for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); } - /* - * Now check and log upper status bits - */ - - gpe0_en = inl(pmbase + GPE0_EN_2); + /* Now check and log upper status bits */ + gpe0_en = inl(pmbase + GPE0_EN_2); gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en; for (i = 0; i <= 31; i++) { if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, - gpe0_high_gpios[i]); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, gpe0_high_gpios[i]); } } @@ -102,9 +99,9 @@ if (!lpc) return; - pm1_sts = inw(get_pmbase() + PM1_STS); + pm1_sts = inw(get_pmbase() + PM1_STS); tco2_sts = inw(get_pmbase() + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); + gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); /* PWR_FLR Power Failure */ @@ -141,8 +138,7 @@ /* ACPI Wake */ if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 9d264e0..59f6028 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -69,14 +69,12 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -90,9 +88,8 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_valid(u8 *base) { @@ -103,14 +100,12 @@ reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -143,19 +138,18 @@ * 2 - Subsystem ID * 3 - Number of jacks (groups of 4 dwords) for this codec */ -static u32 hda_find_verb(u32 verb_table_bytes, - const u32 *verb_table_data, - u32 viddid, const u32 **verb) +static u32 hda_find_verb(u32 verb_table_bytes, const u32 *verb_table_data, u32 viddid, + const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (verb_table_bytes / sizeof(u32))) { - u32 verb_size = 4 * verb_table_data[idx+2]; // in u32 + u32 verb_size = 4 * verb_table_data[idx + 2]; // in u32 if (verb_table_data[idx] != viddid) { idx += verb_size + 3; // skip verb + header continue; } - *verb = &verb_table_data[idx+3]; + *verb = &verb_table_data[idx + 3]; return verb_size; } diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index c85ba2c..6599a43 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -14,12 +14,10 @@ #ifdef __SIMPLE_DEVICE__ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else - return pci_read_config16(pcidev_on_root(0x1f, 0), - GPIO_BASE) & 0xfffc; + return pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; #endif } - /* * This function will return a number that indicates which PIRQ * this GPIO maps to. If this is not a PIRQ capable GPIO then @@ -28,16 +26,16 @@ static int lp_gpio_to_pirq(int gpio) { switch (gpio) { - case 8: return 0; /* PIRQI */ - case 9: return 1; /* PIRQJ */ - case 10: return 2; /* PIRQK */ - case 13: return 3; /* PIRQL */ - case 14: return 4; /* PIRQM */ - case 45: return 5; /* PIRQN */ - case 46: return 6; /* PIRQO */ - case 47: return 7; /* PIRQP */ - case 48: return 8; /* PIRQQ */ - case 49: return 9; /* PIRQR */ + case 8: return 0; /* PIRQI */ + case 9: return 1; /* PIRQJ */ + case 10: return 2; /* PIRQK */ + case 13: return 3; /* PIRQL */ + case 14: return 4; /* PIRQM */ + case 45: return 5; /* PIRQN */ + case 46: return 6; /* PIRQO */ + case 47: return 7; /* PIRQP */ + case 48: return 8; /* PIRQQ */ + case 49: return 9; /* PIRQR */ case 50: return 10; /* PIRQS */ case 51: return 11; /* PIRQT */ case 52: return 12; /* PIRQU */ @@ -50,7 +48,7 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base(); const struct pch_lp_gpio_map *config; u32 owner[3] = {0}; u32 route[3] = {0}; @@ -102,7 +100,7 @@ int get_gpio(int gpio_num) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base(); if (gpio_num > MAX_GPIO_NUMBER) return 0; @@ -111,7 +109,7 @@ } /* - * get a number comprised of multiple GPIO values. gpio_num_array points to + * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ unsigned int get_gpios(const int *gpio_num_array) @@ -131,7 +129,7 @@ void set_gpio(int gpio_num, int value) { - u16 gpio_base = get_gpio_base(); + const u16 gpio_base = get_gpio_base(); u32 conf0; if (gpio_num > MAX_GPIO_NUMBER) @@ -145,7 +143,5 @@ int gpio_is_native(int gpio_num) { - u16 gpio_base = get_gpio_base(); - - return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1); + return !(inl(get_gpio_base() + GPIO_CONFIG0(gpio_num)) & 1); } diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index fbad7d0..ca8f843 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -152,10 +152,10 @@ /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); -/* get GPIO pin value */ +/* Get GPIO pin value */ int get_gpio(int gpio_num); /* - * get a number comprised of multiple GPIO values. gpio_num_array points to + * Get a number comprised of multiple GPIO values. gpio_num_array points to * the array of gpio pin numbers to scan, terminated by -1. */ unsigned int get_gpios(const int *gpio_num_array); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a..02ea34c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -63,15 +63,14 @@ static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); #if !CONFIG(SERIRQ_CONTINUOUS_MODE) - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif } -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved * 0x02 - 0010 = Reserved @@ -108,12 +107,13 @@ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); - /* Eric Biederman once said we should let the OS do this. + /* + * Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -140,19 +140,17 @@ config_t *config = dev->chip_info; u32 reg32 = 0; - /* An array would be much nicer here, or some - * other method of doing this. - */ - reg32 |= (config->gpi0_routing & 0x03) << 0; - reg32 |= (config->gpi1_routing & 0x03) << 2; - reg32 |= (config->gpi2_routing & 0x03) << 4; - reg32 |= (config->gpi3_routing & 0x03) << 6; - reg32 |= (config->gpi4_routing & 0x03) << 8; - reg32 |= (config->gpi5_routing & 0x03) << 10; - reg32 |= (config->gpi6_routing & 0x03) << 12; - reg32 |= (config->gpi7_routing & 0x03) << 14; - reg32 |= (config->gpi8_routing & 0x03) << 16; - reg32 |= (config->gpi9_routing & 0x03) << 18; + /* An array would be much nicer here, or some other method of doing this. */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; reg32 |= (config->gpi10_routing & 0x03) << 20; reg32 |= (config->gpi11_routing & 0x03) << 22; reg32 |= (config->gpi12_routing & 0x03) << 24; @@ -175,7 +173,8 @@ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; - /* Which state do we want to goto after g3 (power restored)? + /* + * Which state do we want to go to after G3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * @@ -218,7 +217,7 @@ reg8 &= 0x0f; /* Higher Nibble must be 0 */ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ outb(reg8, 0x61); reg8 = inb(0x70); @@ -254,14 +253,14 @@ enable_alt_smi(config->alt_gp_smi_en); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT - reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 0); // SCI_EN + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + reg32 |= (1 << 4) | (1 << 5) | (1 << 0); RCBA32(0x3310) = reg32; reg16 = RCBA16(0x3f02); @@ -336,8 +335,7 @@ pch_config_rcba(lpt_lp_pm_rcba); - pci_write_config32(dev, 0xac, - pci_read_config32(dev, 0xac) | (1 << 21)); + pci_write_config32(dev, 0xac, pci_read_config32(dev, 0xac) | (1 << 21)); pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700); pch_iobp_update(0xED000118, ~0UL, 0x00c00000); @@ -402,14 +400,14 @@ RCBA32_OR(0x900, (1 << 14)); reg32 = RCBA32(CG); - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1UL << 31); // LPC Dynamic - reg32 |= (1 << 16); // PCIe Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 28); // GPIO Dynamic + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1UL << 31); // LPC Dynamic + reg32 |= (1 << 16); // PCIe Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 28); // GPIO Dynamic RCBA32(CG) = reg32; - RCBA32_OR(0x38c0, 0x7); // SPI Dynamic + RCBA32_OR(0x38c0, 0x7); // SPI Dynamic } static void enable_lp_clock_gating(struct device *dev) @@ -447,25 +445,25 @@ reg32 = RCBA32(CG); if (RCBA32(0x3454) & (1 << 4)) - reg32 &= ~(1 << 29); // LPC Dynamic + reg32 &= ~(1 << 29); // LPC Dynamic else - reg32 |= (1 << 29); // LPC Dynamic - reg32 |= (1UL << 31); // LP LPC - reg32 |= (1 << 30); // LP BLA - reg32 |= (1 << 28); // GPIO Dynamic - reg32 |= (1 << 27); // HPET Dynamic - reg32 |= (1 << 26); // Generic Platform Event Clock + reg32 |= (1 << 29); // LPC Dynamic + reg32 |= (1UL << 31); // LP LPC + reg32 |= (1 << 30); // LP BLA + reg32 |= (1 << 28); // GPIO Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 26); // Generic Platform Event Clock if (RCBA32(BUC) & PCH_DISABLE_GBE) - reg32 |= (1 << 23); // GbE Static - reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 16); // PCI Dynamic + reg32 |= (1 << 23); // GbE Static + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1 << 16); // PCI Dynamic RCBA32(CG) = reg32; - RCBA32_OR(0x3434, 0x7); // LP LPC + RCBA32_OR(0x3434, 0x7); // LP LPC - RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); // SATA - RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic + RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic pch_iobp_update(0xCF000000, ~0UL, 0x00007001); pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0 @@ -503,7 +501,7 @@ * Enable DMI ASPM in the PCH */ RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); RCBA32_OR(0x21a8, 0x3); } @@ -617,8 +615,7 @@ * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, - int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -631,8 +628,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, - int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -657,8 +653,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); @@ -882,8 +877,7 @@ } static unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long start, - struct acpi_rsdp *rsdp) + unsigned long start, struct acpi_rsdp *rsdp) { unsigned long current; acpi_hpet_t *hpet; @@ -967,7 +961,8 @@ 0x9c43, /* LP Premium SKU */ 0x9c45, /* LP Mainstream SKU */ 0x9c47, /* LP Value SKU */ - 0 }; + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 2a05233..19d06c3 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -103,64 +103,64 @@ #define ME_HFS2_PHASE_HOST_COMM 6 /* Current State - Based on Infra Progress values. */ /* ROM State */ -#define ME_HFS2_STATE_ROM_BEGIN 0 -#define ME_HFS2_STATE_ROM_DISABLE 6 +#define ME_HFS2_STATE_ROM_BEGIN 0 +#define ME_HFS2_STATE_ROM_DISABLE 6 /* BUP State */ -#define ME_HFS2_STATE_BUP_INIT 0 -#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 -#define ME_HFS2_STATE_BUP_FLOW_DET 4 -#define ME_HFS2_STATE_BUP_VSCC_ERR 8 -#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa -#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb -#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd -#define ME_HFS2_STATE_BUP_M3 0x11 -#define ME_HFS2_STATE_BUP_M0 0x12 -#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 -#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_INIT 0 +#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 +#define ME_HFS2_STATE_BUP_FLOW_DET 4 +#define ME_HFS2_STATE_BUP_VSCC_ERR 8 +#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa +#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb +#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd +#define ME_HFS2_STATE_BUP_M3 0x11 +#define ME_HFS2_STATE_BUP_M0 0x12 +#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 +#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 -#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 -#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c -#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f -#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 -#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 -#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 -#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 -#define ME_HFS2_STATE_BUP_M0_CLK 0x26 -#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 -#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 -#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 +#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 +#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c +#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f +#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 +#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 +#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 +#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 +#define ME_HFS2_STATE_BUP_M0_CLK 0x26 +#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 +#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 +#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 /* Policy Module State */ -#define ME_HFS2_STATE_POLICY_ENTRY 0 -#define ME_HFS2_STATE_POLICY_RCVD_S3 3 -#define ME_HFS2_STATE_POLICY_RCVD_S4 4 -#define ME_HFS2_STATE_POLICY_RCVD_S5 5 -#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 -#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 -#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 -#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 -#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa -#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb -#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc -#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd -#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe -#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf -#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 +#define ME_HFS2_STATE_POLICY_ENTRY 0 +#define ME_HFS2_STATE_POLICY_RCVD_S3 3 +#define ME_HFS2_STATE_POLICY_RCVD_S4 4 +#define ME_HFS2_STATE_POLICY_RCVD_S5 5 +#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 +#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 +#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 +#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 +#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa +#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb +#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc +#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd +#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe +#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf +#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 /* Current PM Event Values */ -#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 -#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 -#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 -#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 -#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 -#define ME_HFS2_PMEVENT_S0MO_SXM3 7 -#define ME_HFS2_PMEVENT_SXM3_S0M0 8 -#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb -#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc +#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 +#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 +#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 +#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 +#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 +#define ME_HFS2_PMEVENT_S0MO_SXM3 7 +#define ME_HFS2_PMEVENT_SXM3_S0M0 8 +#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb +#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc struct me_hfs2 { u32 bist_in_progress: 1; @@ -185,7 +185,7 @@ #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 #define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) +#define PCI_ME_HER(x) (0xc0 + (4 * (x))) struct me_heres { u32 extend_reg_algorithm: 4; @@ -325,31 +325,30 @@ * structures follows the ordering in the ME9 BWG. */ -#define MBP_APPID_KERNEL 1 -#define MBP_APPID_INTEL_AT 3 -#define MBP_APPID_HWA 4 -#define MBP_APPID_ICC 5 -#define MBP_APPID_NFC 6 +#define MBP_APPID_KERNEL 1 +#define MBP_APPID_INTEL_AT 3 +#define MBP_APPID_HWA 4 +#define MBP_APPID_ICC 5 +#define MBP_APPID_NFC 6 /* Kernel items: */ -#define MBP_KERNEL_FW_VER_ITEM 1 -#define MBP_KERNEL_FW_CAP_ITEM 2 -#define MBP_KERNEL_ROM_BIST_ITEM 3 -#define MBP_KERNEL_PLAT_KEY_ITEM 4 -#define MBP_KERNEL_FW_TYPE_ITEM 5 -#define MBP_KERNEL_MFS_FAILURE_ITEM 6 -#define MBP_KERNEL_PLAT_TIME_ITEM 7 +#define MBP_KERNEL_FW_VER_ITEM 1 +#define MBP_KERNEL_FW_CAP_ITEM 2 +#define MBP_KERNEL_ROM_BIST_ITEM 3 +#define MBP_KERNEL_PLAT_KEY_ITEM 4 +#define MBP_KERNEL_FW_TYPE_ITEM 5 +#define MBP_KERNEL_MFS_FAILURE_ITEM 6 +#define MBP_KERNEL_PLAT_TIME_ITEM 7 /* Intel AT items: */ -#define MBP_INTEL_AT_STATE_ITEM 1 +#define MBP_INTEL_AT_STATE_ITEM 1 /* ICC Items: */ -#define MBP_ICC_PROFILE_ITEM 1 +#define MBP_ICC_PROFILE_ITEM 1 /* HWA Items: */ -#define MBP_HWA_REQUEST_ITEM 1 +#define MBP_HWA_REQUEST_ITEM 1 /* NFC Items: */ -#define MBP_NFC_SUPPORT_DATA_ITEM 1 +#define MBP_NFC_SUPPORT_DATA_ITEM 1 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) -#define MBP_IDENT(appid, item) \ - MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) +#define MBP_IDENT(appid, item) MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) typedef struct { u32 mbp_size : 8; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8914edf..79d47da 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -86,7 +86,6 @@ /* * ME/MEI access helpers using memcpy to avoid aliasing. */ - static inline void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset/sizeof(u32))); @@ -272,8 +271,8 @@ return 0; } -static int mei_send_header(u8 me_address, u8 host_address, - void *header, int header_len, int complete) +static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len, + int complete) { struct mei_header mei = { .client_address = me_address, @@ -284,8 +283,7 @@ return mei_send_packet(&mei, header); } -static int mei_recv_msg(void *header, int header_bytes, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mei_csr me, host; @@ -344,8 +342,8 @@ /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { - printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + printk(BIOS_ERR, "ME: not enough room in response buffer: %u != %u\n", + ndata, rsp_bytes >> 2); return -1; } @@ -384,8 +382,7 @@ return 0; /* Read header and data */ - if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), - rsp_data, rsp_bytes) < 0) + if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), rsp_data, rsp_bytes) < 0) return -1; if (!mkhi_rsp.is_response || @@ -422,7 +419,7 @@ } /* - * mbp clear routine. This will wait for the ME to indicate that + * MBP clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ #ifdef __SIMPLE_DEVICE__ @@ -479,8 +476,7 @@ }; /* Send request and wait for response */ - if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), - &cap_msg, sizeof(cap_msg)) < 0) { + if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; } @@ -499,20 +495,20 @@ return; } - print_cap("Full Network manageability", cap->full_net); - print_cap("Regular Network manageability", cap->std_net); - print_cap("Manageability", cap->manageability); - print_cap("IntelR Anti-Theft (AT)", cap->intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); - print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); - print_cap("IPV6", cap->ipv6); - print_cap("KVM Remote Control (KVM)", cap->kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap->och); - print_cap("Virtual LAN (VLAN)", cap->vlan); - print_cap("TLS", cap->tls); - print_cap("Wireless LAN (WLAN)", cap->wlan); + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); } #if CONFIG(CHROMEOS) && 0 /* DISABLED */ @@ -569,8 +565,7 @@ u32 reg32; u16 reg16; - mei_base_address = (u32 *) - (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) @@ -917,10 +912,7 @@ u32 data[0]; }; -/* - * mbp seems to be following its own flow, let's retrieve it in a dedicated - * function. - */ +/* MBP seems to be following its own flow, let's retrieve it in a dedicated function. */ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; @@ -1033,8 +1025,8 @@ ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); default: - printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " - "dw offset 0x%x\n", mbp->data[i], i); + printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ dw offset 0x%x\n", + mbp->data[i], i); break; } i += item->length; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 045d960..6ef99ed 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -11,7 +11,7 @@ [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In", }; /* HFS1[8:6] Current Operation State Values */ @@ -21,7 +21,7 @@ [ME_HFS_STATE_M3] = "M3 without UMA", [ME_HFS_STATE_M0] = "M0 without UMA", [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error", }; /* HFS[19:16] Current Operation Mode Values */ @@ -30,7 +30,7 @@ [ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message", }; /* HFS[15:12] Error Code Values */ @@ -38,7 +38,7 @@ [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" + [ME_HFS_ERROR_DEBUG] = "Debug Failure", }; /* HFS2[31:28] ME Progress Code */ @@ -49,30 +49,30 @@ [ME_HFS2_PHASE_POLICY] = "Policy Module", [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", [ME_HFS2_PHASE_UNKNOWN] = "Unknown", - [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication", }; /* HFS2[27:24] Power Management Event */ static const char *me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", - [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", - [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", + [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff", }; /* Progress Code 0 states */ static const char *me_progress_rom_values[] = { - [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", - [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE", }; /* Progress Code 1 states */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index e3c5bb2..9564b76 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -25,8 +25,7 @@ static int pch_revision_id = -1; if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(pch_get_lpc_device(), - PCI_REVISION_ID); + pch_revision_id = pci_read_config8(pch_get_lpc_device(), PCI_REVISION_ID); return pch_revision_id; } @@ -45,8 +44,7 @@ static int pch_type = -1; if (pch_type < 0) - pch_type = pci_read_config8(pch_get_lpc_device(), - PCI_DEVICE_ID + 1); + pch_type = pci_read_config8(pch_get_lpc_device(), PCI_DEVICE_ID + 1); return pch_type; } @@ -60,8 +58,7 @@ static u16 pmbase; if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; + pmbase = pci_read_config16(pch_get_lpc_device(), PMBASE) & 0xfffc; return pmbase; } @@ -70,8 +67,7 @@ static u16 gpiobase; if (!gpiobase) - gpiobase = pci_read_config16(pch_get_lpc_device(), - GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(pch_get_lpc_device(), GPIOBASE) & 0xfffc; return gpiobase; } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 19f8637..6e2bd24 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -32,7 +32,7 @@ * Bus 0:Device 22:Function 2 IDE-R * Bus 0:Device 22:Function 3 KT * Bus 0:Device 20:Function 0 xHCI Controller -*/ + */ /* PCH types */ #define PCH_TYPE_LPT 0x8c @@ -166,8 +166,7 @@ #endif void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e11a0b7..79b9517 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -322,8 +322,7 @@ } } - printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; } @@ -358,58 +357,54 @@ /* Check Root Port Configuration. */ switch (rp) { - case 2: - /* Root Port 2 is disabled for all lane configurations - * but config 00b (4x1 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x3) { - root_port_mark_disable(dev); - return; - } + case 2: + /* Root Port 2 is disabled for all lane configs except 00b (4x1 links). */ + if ((rpc.strpfusecfg1 >> 14) & 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 3: + /* Root Port 3 is disabled in config 11b (1x4 links). */ + if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 4: + /* Root Port 4 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */ + if ((rpc.strpfusecfg1 >> 14) & 0x2) { + root_port_mark_disable(dev); + return; + } + break; + case 6: + if (is_lp) break; - case 3: - /* Root Port 3 is disabled in config 11b (1x4 links). */ - if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) { - root_port_mark_disable(dev); - return; - } + /* Root Port 6 is disabled for all lane configs except 00b (4x1 links). */ + if ((rpc.strpfusecfg2 >> 14) & 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 7: + if (is_lp) break; - case 4: - /* Root Port 4 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ - if ((rpc.strpfusecfg1 >> 14) & 0x2) { - root_port_mark_disable(dev); - return; - } + /* Root Port 7 is disabled in config 11b (1x4 links). */ + if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { + root_port_mark_disable(dev); + return; + } + break; + case 8: + if (is_lp) break; - case 6: - if (is_lp) - break; - /* Root Port 6 is disabled for all lane configurations - * but config 00b (4x1 links). */ - if ((rpc.strpfusecfg2 >> 14) & 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 7: - if (is_lp) - break; - /* Root Port 7 is disabled in config 11b (1x4 links). */ - if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { - root_port_mark_disable(dev); - return; - } - break; - case 8: - if (is_lp) - break; - /* Root Port 8 is disabled in configs 11b (1x4 links) - * and 10b (2x2 links). */ - if ((rpc.strpfusecfg2 >> 14) & 0x2) { - root_port_mark_disable(dev); - return; - } - break; + /* Root Port 8 is disabled in configs 11b (1x4 links) and 10b (2x2 links). */ + if ((rpc.strpfusecfg2 >> 14) & 0x2) { + root_port_mark_disable(dev); + return; + } + break; } /* Check Pin Ownership. */ diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 8c4a8c1..f40b921 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -95,10 +95,10 @@ static u16 print_pm1_status(u16 pm1_sts) { const char *pm1_sts_bits[] = { - [0] = "TMROF", - [4] = "BM", - [5] = "GBL", - [8] = "PWRBTN", + [0] = "TMROF", + [4] = "BM", + [5] = "GBL", + [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", [14] = "PCIEXPWAK", @@ -127,7 +127,6 @@ outw(events, get_pmbase() + PM1_EN); } - /* * SMI */ @@ -135,7 +134,7 @@ /* Clear and return SMI status register */ static u32 reset_smi_status(void) { - u32 smi_sts = inl(get_pmbase() + SMI_STS); + const u32 smi_sts = inl(get_pmbase() + SMI_STS); outl(smi_sts, get_pmbase() + SMI_STS); return smi_sts; } @@ -144,13 +143,13 @@ static u32 print_smi_status(u32 smi_sts) { const char *smi_sts_bits[] = { - [2] = "BIOS", - [3] = "LEGACY_USB", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", + [2] = "BIOS", + [3] = "LEGACY_USB", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", [10] = "GPI", [11] = "MCSMI", [12] = "DEVMON", @@ -198,7 +197,6 @@ outl(smi_en, get_pmbase() + SMI_EN); } - /* * ALT_GP_SMI */ @@ -298,7 +296,6 @@ } } - /* * TCO */ @@ -324,13 +321,13 @@ static u32 print_tco_status(u32 tco_sts) { const char *tco_sts_bits[] = { - [0] = "NMI2SMI", - [1] = "SW_TCO", - [2] = "TCO_INT", - [3] = "TIMEOUT", - [7] = "NEWCENTURY", - [8] = "BIOSWR", - [9] = "DMISCI", + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", [10] = "DMISMI", [12] = "DMISERR", [13] = "SLVSEL", @@ -368,7 +365,6 @@ enable_gpe(TCOSCI_EN); } - /* * GPE0 */ @@ -377,7 +373,7 @@ static u32 reset_gpe_status(u16 sts_reg, u16 en_reg) { u32 gpe0_sts = inl(get_pmbase() + sts_reg); - u32 gpe0_en = inl(get_pmbase() + en_reg); + u32 gpe0_en = inl(get_pmbase() + en_reg); outl(gpe0_sts, get_pmbase() + sts_reg); @@ -415,12 +411,12 @@ static u32 clear_lpt_gpe_status(void) { const char *gpe0_sts_bits_low[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [8] = "RI", - [9] = "PCI_EXP", + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [8] = "RI", + [9] = "PCI_EXP", [10] = "BATLOW", [11] = "PME", [13] = "PME_B0", @@ -442,8 +438,8 @@ [31] = "GPIO15", }; const char *gpe0_sts_bits_high[] = { - [3] = "GPIO27", - [6] = "WADT", + [3] = "GPIO27", + [6] = "WADT", [24] = "GPIO17", [25] = "GPIO19", [26] = "GPIO21", @@ -455,23 +451,21 @@ }; /* High bits */ - print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2), - gpe0_sts_bits_high); + print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2), gpe0_sts_bits_high); /* Standard GPE and GPIO 0-31 */ - return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN), - gpe0_sts_bits_low); + return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN), gpe0_sts_bits_low); } /* Print, clear, and return LynxPoint-LP GPE0 status */ static u32 clear_lpt_lp_gpe_status(void) { const char *gpe0_sts_4_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [6] = "TCO_SCI", - [7] = "SMB_WAK", - [9] = "PCI_EXP", + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", [10] = "BATLOW", [11] = "PME", [12] = "ME", @@ -490,8 +484,7 @@ print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_3, LP_GPE0_EN_3), 64); /* Standard GPE */ - return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4), - gpe0_sts_4_bits); + return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4), gpe0_sts_4_bits); } /* Clear all GPE status and return "standard" GPE event status */ @@ -528,7 +521,7 @@ /* Enable a standard GPE */ void enable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + const u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; u32 gpe0_en = inl(get_pmbase() + gpe0_reg); gpe0_en |= mask; outl(gpe0_en, get_pmbase() + gpe0_reg); @@ -537,7 +530,7 @@ /* Disable a standard GPE */ void disable_gpe(u32 mask) { - u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; + const u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN; u32 gpe0_en = inl(get_pmbase() + gpe0_reg); gpe0_en &= ~mask; outl(gpe0_en, get_pmbase() + gpe0_reg); diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c index 9f62cd3..de5a90b 100644 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -11,8 +11,7 @@ u32 value; rc = rcba_config; - while (rc->command != RCBA_COMMAND_END) - { + while (rc->command != RCBA_COMMAND_END) { if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { switch (rc->command & RCBA_COMMAND_MASK) { case RCBA_COMMAND_SET: diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ab96d62..9515473 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -311,7 +311,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index e093508..accc51b 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -154,46 +154,39 @@ case PCI_DEVFN(21, 0): /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); - serialio_d21_mode(sio_index, SIO_PIN_INTB, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; case PCI_DEVFN(21, 1): /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 2): /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 3): /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 4): /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTC, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; case PCI_DEVFN(21, 5): /* UART0 */ sio_index = SIO_ID_UART0; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTD, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; case PCI_DEVFN(21, 6): /* UART1 */ sio_index = SIO_ID_UART1; serialio_d21_ltr(bar0); - serialio_d21_mode(sio_index, SIO_PIN_INTD, - config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; case PCI_DEVFN(23, 0): /* SDIO */ sio_index = SIO_ID_SDIO; @@ -221,7 +214,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index e78d85d..48d4349 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -51,12 +51,12 @@ } static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static struct pci_operations smbus_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d57554..5fedc5e 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -43,7 +43,8 @@ enable_pm1(PWRBTN_EN | GBL_EN); disable_gpe(PME_B0_EN); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8bbe3fe..5d58cac 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -350,11 +350,9 @@ { u16 pm1_sts = clear_pm1_status(); - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ + /* While OSPM is not active, poweroff immediately on a power button event */ if (pm1_sts & PWRBTN_STS) { - // power button pressed + /* Power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); disable_pm1_control(-1UL); enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); @@ -387,8 +385,6 @@ printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } - - static void southbridge_smi_tco(void) { u32 tco_sts = clear_tco_status(); @@ -403,19 +399,18 @@ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { - /* BWE is RW, so the SMI was caused by a + /* + * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */ - /* This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. + /* This is the place where we notice someone is + * trying to tinker with the BIOS. We are trying + * to be nice and just ignore it. A more resolute + * answer would be to power down the box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -439,6 +434,7 @@ static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; u32 data, mask = 0; int i; @@ -447,7 +443,7 @@ RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { + for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 2)); } @@ -460,8 +456,8 @@ return; } - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ + /* IOTRAP(2) currently unused */ + /* IOTRAP(1) currently unused */ /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { @@ -476,14 +472,15 @@ // Fall through to debug } - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", - trap_cycle & 0xfffc); - for (i=0; i < 4; i++) - if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + + for (i = 0; i < 4; i++) { + if (IOTRAP(i)) + printk(BIOS_DEBUG, " TRAP = %d\n", i); + } printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", - (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ @@ -538,7 +535,8 @@ int i; u32 smi_sts; - /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -550,8 +548,7 @@ southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); + "SMI_STS[%d] occurred, but no handler available.\n", i); } } } diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8..74ef021 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -127,7 +127,7 @@ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b - * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ + Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 5) | (1 << 2) | (1 << 1); pci_write_config32(dev, 0xdc, reg32); @@ -150,8 +150,7 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 49a6cfc..5ab5a2c 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -258,7 +258,7 @@ reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ - reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); + reg32 |= (1 << 21) | (1 << 20) | (1 << 18) | (1 << 17) | (1 << 8); } /* Avoid writing upper byte as it is write-once */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb908d1a610c10897e1005ba024e433979347fa6 Gerrit-Change-Number: 41943 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: sb/amd/cimx,hudson: Use common enable_usbdebug
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38007 ) Change subject: sb/amd/cimx,hudson: Use common enable_usbdebug ...................................................................... sb/amd/cimx,hudson: Use common enable_usbdebug Due the file's previous location under amd/sb800, usbdebug feature got removed from fam14 with fam10 deprecation, this brings it back. Change-Id: Id658001179898b94fdc179c539b92637af5095b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc D src/southbridge/amd/pi/hudson/enable_usbdebug.c 5 files changed, 5 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38007/1 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b8eb5b9..7c802ca 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -18,10 +18,7 @@ bootblock-y += bootblock.c bootblock-y += early_setup.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c @@ -33,6 +30,7 @@ romstage-y += imc.c ramstage-y += imc.c +all-y += enable_usbdebug.c all-y += reset.c smm-y += smihandler.c smi_util.c diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 47b5990..112aa54 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -17,19 +17,16 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> -#include <arch/io.h> +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ehci.h> -#include <device/pci_def.h> -#include "hudson.h" #define DEBUGPORT_MISC_CONTROL 0x80 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); + pm_write8(0xef, 0x7f); if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2c51648..aad9732 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -36,9 +36,7 @@ romstage-y += ramtop.c ramstage-y += ramtop.c -bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c +all-y += ../../agesa/hudson/enable_usbdebug.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 9d985e6d..b62e559 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -30,10 +30,8 @@ bootblock-y += bootblock.c bootblock-y += early_setup.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c -romstage-y += enable_usbdebug.c romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c romstage-y += smbus.c romstage-y += smbus_spd.c @@ -42,7 +40,6 @@ verstage-y += early_setup.c verstage-$(CONFIG_HUDSON_UART) += uart.c -ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c ramstage-y += hda.c @@ -60,6 +57,7 @@ ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c +all-y += ../../agesa/hudson/enable_usbdebug.c all-y += reset.c smm-y += smihandler.c diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c deleted file mode 100644 index 9ad03dc..0000000 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include "hudson.h" - -#define DEBUGPORT_MISC_CONTROL 0x80 - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); - - if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 0); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 0); - else - return PCI_DEV(0, 0x12, 0); -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; - - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/38007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id658001179898b94fdc179c539b92637af5095b8 Gerrit-Change-Number: 38007 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37825 ) Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... aopen/dxplplusu: Add early GPIO settings Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 109 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37825/1 diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index db55f95..eb51335 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -13,13 +13,120 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <southbridge/intel/i82801dx/i82801dx.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) +#define GPIO_DEV PNP_DEV(0x2e, LPC47M10X2_PME) +#define PME_BASE 0xe00 + +/* JP3 + * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 + * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 + */ + +static void enable_gpio(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* These should go under sb/. */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); + + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_enable(GPIO_DEV, 0); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO0, PME_BASE); + pnp_set_enable(GPIO_DEV, 1); + pnp_exit_conf_state(GPIO_DEV); + + pci_write_config16(dev, GEN1_DEC, PME_BASE | 0x01); +} + +static void gpio_write(u8 addr, u8 val) +{ + outb(val, PME_BASE + addr); +} + +static void gpio_read_write(u8 addr, u8 amask, u8 omask) +{ + u8 val = inb(PME_BASE + addr); + val &= amask; + val |= omask; + outb(val, PME_BASE + addr); +} + +static void configure_gpios(void) +{ + /* GP10-17 */ + gpio_write(0x23, 0x00); /* push-pull output */ + gpio_write(0x24, 0x81); /* open-drain but input ? */ + gpio_write(0x25, 0x01); + gpio_write(0x26, 0x01); + gpio_write(0x27, 0x01); + gpio_write(0x28, 0x01); + gpio_write(0x29, 0x01); + gpio_write(0x2a, 0x00); /* push-pull output */ + + /* GP20-27 */ + gpio_write(0x2b, 0x01); + gpio_write(0x2c, 0x0c); /* nDS1 floppy select */ + gpio_write(0x2d, 0x00); /* push-pull output */ + gpio_write(0x2f, 0x01); + gpio_write(0x30, 0x01); + gpio_write(0x31, 0x01); + gpio_write(0x32, 0x04); /* nIO_SMI */ + + /* GP30-37 */ + gpio_write(0x33, 0x04); /* FAN_TACH2 */ + gpio_write(0x34, 0x01); + gpio_write(0x35, 0x01); + gpio_write(0x36, 0x01); + gpio_write(0x37, 0x01); + gpio_write(0x38, 0x01); + gpio_write(0x39, 0x04); /* nKBDRESET */ + gpio_write(0x3a, 0x04); /* A20M */ + + /* GP40-43 */ + gpio_write(0x3b, 0x84); /* DRVDEN0 open-drain */ + gpio_write(0x3c, 0x04); /* DRVDEN1 push/pull */ + gpio_write(0x3d, 0x84); /* nIO_PME open-drain */ + gpio_write(0x3e, 0x01); + + /* GP50-GP57 to UART signals */ + gpio_write(0x3f, 0x05); + gpio_write(0x40, 0x05); + gpio_write(0x41, 0x05); + gpio_write(0x42, 0x04); + gpio_write(0x43, 0x05); + gpio_write(0x44, 0x04); + gpio_write(0x45, 0x05); + gpio_write(0x46, 0x04); + + /* GP60-GP61 */ + gpio_write(0x47, 0x86); /* LED1 invert open-drain*/ + gpio_write(0x48, 0x81); /* open-drain but input */ + + /* Set initial output bits */ + gpio_read_write(0x4b, 0xff, 0x81); /* GP1 */ + gpio_read_write(0x4c, ~0x01, 0x00); /* GP2 */ + gpio_read_write(0x4d, 0xff, 0x80); /* GP3 */ + gpio_read_write(0x4e, ~0x08, 0x00); /* GP4 */ + + /* LED1 off */ + gpio_write(0x5d, 0x00); +} void bootblock_mainboard_early_init(void) { + enable_gpio(); + configure_gpios(); + /* Get the serial port configured. */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index bc80e87..b3449a1 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -59,7 +59,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d8..7a8fee4 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -92,6 +92,7 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 37825 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [WIP] sb/intel/i82801ix,jx: Adjust TCO watchdog timeout
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41970 ) Change subject: [WIP] sb/intel/i82801ix,jx: Adjust TCO watchdog timeout ...................................................................... [WIP] sb/intel/i82801ix,jx: Adjust TCO watchdog timeout Change-Id: I1514fc8ada9198fae40dce985eb6c5de86a00f51 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41970/1 diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index b2b55ce..5e5e667 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -204,9 +204,9 @@ i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG(HAVE_SMI_HANDLER) - outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ -#endif + if (!permanent_smi_handler()) + outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ + outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ } diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index b4ffcfa..7c6371b 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -203,9 +203,9 @@ i82801jx_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG(HAVE_SMI_HANDLER) - outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ -#endif + if (!permanent_smi_handler()) + outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ + outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/41970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1514fc8ada9198fae40dce985eb6c5de86a00f51 Gerrit-Change-Number: 41970 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] asus/f2a85-m: Fix f2a85-m_pro devicetree
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37619 ) Change subject: [WIP] asus/f2a85-m: Fix f2a85-m_pro devicetree ...................................................................... [WIP] asus/f2a85-m: Fix f2a85-m_pro devicetree Change-Id: I3a4a6aca7058e2576e0e6046c8397c03f1222830 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 1 file changed, 45 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37619/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index f13e3e8..3f08015 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -65,83 +65,64 @@ device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - io 0xe0 = 0x7f - io 0xe1 = 0x10 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0xff - io 0xe5 = 0xff - io 0xe6 = 0xff - io 0xe7 = 0xff - io 0xec = 0x00 - io 0xed = 0xff - io 0xf4 = 0xff - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xf8 = 0x00 + irq 0xe0 = 0x7f + irq 0xe1 = 0x10 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0xff + irq 0xe5 = 0xff + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xec = 0x00 + irq 0xed = 0xff + irq 0xf4 = 0xff + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x00 end - device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - io 0x30 = 0x00 - io 0x60 = 0x00 - io 0x61 = 0x00 - io 0xe0 = 0xff - io 0xe1 = 0xff - io 0xe2 = 0xff - io 0xe3 = 0xff - io 0xe4 = 0xff - io 0xf0 = 0xff - io 0xf1 = 0x28 - io 0xf2 = 0x00 - io 0xf3 = 0x00 - io 0xf4 = 0x08 - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0xff - end + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 io 0x30 = 0xfe - io 0xe0 = 0xff - io 0xe1 = 0x90 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0x7f - io 0xe5 = 0x76 - io 0xe6 = 0x00 - io 0xe7 = 0x00 - io 0xe8 = 0x00 - io 0xe9 = 0x00 - io 0xea = 0x00 - io 0xeb = 0x00 - io 0xee = 0x00 - io 0xf0 = 0xff - io 0xf1 = 0x7b - io 0xf2 = 0x00 - io 0xf4 = 0xff - io 0xf5 = 0xef - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xfe = 0x00 + irq 0xe0 = 0xff + irq 0xe1 = 0x90 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0x7f + irq 0xe5 = 0x76 + irq 0xe6 = 0x00 + irq 0xe7 = 0x00 + irq 0xe8 = 0x00 + irq 0xe9 = 0x00 + irq 0xea = 0x00 + irq 0xeb = 0x00 + irq 0xee = 0x00 + irq 0xf0 = 0xff + irq 0xf1 = 0x7b + irq 0xf2 = 0x00 + irq 0xf4 = 0xff + irq 0xf5 = 0xef + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xfe = 0x00 end device pnp 2e.a on # ACPI - io 0xe6 = 0x4c - io 0xe7 = 0x11 - io 0xf2 = 0x5d + irq 0xe6 = 0x4c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x30 = 0x01 - io 0x60 = 0x02 - io 0x61 = 0x90 - io 0xe2 = 0x7f - io 0xe4 = 0xf1 + io 0x60 = 0x0290 + irq 0xe2 = 0x7f + irq 0xe4 = 0xf1 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f off # GPIO Push-pull/Open-drain selection - io 0xe6 = 7f + irq 0xe6 = 0x7f end device pnp 2e.14 off # PORT80 UART - io 0xe0 = 0x00 + irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep end -- To view, visit https://review.coreboot.org/c/coreboot/+/37619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4a6aca7058e2576e0e6046c8397c03f1222830 Gerrit-Change-Number: 37619 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [WIP] sb/amd: Change to common early SMBus prototypes
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42345 ) Change subject: [WIP] sb/amd: Change to common early SMBus prototypes ...................................................................... [WIP] sb/amd: Change to common early SMBus prototypes Change-Id: I923984bb6c6073a7e0d88183e2cabb2d6e4caba8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/f2a85-m/romstage.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/cimx/sb800/smbus.h M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.h 9 files changed, 19 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42345/1 diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d4b11fc..f40f00c 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -3,7 +3,7 @@ #include <amdblocks/acpimmio.h> #include <arch/io.h> #include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/agesa/hudson/smbus.h> +#include <device/smbus_host.h> #include <stdint.h> void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index a6b1464..eed68e3 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -4,6 +4,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/smbus.h> +#include <device/smbus_host.h> #include <arch/ioapic.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index c418492..4b878ff 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -4,6 +4,7 @@ #define _HUDSON_SMBUS_C_ #include <arch/io.h> +#include <device/smbus_host.h> #include <stdint.h> #include "smbus.h" @@ -43,7 +44,7 @@ return -3; /* timeout */ } -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(uintptr_t smbus_io_base, u8 device) { u8 byte; @@ -70,7 +71,7 @@ return byte; } -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +int do_smbus_send_byte(uintptr_t smbus_io_base, u8 device, u8 val) { u8 byte; @@ -97,8 +98,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(uintptr_t smbus_io_base, u8 device, u8 address) { u8 byte; @@ -128,8 +128,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(uintptr_t smbus_io_base, u8 device, u8 address, u8 val) { u8 byte; diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 5850f2b..2ce0b46 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -47,10 +47,6 @@ #define rcindxp_reg(reg, port, mask, val) \ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 86bde26..c51029b 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -2,8 +2,9 @@ #include <arch/io.h> +#include <console/console.h> +#include <device/smbus_host.h> #include "smbus.h" -#include <console/console.h> /* printk */ static int smbus_wait_until_ready(u32 smbus_io_base) { @@ -45,7 +46,7 @@ return -3; /* timeout */ } -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(uintptr_t smbus_io_base, u8 device) { u8 byte; @@ -75,7 +76,7 @@ return byte; } -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +int do_smbus_send_byte(uintptr_t smbus_io_base, u8 device, u8 val) { u8 byte; @@ -105,7 +106,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +int do_smbus_read_byte(uintptr_t smbus_io_base, u8 device, u8 address) { u8 byte; @@ -138,7 +139,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +int do_smbus_write_byte(uintptr_t smbus_io_base, u8 device, u8 address, u8 val) { u8 byte; diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 0a1b279..58dfeb3 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -49,10 +49,6 @@ #define rcindxp_reg(reg, port, mask, val) \ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 6f9e03c..31a1c67 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -4,6 +4,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/smbus.h> +#include <device/smbus_host.h> #include <arch/ioapic.h> #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index c418492..4b878ff 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -4,6 +4,7 @@ #define _HUDSON_SMBUS_C_ #include <arch/io.h> +#include <device/smbus_host.h> #include <stdint.h> #include "smbus.h" @@ -43,7 +44,7 @@ return -3; /* timeout */ } -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(uintptr_t smbus_io_base, u8 device) { u8 byte; @@ -70,7 +71,7 @@ return byte; } -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +int do_smbus_send_byte(uintptr_t smbus_io_base, u8 device, u8 val) { u8 byte; @@ -97,8 +98,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(uintptr_t smbus_io_base, u8 device, u8 address) { u8 byte; @@ -128,8 +128,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(uintptr_t smbus_io_base, u8 device, u8 address, u8 val) { u8 byte; diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index a367caa..432c8a5 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -47,10 +47,6 @@ #define rcindxp_reg(reg, port, mask, val) \ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); -- To view, visit https://review.coreboot.org/c/coreboot/+/42345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I923984bb6c6073a7e0d88183e2cabb2d6e4caba8 Gerrit-Change-Number: 42345 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: cpu/x86: Define INSTALL_SMM option
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34257 ) Change subject: cpu/x86: Define INSTALL_SMM option ...................................................................... cpu/x86: Define INSTALL_SMM option Change-Id: Ibe827193527b7e16a3360b92bc0be25ceec8d1e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/smm/smm_init.c M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/Makefile.inc M src/drivers/elog/Kconfig M src/drivers/spi/Kconfig M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c 8 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34257/1 diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 60e506c..612557e 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -23,6 +23,16 @@ #include <cpu/x86/smm.h> #include <string.h> +static void smm_install(void) +{ + enable_cache(); + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, _binary_smm_start, + _binary_smm_end - _binary_smm_start); + wbinvd(); + disable_cache(); +} + void smm_init(void) { msr_t msr, syscfg_orig, mtrr_aseg_orig; @@ -55,12 +65,8 @@ msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - disable_cache(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Restore SYSCFG and MTRR */ wrmsr(SYSCFG_MSR, syscfg_orig); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index caee5db..25eee72 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -86,6 +86,11 @@ bool default y +config INSTALL_SMM + bool + default y + depends on HAVE_SMI_HANDLER + config HAVE_SMI_HANDLER bool default n diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149..7855ebf 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -789,6 +789,9 @@ if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 1); + if (!CONFIG(INSTALL_SMM)) + return -1; + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); if (smm_load_module((void *)smbase, smsize, &smm_params)) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 5c7aab3..57013da 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -36,7 +36,7 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +ifeq ($(CONFIG_INSTALL_SMM),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index 4a66e78..7848f7b 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -43,7 +43,7 @@ This option will enable event logging from the preram stage. config ELOG_GSMI - depends on HAVE_SMI_HANDLER + depends on INSTALL_SMM bool "SMI interface to write and clear event log" select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP default n diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502..3013087 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -63,7 +63,7 @@ config SPI_FLASH_SMM bool - depends on HAVE_SMI_HANDLER + depends on INSTALL_SMM help Select this option if you want SPI flash support in SMM. diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 7dfed9d..86e75d0 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -328,7 +328,8 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5d898cc..d50432b 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -157,7 +157,8 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); -- To view, visit https://review.coreboot.org/c/coreboot/+/34257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe827193527b7e16a3360b92bc0be25ceec8d1e6 Gerrit-Change-Number: 34257 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: [TESTONLY] arch/x86: Default INSTALL_SMM off
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34258 ) Change subject: [TESTONLY] arch/x86: Default INSTALL_SMM off ...................................................................... [TESTONLY] arch/x86: Default INSTALL_SMM off Change-Id: Id1e05a3477da73f03fb5653b61a0b4723b8d0503 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34258/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 25eee72..9f68663 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -88,7 +88,7 @@ config INSTALL_SMM bool - default y + default n depends on HAVE_SMI_HANDLER config HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/34258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e05a3477da73f03fb5653b61a0b4723b8d0503 Gerrit-Change-Number: 34258 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: commonlib: Add header for multiboot
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34064 ) Change subject: commonlib: Add header for multiboot ...................................................................... commonlib: Add header for multiboot Copied file from grub2 repository. Change-Id: I1e593b5bb55881cbab87d2c59ff615f546711445 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/commonlib/include/commonlib/multiboot.h 1 file changed, 274 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34064/1 diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h new file mode 100644 index 0000000..7e5ac69 --- /dev/null +++ b/src/commonlib/include/commonlib/multiboot.h @@ -0,0 +1,274 @@ +/* multiboot.h - Multiboot header file. */ +/* Copyright (C) 1999,2003,2007,2008,2009,2010 Free Software Foundation, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ANY + * DEVELOPER OR DISTRIBUTOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR + * IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef MULTIBOOT_HEADER +#define MULTIBOOT_HEADER 1 + +/* How many bytes from the start of the file we search for the header. */ +#define MULTIBOOT_SEARCH 8192 +#define MULTIBOOT_HEADER_ALIGN 4 + +/* The magic field should contain this. */ +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 + +/* This should be in %eax. */ +#define MULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 + +/* Alignment of multiboot modules. */ +#define MULTIBOOT_MOD_ALIGN 0x00001000 + +/* Alignment of the multiboot info structure. */ +#define MULTIBOOT_INFO_ALIGN 0x00000004 + +/* Flags set in the 'flags' member of the multiboot header. */ + +/* Align all boot modules on i386 page (4KB) boundaries. */ +#define MULTIBOOT_PAGE_ALIGN 0x00000001 + +/* Must pass memory information to OS. */ +#define MULTIBOOT_MEMORY_INFO 0x00000002 + +/* Must pass video information to OS. */ +#define MULTIBOOT_VIDEO_MODE 0x00000004 + +/* This flag indicates the use of the address fields in the header. */ +#define MULTIBOOT_AOUT_KLUDGE 0x00010000 + +/* Flags to be set in the 'flags' member of the multiboot info structure. */ + +/* is there basic lower/upper memory information? */ +#define MULTIBOOT_INFO_MEMORY 0x00000001 +/* is there a boot device set? */ +#define MULTIBOOT_INFO_BOOTDEV 0x00000002 +/* is the command-line defined? */ +#define MULTIBOOT_INFO_CMDLINE 0x00000004 +/* are there modules to do something with? */ +#define MULTIBOOT_INFO_MODS 0x00000008 + +/* These next two are mutually exclusive */ + +/* is there a symbol table loaded? */ +#define MULTIBOOT_INFO_AOUT_SYMS 0x00000010 +/* is there an ELF section header table? */ +#define MULTIBOOT_INFO_ELF_SHDR 0X00000020 + +/* is there a full memory map? */ +#define MULTIBOOT_INFO_MEM_MAP 0x00000040 + +/* Is there drive info? */ +#define MULTIBOOT_INFO_DRIVE_INFO 0x00000080 + +/* Is there a config table? */ +#define MULTIBOOT_INFO_CONFIG_TABLE 0x00000100 + +/* Is there a boot loader name? */ +#define MULTIBOOT_INFO_BOOT_LOADER_NAME 0x00000200 + +/* Is there a APM table? */ +#define MULTIBOOT_INFO_APM_TABLE 0x00000400 + +/* Is there video information? */ +#define MULTIBOOT_INFO_VBE_INFO 0x00000800 +#define MULTIBOOT_INFO_FRAMEBUFFER_INFO 0x00001000 + +#ifndef ASM_FILE + +typedef unsigned char multiboot_uint8_t; +typedef unsigned short multiboot_uint16_t; +typedef unsigned int multiboot_uint32_t; +typedef unsigned long long multiboot_uint64_t; + +struct multiboot_header +{ + /* Must be MULTIBOOT_MAGIC - see above. */ + multiboot_uint32_t magic; + + /* Feature flags. */ + multiboot_uint32_t flags; + + /* The above fields plus this one must equal 0 mod 2^32. */ + multiboot_uint32_t checksum; + + /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ + multiboot_uint32_t header_addr; + multiboot_uint32_t load_addr; + multiboot_uint32_t load_end_addr; + multiboot_uint32_t bss_end_addr; + multiboot_uint32_t entry_addr; + + /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ + multiboot_uint32_t mode_type; + multiboot_uint32_t width; + multiboot_uint32_t height; + multiboot_uint32_t depth; +}; + +/* The symbol table for a.out. */ +struct multiboot_aout_symbol_table +{ + multiboot_uint32_t tabsize; + multiboot_uint32_t strsize; + multiboot_uint32_t addr; + multiboot_uint32_t reserved; +}; +typedef struct multiboot_aout_symbol_table multiboot_aout_symbol_table_t; + +/* The section header table for ELF. */ +struct multiboot_elf_section_header_table +{ + multiboot_uint32_t num; + multiboot_uint32_t size; + multiboot_uint32_t addr; + multiboot_uint32_t shndx; +}; +typedef struct multiboot_elf_section_header_table multiboot_elf_section_header_table_t; + +struct multiboot_info +{ + /* Multiboot info version number */ + multiboot_uint32_t flags; + + /* Available memory from BIOS */ + multiboot_uint32_t mem_lower; + multiboot_uint32_t mem_upper; + + /* "root" partition */ + multiboot_uint32_t boot_device; + + /* Kernel command line */ + multiboot_uint32_t cmdline; + + /* Boot-Module list */ + multiboot_uint32_t mods_count; + multiboot_uint32_t mods_addr; + + union + { + multiboot_aout_symbol_table_t aout_sym; + multiboot_elf_section_header_table_t elf_sec; + } u; + + /* Memory Mapping buffer */ + multiboot_uint32_t mmap_length; + multiboot_uint32_t mmap_addr; + + /* Drive Info buffer */ + multiboot_uint32_t drives_length; + multiboot_uint32_t drives_addr; + + /* ROM configuration table */ + multiboot_uint32_t config_table; + + /* Boot Loader Name */ + multiboot_uint32_t boot_loader_name; + + /* APM table */ + multiboot_uint32_t apm_table; + + /* Video */ + multiboot_uint32_t vbe_control_info; + multiboot_uint32_t vbe_mode_info; + multiboot_uint16_t vbe_mode; + multiboot_uint16_t vbe_interface_seg; + multiboot_uint16_t vbe_interface_off; + multiboot_uint16_t vbe_interface_len; + + multiboot_uint64_t framebuffer_addr; + multiboot_uint32_t framebuffer_pitch; + multiboot_uint32_t framebuffer_width; + multiboot_uint32_t framebuffer_height; + multiboot_uint8_t framebuffer_bpp; +#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 +#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 +#define MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT 2 + multiboot_uint8_t framebuffer_type; + union + { + struct + { + multiboot_uint32_t framebuffer_palette_addr; + multiboot_uint16_t framebuffer_palette_num_colors; + }; + struct + { + multiboot_uint8_t framebuffer_red_field_position; + multiboot_uint8_t framebuffer_red_mask_size; + multiboot_uint8_t framebuffer_green_field_position; + multiboot_uint8_t framebuffer_green_mask_size; + multiboot_uint8_t framebuffer_blue_field_position; + multiboot_uint8_t framebuffer_blue_mask_size; + }; + }; +}; +typedef struct multiboot_info multiboot_info_t; + +struct multiboot_color +{ + multiboot_uint8_t red; + multiboot_uint8_t green; + multiboot_uint8_t blue; +}; + +struct multiboot_mmap_entry +{ + multiboot_uint32_t size; + multiboot_uint64_t addr; + multiboot_uint64_t len; +#define MULTIBOOT_MEMORY_AVAILABLE 1 +#define MULTIBOOT_MEMORY_RESERVED 2 +#define MULTIBOOT_MEMORY_ACPI_RECLAIMABLE 3 +#define MULTIBOOT_MEMORY_NVS 4 +#define MULTIBOOT_MEMORY_BADRAM 5 + multiboot_uint32_t type; +} GRUB_PACKED; +typedef struct multiboot_mmap_entry multiboot_memory_map_t; + +struct multiboot_mod_list +{ + /* the memory used goes from bytes 'mod_start' to 'mod_end-1' inclusive */ + multiboot_uint32_t mod_start; + multiboot_uint32_t mod_end; + + /* Module command line */ + multiboot_uint32_t cmdline; + + /* padding to take it to 16 bytes (must be zero) */ + multiboot_uint32_t pad; +}; +typedef struct multiboot_mod_list multiboot_module_t; + +/* APM BIOS info. */ +struct multiboot_apm_info +{ + grub_uint16_t version; + grub_uint16_t cseg; + grub_uint32_t offset; + grub_uint16_t cseg_16; + grub_uint16_t dseg; + grub_uint16_t flags; + grub_uint16_t cseg_len; + grub_uint16_t cseg_16_len; + grub_uint16_t dseg_len; +}; + +#endif /* ! ASM_FILE */ + +#endif /* ! MULTIBOOT_HEADER */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e593b5bb55881cbab87d2c59ff615f546711445 Gerrit-Change-Number: 34064 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020