coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: commonlib: Apply coding style for multiboot.h
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34065 ) Change subject: commonlib: Apply coding style for multiboot.h ...................................................................... commonlib: Apply coding style for multiboot.h Add includes, change whitespace. Remove multiboot_ prefixes and some typedefs. Change-Id: I4ebc83c3c737349bf9bc10d141a9ce9047eda1ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/commonlib/include/commonlib/multiboot.h 1 file changed, 124 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34065/1 diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h index 7e5ac69..2aae2ea 100644 --- a/src/commonlib/include/commonlib/multiboot.h +++ b/src/commonlib/include/commonlib/multiboot.h @@ -22,6 +22,8 @@ #ifndef MULTIBOOT_HEADER #define MULTIBOOT_HEADER 1 +#include <stdint.h> + /* How many bytes from the start of the file we search for the header. */ #define MULTIBOOT_SEARCH 8192 #define MULTIBOOT_HEADER_ALIGN 4 @@ -89,186 +91,177 @@ #define MULTIBOOT_INFO_VBE_INFO 0x00000800 #define MULTIBOOT_INFO_FRAMEBUFFER_INFO 0x00001000 -#ifndef ASM_FILE - -typedef unsigned char multiboot_uint8_t; -typedef unsigned short multiboot_uint16_t; -typedef unsigned int multiboot_uint32_t; -typedef unsigned long long multiboot_uint64_t; - struct multiboot_header { - /* Must be MULTIBOOT_MAGIC - see above. */ - multiboot_uint32_t magic; + /* Must be MULTIBOOT_MAGIC - see above. */ + uint32_t magic; - /* Feature flags. */ - multiboot_uint32_t flags; + /* Feature flags. */ + uint32_t flags; - /* The above fields plus this one must equal 0 mod 2^32. */ - multiboot_uint32_t checksum; + /* The above fields plus this one must equal 0 mod 2^32. */ + uint32_t checksum; - /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ - multiboot_uint32_t header_addr; - multiboot_uint32_t load_addr; - multiboot_uint32_t load_end_addr; - multiboot_uint32_t bss_end_addr; - multiboot_uint32_t entry_addr; + /* These are only valid if MULTIBOOT_AOUT_KLUDGE is set. */ + uint32_t header_addr; + uint32_t load_addr; + uint32_t load_end_addr; + uint32_t bss_end_addr; + uint32_t entry_addr; - /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ - multiboot_uint32_t mode_type; - multiboot_uint32_t width; - multiboot_uint32_t height; - multiboot_uint32_t depth; + /* These are only valid if MULTIBOOT_VIDEO_MODE is set. */ + uint32_t mode_type; + uint32_t width; + uint32_t height; + uint32_t depth; }; /* The symbol table for a.out. */ struct multiboot_aout_symbol_table { - multiboot_uint32_t tabsize; - multiboot_uint32_t strsize; - multiboot_uint32_t addr; - multiboot_uint32_t reserved; + uint32_t tabsize; + uint32_t strsize; + uint32_t addr; + uint32_t reserved; }; -typedef struct multiboot_aout_symbol_table multiboot_aout_symbol_table_t; /* The section header table for ELF. */ struct multiboot_elf_section_header_table { - multiboot_uint32_t num; - multiboot_uint32_t size; - multiboot_uint32_t addr; - multiboot_uint32_t shndx; + uint32_t num; + uint32_t size; + uint32_t addr; + uint32_t shndx; }; -typedef struct multiboot_elf_section_header_table multiboot_elf_section_header_table_t; struct multiboot_info { - /* Multiboot info version number */ - multiboot_uint32_t flags; + /* Multiboot info version number */ + uint32_t flags; - /* Available memory from BIOS */ - multiboot_uint32_t mem_lower; - multiboot_uint32_t mem_upper; + /* Available memory from BIOS */ + uint32_t mem_lower; + uint32_t mem_upper; - /* "root" partition */ - multiboot_uint32_t boot_device; + /* "root" partition */ + uint32_t boot_device; - /* Kernel command line */ - multiboot_uint32_t cmdline; + /* Kernel command line */ + uint32_t cmdline; - /* Boot-Module list */ - multiboot_uint32_t mods_count; - multiboot_uint32_t mods_addr; + /* Boot-Module list */ + uint32_t mods_count; + uint32_t mods_addr; - union - { - multiboot_aout_symbol_table_t aout_sym; - multiboot_elf_section_header_table_t elf_sec; - } u; + union + { + struct multiboot_aout_symbol_table aout_sym; + struct multiboot_elf_section_header_table elf_sec; + } u; - /* Memory Mapping buffer */ - multiboot_uint32_t mmap_length; - multiboot_uint32_t mmap_addr; + /* Memory Mapping buffer */ + uint32_t mmap_length; + uint32_t mmap_addr; - /* Drive Info buffer */ - multiboot_uint32_t drives_length; - multiboot_uint32_t drives_addr; + /* Drive Info buffer */ + uint32_t drives_length; + uint32_t drives_addr; - /* ROM configuration table */ - multiboot_uint32_t config_table; + /* ROM configuration table */ + uint32_t config_table; - /* Boot Loader Name */ - multiboot_uint32_t boot_loader_name; + /* Boot Loader Name */ + uint32_t boot_loader_name; - /* APM table */ - multiboot_uint32_t apm_table; + /* APM table */ + uint32_t apm_table; - /* Video */ - multiboot_uint32_t vbe_control_info; - multiboot_uint32_t vbe_mode_info; - multiboot_uint16_t vbe_mode; - multiboot_uint16_t vbe_interface_seg; - multiboot_uint16_t vbe_interface_off; - multiboot_uint16_t vbe_interface_len; + /* Video */ + uint32_t vbe_control_info; + uint32_t vbe_mode_info; + uint16_t vbe_mode; + uint16_t vbe_interface_seg; + uint16_t vbe_interface_off; + uint16_t vbe_interface_len; - multiboot_uint64_t framebuffer_addr; - multiboot_uint32_t framebuffer_pitch; - multiboot_uint32_t framebuffer_width; - multiboot_uint32_t framebuffer_height; - multiboot_uint8_t framebuffer_bpp; -#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 -#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 + uint64_t framebuffer_addr; + uint32_t framebuffer_pitch; + uint32_t framebuffer_width; + uint32_t framebuffer_height; + uint8_t framebuffer_bpp; + +#define MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED 0 +#define MULTIBOOT_FRAMEBUFFER_TYPE_RGB 1 #define MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT 2 - multiboot_uint8_t framebuffer_type; - union - { - struct - { - multiboot_uint32_t framebuffer_palette_addr; - multiboot_uint16_t framebuffer_palette_num_colors; - }; - struct - { - multiboot_uint8_t framebuffer_red_field_position; - multiboot_uint8_t framebuffer_red_mask_size; - multiboot_uint8_t framebuffer_green_field_position; - multiboot_uint8_t framebuffer_green_mask_size; - multiboot_uint8_t framebuffer_blue_field_position; - multiboot_uint8_t framebuffer_blue_mask_size; - }; - }; -}; -typedef struct multiboot_info multiboot_info_t; - -struct multiboot_color -{ - multiboot_uint8_t red; - multiboot_uint8_t green; - multiboot_uint8_t blue; + uint8_t framebuffer_type; + union + { + struct + { + uint32_t framebuffer_palette_addr; + uint16_t framebuffer_palette_num_colors; + }; + struct + { + uint8_t framebuffer_red_field_position; + uint8_t framebuffer_red_mask_size; + uint8_t framebuffer_green_field_position; + uint8_t framebuffer_green_mask_size; + uint8_t framebuffer_blue_field_position; + uint8_t framebuffer_blue_mask_size; + }; + }; }; -struct multiboot_mmap_entry +struct color { - multiboot_uint32_t size; - multiboot_uint64_t addr; - multiboot_uint64_t len; + uint8_t red; + uint8_t green; + uint8_t blue; +}; + +struct mmap_entry +{ + uint32_t size; + uint64_t addr; + uint64_t len; #define MULTIBOOT_MEMORY_AVAILABLE 1 #define MULTIBOOT_MEMORY_RESERVED 2 #define MULTIBOOT_MEMORY_ACPI_RECLAIMABLE 3 #define MULTIBOOT_MEMORY_NVS 4 #define MULTIBOOT_MEMORY_BADRAM 5 - multiboot_uint32_t type; -} GRUB_PACKED; -typedef struct multiboot_mmap_entry multiboot_memory_map_t; + uint32_t type; +} __packed; -struct multiboot_mod_list +struct mod_list { - /* the memory used goes from bytes 'mod_start' to 'mod_end-1' inclusive */ - multiboot_uint32_t mod_start; - multiboot_uint32_t mod_end; + /* the memory used goes from bytes + * 'mod_start' to 'mod_end-1' inclusive + */ + uint32_t mod_start; + uint32_t mod_end; - /* Module command line */ - multiboot_uint32_t cmdline; + /* Module command line */ + uint32_t cmdline; - /* padding to take it to 16 bytes (must be zero) */ - multiboot_uint32_t pad; + /* padding to take it to 16 bytes (must be zero) */ + uint32_t pad; }; -typedef struct multiboot_mod_list multiboot_module_t; +#if 0 /* APM BIOS info. */ -struct multiboot_apm_info +struct apm_info { - grub_uint16_t version; - grub_uint16_t cseg; - grub_uint32_t offset; - grub_uint16_t cseg_16; - grub_uint16_t dseg; - grub_uint16_t flags; - grub_uint16_t cseg_len; - grub_uint16_t cseg_16_len; - grub_uint16_t dseg_len; + grub_uint16_t version; + grub_uint16_t cseg; + grub_uint32_t offset; + grub_uint16_t cseg_16; + grub_uint16_t dseg; + grub_uint16_t flags; + grub_uint16_t cseg_len; + grub_uint16_t cseg_16_len; + grub_uint16_t dseg_len; }; - -#endif /* ! ASM_FILE */ +#endif #endif /* ! MULTIBOOT_HEADER */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ebc83c3c737349bf9bc10d141a9ce9047eda1ac Gerrit-Change-Number: 34065 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: arch/x86: Add MULTIBOOT run-time info
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34066 ) Change subject: arch/x86: Add MULTIBOOT run-time info ...................................................................... arch/x86: Add MULTIBOOT run-time info Change-Id: Ia14a49e37e308b05cde4dbadf0e4596bbebc9933 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M payloads/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/boot.c A src/arch/x86/multiboot.c M src/arch/x86/tables.c M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/multiboot.h M src/lib/coreboot_table.c 8 files changed, 182 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34066/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44..a7a16ef 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -114,6 +114,15 @@ In order to reduce the size secondary payloads take up in the ROM chip they can be compressed using the LZMA algorithm. +config MULTIBOOT_RUNTIME + bool "Fill MultiBoot runtime info for payload" + depends on ARCH_X86 + default n + +config MULTIBOOT_RUNTIME_CMDLINE + string "Commandline passed to payload in MultiBoot runtime info" + depends on MULTIBOOT_RUNTIME + menu "Secondary Payloads" config COREINFO_SECONDARY_PAYLOAD diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 025b933..290b7ed 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -312,6 +312,7 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c +ramstage-y += multiboot.c ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 5f60f13..41a5eff 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -11,10 +11,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <commonlib/helpers.h> +#include <commonlib/multiboot.h> #include <console/console.h> #include <program_loading.h> #include <ip_checksum.h> +#include <stdint.h> #include <symbols.h> int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) @@ -30,6 +33,18 @@ void arch_prog_run(struct prog *prog) { + uint32_t eax = 0, ebx = 0; + + if (ENV_PAYLOAD_LOADER && (prog_type(prog) == PROG_PAYLOAD)) { + if (CONFIG(MULTIBOOT_RUNTIME)) { + void *info = cbmem_find(CBMEM_ID_MULTIBOOT); + if (info) { + eax = MULTIBOOT_BOOTLOADER_MAGIC; + ebx = (uintptr_t)info; + } + } + } + __asm__ volatile ( #ifdef __x86_64__ "jmp *%%rdi\n" @@ -37,6 +52,6 @@ "jmp *%%edi\n" #endif - :: "D"(prog_entry(prog)) + :: "D"(prog_entry(prog)), "a" (eax), "b" (ebx) ); } diff --git a/src/arch/x86/multiboot.c b/src/arch/x86/multiboot.c new file mode 100644 index 0000000..56822a4 --- /dev/null +++ b/src/arch/x86/multiboot.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootmem.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <commonlib/multiboot.h> +#include <memrange.h> +#include <string.h> + +#define MAX_MMAP_ENTRIES 32 +#define MAX_CMDLINE_LEN 100 + +/* Memory reserved for CBMEM may grow here, do this step early. */ +void alloc_multiboot_info(void) +{ + struct multiboot_info *info; + uintptr_t current, cmdline_offset, mmap_offset; + + current = sizeof(*info); + current = ALIGN_UP(current, 8); + + /* Static reserver for command line. */ + cmdline_offset = current; + current += MAX_CMDLINE_LEN; + current = ALIGN_UP(current, 8); + + /* Static reserve of mmap entries. */ + mmap_offset = current; + current += MAX_MMAP_ENTRIES * sizeof(struct mmap_entry); + current = ALIGN_UP(current, 8); + + info = cbmem_add(CBMEM_ID_MULTIBOOT, current); + if (!info) + return; + + memset(info, 0, sizeof(*info)); + info->cmdline = (uintptr_t)(char *)info + cmdline_offset; + info->mmap_addr = (uintptr_t)(char *)info + mmap_offset; +} + +static bool add_mmap_entry(const struct range_entry *r, void *arg) +{ + struct multiboot_info *info = arg; + struct mmap_entry *m; + uintptr_t new_entry; + + if (info->mmap_length >= MAX_MMAP_ENTRIES * sizeof(*m)) + return false; + + new_entry = info->mmap_addr + info->mmap_length; + info->mmap_length += sizeof(*m); + + m = (void *)new_entry; + m->size = sizeof(*m) - sizeof(m->size); + m->addr = range_entry_base(r); + m->len = range_entry_size(r); + + /* Don't differentiate between unavailable ranges. */ + if (range_entry_tag(r) != BM_MEM_RAM) { + m->type = MULTIBOOT_MEMORY_RESERVED; + return true; + } + + m->type = MULTIBOOT_MEMORY_AVAILABLE; + + /* Range crossing or starting at 1 MiB boundary determines + * available upper memory. */ + if ((m->addr <= 1 * MiB) && (m->addr + m->len > 1 * MiB)) + info->mem_upper = (m->addr + m->len - 1 * MiB) / KiB; + + /* Specs says to report max 640 KiB of lower memory, + * report that if we have any memory at all. */ + info->mem_lower = 640; + + return true; +} + +static void fill_memory(struct multiboot_info *info) +{ + if (!info || !info->mmap_addr) + return; + + bootmem_walk_os_mem(add_mmap_entry, info); + + if (info->mem_lower || info->mem_upper) + info->flags |= MULTIBOOT_INFO_MEMORY; + + if (info->mmap_length) + info->flags |= MULTIBOOT_INFO_MEM_MAP; +} + +const char *__weak multiboot_runtime_cmdline(void) +{ + return CONFIG_MULTIBOOT_RUNTIME_CMDLINE; +} + +static void fill_cmdline(struct multiboot_info *info) +{ + const char *s; + size_t len; + + if (!info || !info->cmdline) + return; + + s = multiboot_runtime_cmdline(); + if (!s) + return; + + /* Do not allow partial lines. */ + len = strnlen(s, 2 * MAX_CMDLINE_LEN); + if (len >= MAX_CMDLINE_LEN) + return; + + memcpy((char *)(uintptr_t)info->cmdline, s, len); + info->flags |= MULTIBOOT_INFO_CMDLINE; +} + +void fill_multiboot_info(void) +{ + struct multiboot_info *info; + + info = cbmem_find(CBMEM_ID_MULTIBOOT); + if (!info) + return; + + fill_memory(info); + fill_cmdline(info); +} diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 0baa58e..58f7fa3 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <commonlib/multiboot.h> #include <console/console.h> #include <bootmem.h> #include <bootstate.h> @@ -260,6 +261,10 @@ /* Align up to page boundary for historical consistency. */ forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); + /* We need to do this before bootmem generation. */ + if (CONFIG(MULTIBOOT_RUNTIME)) + alloc_multiboot_info(); + /* Tell static analysis we know value is left unused. */ (void)rom_table_end; } diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 2236c95..ff21a13 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -45,6 +45,7 @@ #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c +#define CBMEM_ID_MULTIBOOT 0x2badb002 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_POWER_STATE 0x50535454 @@ -108,6 +109,7 @@ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ + { CBMEM_ID_MULTIBOOT, "MULTIBOOT " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ diff --git a/src/commonlib/include/commonlib/multiboot.h b/src/commonlib/include/commonlib/multiboot.h index 2aae2ea..8f338e8 100644 --- a/src/commonlib/include/commonlib/multiboot.h +++ b/src/commonlib/include/commonlib/multiboot.h @@ -264,4 +264,8 @@ }; #endif +void alloc_multiboot_info(void); +void fill_multiboot_info(void); +const char *multiboot_runtime_cmdline(void); + #endif /* ! MULTIBOOT_HEADER */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index df75698..fc42ef7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -16,6 +16,7 @@ */ #include <arch/cbconfig.h> +#include <commonlib/multiboot.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -599,6 +600,11 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + /* We need to do this before checksum is calculated. + * FIXME: Find better place for the call. */ + if (CONFIG(MULTIBOOT_RUNTIME)) + fill_multiboot_info(); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia14a49e37e308b05cde4dbadf0e4596bbebc9933 Gerrit-Change-Number: 34066 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: AGESA: Restrict use of -fno-strict-aliasing
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34799 ) Change subject: AGESA: Restrict use of -fno-strict-aliasing ...................................................................... AGESA: Restrict use of -fno-strict-aliasing Only apply the flag for libagesa -class. Change-Id: I462d1cb03d6dfb0e3d9ecd4e8323ddf280479466 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/34799/1 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index d672cf4..4d3224e 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -10,9 +10,10 @@ classes-y += libagesa libagesa-y = libagesa-generic-ccopts += -D__LIBAGESA__ +libagesa-generic-ccopts += -fno-strict-aliasing libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) -AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/34799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I462d1cb03d6dfb0e3d9ecd4e8323ddf280479466 Gerrit-Change-Number: 34799 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: [TESTONLY] arch/x86: experiment with SMM defaults
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34128 ) Change subject: [TESTONLY] arch/x86: experiment with SMM defaults ...................................................................... [TESTONLY] arch/x86: experiment with SMM defaults Change-Id: I332a80ffd9c5dff3efe33e14eabe334cb248296c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/cpu/x86/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/lenovo/g505s/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 23 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34128/1 diff --git a/src/Kconfig b/src/Kconfig index 778f169..38209ee 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -543,10 +543,6 @@ file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. -config HAVE_SMI_HANDLER - bool - default n - config PCI_IO_CFG_EXT bool default n diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 608afd7..b7ca154 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -98,6 +98,10 @@ bool default y +config HAVE_SMI_HANDLER + bool + default n + config SMM_TSEG bool default n diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 7fa04ee..0398e01 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -26,7 +26,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index b80019e..e5d6f8e 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -25,7 +25,6 @@ select HAVE_OPTION_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a930f60..70552b0 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,7 +56,6 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ba82565..76eb7b1 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -64,7 +64,6 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER select SMM_TSEG select POSTCAR_STAGE select POSTCAR_CONSOLE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1f819ea..8080e9d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,7 +46,6 @@ select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 43c2906..73c2c66 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f83..7fc5632 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -20,7 +20,6 @@ select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 801800c..7865726 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,7 +19,6 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5e405db..9620df3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -67,7 +67,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 273ce30..9af407d 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -36,7 +36,6 @@ select POSTCAR_STAGE select C_ENVIRONMENT_BOOTBLOCK select IOAPIC - select HAVE_SMI_HANDLER select SMM_TSEG select CACHE_MRC_SETTINGS select PARALLEL_MP diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 5228bb7..c28bdc8 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -28,7 +28,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index f71148f..3a94dc29 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -22,7 +22,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SMM_TSEG - select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE select HAVE_FSP_BIN diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index f0b2918..7359814 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -24,7 +24,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fb455d2..dbeb5dc 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -39,7 +39,6 @@ select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER - select HAVE_SMI_HANDLER select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..0c9dde0 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -32,7 +32,6 @@ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 12640b3..944fdd8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -18,7 +18,6 @@ bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_SMI_HANDLER select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d6e938..f250a76 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,7 +20,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 5edb8a1..48ce9c3 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,7 +23,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMM diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b423eca..43c4280 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -24,7 +24,6 @@ select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 00eb413..e67f5f7 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -23,7 +23,6 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC select HAVE_USBDEBUG - select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 67e20be..2697120 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -28,7 +28,6 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC - select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM -- To view, visit https://review.coreboot.org/c/coreboot/+/34128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I332a80ffd9c5dff3efe33e14eabe334cb248296c Gerrit-Change-Number: 34128 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: arch/x86: Drop some HAVE_SMI_HANDLER guards
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34158 ) Change subject: arch/x86: Drop some HAVE_SMI_HANDLER guards ...................................................................... arch/x86: Drop some HAVE_SMI_HANDLER guards Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc 7 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34158/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 93a8bbb..7e84e41 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -56,7 +56,7 @@ romstage-y += tsc_freq.c romstage-y += southbridge.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -89,7 +89,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index babd878..230640a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -50,7 +50,7 @@ bootblock-y += southbridge.c bootblock-y += nb_util.c bootblock-$(CONFIG_SPI_FLASH) += spi.c -bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +bootblock-y += smi_util.c romstage-y += BiosCallOuts.c romstage-y += i2c.c @@ -68,7 +68,7 @@ romstage-y += southbridge.c romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +romstage-y += smi_util.c verstage-y += gpio.c verstage-y += i2c.c @@ -105,7 +105,7 @@ ramstage-y += smbus.c ramstage-y += ramtop.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index cfd8149..1f12db7 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -67,7 +67,7 @@ ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 1aba88b..d957778 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += gpio.c ramstage-y += iou_complto.c ramstage-y += smmrelocate.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c ramstage-y += vtd.c smm-y += pmutil.c smm-y += smihandler.c diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index cd0a1d5..5603a20 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -32,7 +32,8 @@ ramstage-y += imc.c smm-y += smihandler.c smi_util.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-y += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c8949b0..ac198aa 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -56,7 +56,7 @@ ramstage-y += sd.c ramstage-y += sm.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-y += smi_util.c ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..8be9234 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -38,10 +38,11 @@ ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += acpi.c +ramstage-y += pmutil.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-y += smihandler.c me_9.x.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f7196febd091325eddceb77870acd40dbe332f9 Gerrit-Change-Number: 34158 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 5

Change in ...coreboot[master]: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31361 to review the following change. Change subject: [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs ...................................................................... [WIP] AGESA: Fix CAR_GLOBAL use for AP CPUs The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise CAR_GLOBALs may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all. Does not fix family14. Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/gcccar.inc M src/vendorcode/amd/agesa/f14/gcccar.inc M src/vendorcode/amd/agesa/f15tn/gcccar.inc M src/vendorcode/amd/agesa/f16kb/gcccar.inc 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31361/1 diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 95dd74d..e6dba6a 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1451,6 +1451,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index b13e02a..e96c7f7 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1767,6 +1767,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index c818d97..26745c9 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1131,6 +1131,13 @@ 0: _WRMSR # + # All cores must see BSP stack region that is also used to + # communicate global variables before DRAM is up. + mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250 + _RDMSR + or $0x1e000000, %eax + _WRMSR + # Enable MTRR defaults as UC type mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF _RDMSR # Read-modify-write the MSR -- To view, visit https://review.coreboot.org/c/coreboot/+/31361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8a389ca0d7a88c779f27f4ead0d9581465edfd Gerrit-Change-Number: 31361 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: [WIP] sb/intel: Always raise SMI with APM CNT FINALIZE
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41992 ) Change subject: [WIP] sb/intel: Always raise SMI with APM_CNT_FINALIZE ...................................................................... [WIP] sb/intel: Always raise SMI with APM_CNT_FINALIZE At least google/stout has APM_CNT_FINALIZE handler in mainboard, so mainboard_smi_apmc() should be an unconditional call. Change-Id: I7b6450e0c8436e1c6113d54b7987b6b486908ed9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smihandler.c 6 files changed, 21 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41992/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7bfde3f..170f4b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -827,10 +827,7 @@ spi_finalize_ops(); /* Call SMM finalize() handlers before resume */ - if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || - acpi_is_wakeup_s3()) { - apm_control(APM_CNT_FINALIZE); - } + apm_control(APM_CNT_FINALIZE); } void intel_southbridge_override_spi( diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f778f7a..721cfe4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -210,6 +210,9 @@ void southbridge_finalize_all(void) { + if (!CONFIG(INTEL_CHIPSET_LOCKDOWN) && !acpi_is_wakeup_s3()) + return; + intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_sandybridge_finalize_smm(); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 9a115f7..bdfd8e0 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -720,10 +720,7 @@ spi_finalize_ops(); /* Call SMM finalize() handlers before resume */ - if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || - acpi_is_wakeup_s3()) { - apm_control(APM_CNT_FINALIZE); - } + apm_control(APM_CNT_FINALIZE); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index a881f33..b8ff520 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -168,6 +168,9 @@ void southbridge_finalize_all(void) { + if (!CONFIG(INTEL_CHIPSET_LOCKDOWN) && !acpi_is_wakeup_s3()) + return; + intel_me_finalize_smm(); intel_pch_finalize_smm(); intel_ironlake_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d3a066e..782ecb5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -913,8 +913,7 @@ { spi_finalize_ops(); - if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) - apm_control(APM_CNT_FINALIZE); + apm_control(APM_CNT_FINALIZE); } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8bbe3fe..74e0802 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -287,11 +287,7 @@ return; } - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - + southbridge_finalize_all(); chipset_finalized = 1; break; case APM_CNT_CST_CONTROL: @@ -556,3 +552,14 @@ } } } + +void southbridge_finalize_all(void) +{ + if (!CONFIG(INTEL_CHIPSET_LOCKDOWN) && !acpi_is_wakeup_s3()) + return; + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6450e0c8436e1c6113d54b7987b6b486908ed9 Gerrit-Change-Number: 41992 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34229 ) Change subject: [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE ...................................................................... [WIP] arch/x86: Drop TSC_SYNC_MFENCE and TSC_SYNC_LFENCE Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/x86/Kconfig M src/include/cpu/x86/tsc.h M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/skylake/Kconfig 21 files changed, 4 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34229/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 2b8a8c7..af6605e 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -25,7 +25,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 98be6f6..eff4e18 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -5,7 +5,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SSE2 - select TSC_SYNC_LFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select ACPI_HUGE_LOWMEM_BACKUP diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 099f54c..d760cf9 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -24,7 +24,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI - select TSC_SYNC_LFENCE select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 0aab0a2..2627265 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -31,7 +31,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 84a2241..127e8ce 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,7 +16,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_MP select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 2399c41..f1033fa 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2d6a387..8333e1d 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -9,7 +9,6 @@ select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 6c65907..8c9c5a1 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -15,7 +15,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_FIXED_XIP_ROM_SIZE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 4ed1119..6117480 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -15,7 +15,6 @@ select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 49f4302..a4c3ce2 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index b31b01d..3724cc1 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -8,7 +8,6 @@ select SSE2 select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT - select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0bf2f0d..dd7c8d9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -30,22 +30,6 @@ help Expose monotonic time using the TSC. -config TSC_SYNC_LFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an lfence instruction in order to synchronize - rdtsc. This is true for all modern AMD CPUs. - -config TSC_SYNC_MFENCE - bool - default n - help - The CPU driver should select this if the CPU needs - to execute an mfence instruction in order to synchronize - rdtsc. This is true for all modern Intel CPUs. - config NO_FIXED_XIP_ROM_SIZE bool default n diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 23b74b2..8b7807b 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,10 +3,12 @@ #include <stdint.h> -#if CONFIG(TSC_SYNC_MFENCE) +#if CONFIG(CPU_INTEL_COMMON) #define TSC_SYNC "mfence\n" -#elif CONFIG(TSC_SYNC_LFENCE) +#elif CONFIG(DRIVERS_AMD_PI) || CONFIG(CPU_AMD_MODEL_10XXX) #define TSC_SYNC "lfence\n" +#elif CONFIG(TSC_MONOTONIC_TIMER) +#error "Undefined rdtsc() fence" #else #define TSC_SYNC #endif diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d654e94..6f46706 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -35,7 +35,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 465df60..622fad9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME - select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 46ef898..29be910 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -28,7 +28,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d2a776..bf8133b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -37,7 +37,6 @@ select SPI_FLASH select SSE2 select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select USE_GENERIC_FSP_CAR_INC select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6bec847..663dbdc 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -28,7 +28,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 3bf608e..d9b86b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -53,7 +53,6 @@ select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 38777c5..820b396 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3d7a530..94b6585 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -75,7 +75,6 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER - select TSC_SYNC_MFENCE config CPU_INTEL_NUM_FIT_ENTRIES int -- To view, visit https://review.coreboot.org/c/coreboot/+/34229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib712fa2c10931da90062bd853318079d5c144f48 Gerrit-Change-Number: 34229 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: [WIP] cpu/x86/lapic: Use udelay() from LAPIC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36530 ) Change subject: [WIP] cpu/x86/lapic: Use udelay() from LAPIC_MONOTONIC_TIMER ...................................................................... [WIP] cpu/x86/lapic: Use udelay() from LAPIC_MONOTONIC_TIMER TBD: PI/AGESA reconfigures LAPIC breaking udelay(). TBD: Use of init_timer() is wrong for smm-y Change-Id: I3c982e4121586e932856f390a12ce125f964b2e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family15tn/Makefile.inc D src/cpu/amd/agesa/family15tn/udelay.c M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/amd/pi/00630F01/fixme.c D src/cpu/amd/pi/00630F01/udelay.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/cpu/amd/pi/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/apic_timer.c 13 files changed, 7 insertions(+), 160 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36530/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b1fde2d..96bf043 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -24,7 +24,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 8522eb2..3554196 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -17,8 +17,6 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-y += udelay.c - subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/tsc diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c deleted file mode 100644 index 898f6c1..0000000 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * udelay() implementation for SMI handlers - * This is neat in that it never writes to hardware registers, and thus does - * not modify the state of the hardware while servicing SMIs. - */ - -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/tsc.h> -#include <delay.h> -#include <stdint.h> - -void udelay(uint32_t us) -{ - uint8_t fid, did, pstate_idx; - uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; - msr_t msr; - const uint64_t tsc_base = 100000000; - - /* Get initial timestamp before we do the math */ - tsc_start = rdtscll(); - - /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(PS_STS_REG); - pstate_idx = msr.lo & 0x07; - - /* Get FID and VID for current P-State */ - msr = rdmsr(PSTATE_0_MSR + pstate_idx); - - /* Extract the FID and VID values */ - fid = msr.lo & 0x3f; - did = (msr.lo >> 6) & 0x7; - - /* Calculate the CPU clock (from base freq of 100MHz) */ - tsc_clock = tsc_base * (fid + 0x10) / (1 << did); - - /* Now go on and wait */ - tsc_wait_ticks = (tsc_clock / 1000000) * us; - - do { - tsc_now = rdtscll(); - } while (tsc_now - tsc_wait_ticks < tsc_start); -} diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index ad4f5f4..d81628b 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ select ARCH_RAMSTAGE_X86_32 select SSE2 select TSC_SYNC_LFENCE - select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select CAR_GLOBAL_MIGRATION diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 8522eb2..3554196 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -17,8 +17,6 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-y += udelay.c - subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/tsc diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062..6c88bb6 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -86,7 +86,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)){ + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c deleted file mode 100644 index d4bf45f..0000000 --- a/src/cpu/amd/pi/00630F01/udelay.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * udelay() implementation for SMI handlers - * This is neat in that it never writes to hardware registers, and thus does not - * modify the state of the hardware while servicing SMIs. - */ - -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/tsc.h> -#include <delay.h> -#include <stdint.h> - -void udelay(uint32_t us) -{ - uint8_t fid, did, pstate_idx; - uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; - msr_t msr; - const uint64_t tsc_base = 100000000; - - /* Get initial timestamp before we do the math */ - tsc_start = rdtscll(); - - /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(PS_STS_REG); - pstate_idx = msr.lo & 0x07; - - /* Get FID and VID for current P-State */ - msr = rdmsr(PSTATE_0_MSR + pstate_idx); - - /* Extract the FID and VID values */ - fid = msr.lo & 0x3f; - did = (msr.lo >> 6) & 0x7; - - /* Calculate the CPU clock (from base freq of 100MHz) */ - tsc_clock = tsc_base * (fid + 0x10) / (1 << did); - - /* Now go on and wait */ - tsc_wait_ticks = (tsc_clock / 1000000) * us; - - do { - tsc_now = rdtscll(); - } while (tsc_now - tsc_wait_ticks < tsc_start); -} diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b..1e52864 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -92,7 +92,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cb..40c8a40 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -97,7 +97,7 @@ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (CONFIG(UDELAY_LAPIC)) { + if (CONFIG(LAPIC_MONOTONIC_TIMER)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index b33302e..8addecb 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -23,7 +23,6 @@ select ARCH_RAMSTAGE_X86_32 select DRIVERS_AMD_PI select TSC_SYNC_LFENCE - select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 01700f2..556a54d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -17,13 +17,8 @@ Allow APs to do other work after initialization instead of going to sleep. -config UDELAY_LAPIC - bool - default n - config LAPIC_MONOTONIC_TIMER def_bool n - depends on UDELAY_LAPIC help Expose monotonic time using the local APIC. diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..058e25b 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,9 +1,9 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S -romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +romstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +ramstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c +postcar-$(CONFIG_LAPIC_MONOTONIC_TIMER) += apic_timer.c bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 58836b5..a2c4c4a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -19,6 +19,7 @@ #include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <timer.h> void init_timer(void) { @@ -32,33 +33,6 @@ lapic_write(LAPIC_TMICT, 0xffffffff); } -void udelay(u32 usecs) -{ - u32 start, value, ticks, timer_fsb; - - if (!thread_yield_microseconds(usecs)) - return; - - timer_fsb = get_timer_fsb(); - if (!timer_fsb || (lapic_read(LAPIC_LVTT) & - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) { - init_timer(); - timer_fsb = get_timer_fsb(); - } - - /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz - */ - ticks = usecs * timer_fsb; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while ((start - value) < ticks); -} - -#if CONFIG(LAPIC_MONOTONIC_TIMER) -#include <timer.h> - static struct monotonic_counter { int initialized; struct mono_time time; @@ -102,4 +76,3 @@ /* Save result. */ *mt = mono_counter->time; } -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c982e4121586e932856f390a12ce125f964b2e7 Gerrit-Change-Number: 36530 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: arch/x86: Use TSC_MONOTONIC_TIMER for timestamps
by Kyösti Mälkki (Code Review) 31 Jul '20

31 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36529 ) Change subject: arch/x86: Use TSC_MONOTONIC_TIMER for timestamps ...................................................................... arch/x86: Use TSC_MONOTONIC_TIMER for timestamps Implementations with monotonic_timer can take benefit of the generic implementations of timestamp_get() and timestamp_freq_tick_mhz() in lib/timestamp.c. Change-Id: I0adfbdeb456fbd6769fbd7f39421f797369876a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/cpu/x86/tsc/Makefile.inc R src/cpu/x86/tsc/timestamp.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/monotonic_timer.c 6 files changed, 12 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36529/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e774..6c1dd48 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -291,21 +291,6 @@ the acpigen function. Default is \_PR.CPxx. Note that you need the \ escape character in the string. -config COLLECT_TIMESTAMPS_NO_TSC - bool - default n - depends on COLLECT_TIMESTAMPS - help - Use a non-TSC platform-dependent source for timestamps. - -config COLLECT_TIMESTAMPS_TSC - bool - default y if !COLLECT_TIMESTAMPS_NO_TSC - default n - depends on COLLECT_TIMESTAMPS - help - Use the TSC as the timestamp source. - config PAGING_IN_CACHE_AS_RAM bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8d00174..ffbf0f3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -110,7 +110,6 @@ bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-y += id.S @@ -198,8 +197,6 @@ # which just calls verstage(). verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c -verstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c - verstage-libs ?= $(eval $(call early_x86_assembly_entry_rule,verstage)) @@ -230,7 +227,6 @@ romstage-y += memmove.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += walkcbfs.S romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) @@ -268,7 +264,6 @@ postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c -postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c LDFLAGS_postcar += -Map $(objcbfs)/postcar.map @@ -316,7 +311,6 @@ ramstage-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S -ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..0afd05b 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -4,3 +4,9 @@ verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c + +bootblock-$(CONFIG_LAPIC_MONOTONIC_TIMER) += timestamp.c +ramstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += timestamp.c +romstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += timestamp.c +verstage-$(CONFIG_LAPIC_MONOTONIC_TIMER) += timestamp.c +postcar-$(CONFIG_LAPIC_MONOTONIC_TIMER) += timestamp.c diff --git a/src/arch/x86/timestamp.c b/src/cpu/x86/tsc/timestamp.c similarity index 86% rename from src/arch/x86/timestamp.c rename to src/cpu/x86/tsc/timestamp.c index 8cf0f96..0100021 100644 --- a/src/arch/x86/timestamp.c +++ b/src/cpu/x86/tsc/timestamp.c @@ -21,10 +21,6 @@ int timestamp_tick_freq_mhz(void) { - /* Chipsets that have a constant TSC provide this value correctly. */ - if (tsc_constant_rate()) - return tsc_freq_mhz(); - /* Filling tick_freq_mhz = 0 in timestamps-table will trigger * userspace utility to try deduce it from the running system. */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff..1db6d55 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,7 +46,6 @@ select ARCH_RAMSTAGE_X86_32 select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES - select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY diff --git a/src/soc/amd/stoneyridge/monotonic_timer.c b/src/soc/amd/stoneyridge/monotonic_timer.c index 7ea571f..00514da 100644 --- a/src/soc/amd/stoneyridge/monotonic_timer.c +++ b/src/soc/amd/stoneyridge/monotonic_timer.c @@ -15,17 +15,11 @@ #include <cpu/x86/msr.h> #include <timer.h> -#include <timestamp.h> #define CU_PTSC_MSR 0xc0010280 #define PTSC_FREQ_MHZ 100 -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, timestamp_get()); -} - -uint64_t timestamp_get(void) +static uint64_t ptsc_get(void) { unsigned long long val; msr_t msr; @@ -36,3 +30,8 @@ return val / PTSC_FREQ_MHZ; } + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, ptsc_get()); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0adfbdeb456fbd6769fbd7f39421f797369876a8 Gerrit-Change-Number: 36529 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 10

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020