coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/zork: Add Bluetooth reset gpios to devicetree
by Rob Barnes (Code Review) 06 Aug '20

06 Aug '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42832 ) Change subject: mb/google/zork: Add Bluetooth reset gpios to devicetree ...................................................................... mb/google/zork: Add Bluetooth reset gpios to devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Add bluetooth reset gpio 143 to dalboz baseboard devicetree BUG=b:157580724 TEST=Boot Ezkinil, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42832/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index d541529..d20115f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -161,6 +161,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_143)" device usb 2.5 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 47ff8ba..c1d8288 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -189,6 +189,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.5 on end end end @@ -208,6 +209,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" device usb 2.1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/42832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Gerrit-Change-Number: 42832 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

6 27

Change in coreboot[master]: cpu/intel/haswell/smmrelocate.c: Align with Broadwell
by Angel Pons (Code Review) 06 Aug '20

06 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42621 ) Change subject: cpu/intel/haswell/smmrelocate.c: Align with Broadwell ...................................................................... cpu/intel/haswell/smmrelocate.c: Align with Broadwell Change-Id: I8c2589141551028622a0ae1a183a74ebceb2acfb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42621/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 0f7585a..5e4e028 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -111,7 +111,7 @@ msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; - printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* Determine if the processor supports saving state in MSRs. If so, * enable it before the non-BSPs run so that SMM relocation can occur @@ -284,6 +284,6 @@ * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, + pci_write_config8(pcidev_path_on_root(PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2589141551028622a0ae1a183a74ebceb2acfb Gerrit-Change-Number: 42621 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42035 ) Change subject: google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup ...................................................................... google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup Current the DRAM control only support 4GB DDR, add more large size DDR support to meet the market requirement. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c 8 files changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42035/1 diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index 6b53bcc..c339d54 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 74b642d..e8dcb82 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 5617ff9..65a54da 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index fc31a18f..0f5003a 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index df37f1a..b44bba3 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index a5764d2..06ec402 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 97a8e2d..3c16325 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 2de4be0..606d7c8 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#include <soc/emi.h> +#include <soc/dramc_param.h> struct sdram_params params = { .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } -- To view, visit https://review.coreboot.org/c/coreboot/+/42035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Gerrit-Change-Number: 42035 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

4 23

Change in coreboot[master]: soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup
by Duan Huayang (Code Review) 06 Aug '20

06 Aug '20

Duan Huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41949 ) Change subject: soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup ...................................................................... soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup Current the DRAM control only support 4GB DDR, add more large size DDR support to meet the market requirement. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_configs.c M src/soc/mediatek/mt8183/dramc_param.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/emi.h 7 files changed, 175 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41949/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 73bd2f8..649ab10 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -30,3 +30,8 @@ return &params; } + +u32 get_rom_code(void) +{ + return ram_code(); +} diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c index 54d2209..546ad3a 100644 --- a/src/soc/mediatek/mt8183/dramc_param.c +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -31,12 +31,37 @@ return validate_dramc_param(blob) == DRAMC_SUCCESS; } +static void set_ddr_size_type(struct dramc_param *param) +{ + u32 ramcode = get_rom_code(); + u16 ddr_size_type = DDR_TYPE_2CH_2RK_4GB_2_2; + + switch (ramcode) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + ddr_size_type = DDR_TYPE_2CH_2RK_4GB_2_2; + break; + default: + break; + } + + param->header.ddr_size_type = ddr_size_type; +} + int initialize_dramc_param(void *blob, u16 config) { struct dramc_param *param = blob; struct dramc_param_header *hdr = &param->header; memset(blob, 0, sizeof(*param)); + + set_ddr_size_type(param); hdr->magic = DRAMC_PARAM_HEADER_MAGIC; hdr->size = sizeof(*param); hdr->version = DRAMC_PARAM_HEADER_VERSION; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b557550..6d5db3a 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -131,6 +131,19 @@ dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u16 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -2678,6 +2691,54 @@ } } +u8 get_dram_infor_after_cal(void) +{ + u8 vendor_id, density, max_density = 0; + u64 dram_size, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + dram_size = 0x20000000; + break; + case 0x1: + dram_size = 0x30000000; + break; + case 0x2: + dram_size = 0x40000000; + break; + case 0x3: + dram_size = 0x60000000; + break; + case 0x4: + dram_size = 0x80000000; + break; + case 0x5: + dram_size = 0xc0000000; + break; + case 0x6: + dram_size = 0x100000000L; + break; + default: + dram_size = 0; + } + if (dram_size > max_size) { + max_size = dram_size; + max_density = density; + } + dramc_show("RK%d size %dGb, density:%d\n", rk, (u32)(dram_size >> 27), max_density); + } + + return max_density; +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index c03f945..6a465e3 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -50,10 +50,10 @@ }; struct optimize_ac_time { - u8 rfc; - u8 rfc_05t; - u8 rfc_pb; - u8 rfrc_pb05t; + u8 trfc; + u8 trfrc_05t; + u8 trfc_pb; + u8 trfrc_pb_05t; u16 tx_ref_cnt; }; @@ -320,30 +320,79 @@ setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(u8 freq_group) +static void dramc_ac_timing_optimize(u8 freq_group, u8 density) { - struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, - .rfrc_pb05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, - .rfrc_pb05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, - .rfrc_pb05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, - .rfrc_pb05t = 1, .tx_ref_cnt = 138}, + u8 rfcab_grp = 0; + u8 trfc = 101, trfrc_05t = 0, trfc_pb = 44, trfrc_pb_05t = 0, tx_ref_cnt = 118; + enum tRFCAB{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM}; + + struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = { + /* LP4X_DDR1600 */ + {{.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0, .trfrc_pb_05t = 0, .tx_ref_cnt = 32}, + {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6, .trfrc_pb_05t = 0, .tx_ref_cnt = 42}, + {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16, .trfrc_pb_05t = 0, .tx_ref_cnt = 62}, + {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26, .trfrc_pb_05t = 0, .tx_ref_cnt = 82}}, + /* LP4X_DDR2400 */ + {{.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6, .trfrc_pb_05t = 0, .tx_ref_cnt = 46}, + {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15, .trfrc_pb_05t = 0, .tx_ref_cnt = 61}, + {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, .trfrc_pb_05t = 0, .tx_ref_cnt = 91}, + {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45, .trfrc_pb_05t = 0, .tx_ref_cnt = 121}}, + /* LP4X_DDR3200 */ + {{.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12, .trfrc_pb_05t = 0, .tx_ref_cnt = 59}, + {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24, .trfrc_pb_05t = 0, .tx_ref_cnt = 79}, + {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44, .trfrc_pb_05t = 0, .tx_ref_cnt = 119}, + {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64, .trfrc_pb_05t = 0, .tx_ref_cnt = 159}}, + /* LP4X_DDR3600 */ + {{.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16, .trfrc_pb_05t = 0, .tx_ref_cnt = 68}, + {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, .trfrc_pb_05t = 0, .tx_ref_cnt = 92}, + {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53, .trfrc_pb_05t = 1, .tx_ref_cnt = 138}, + {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76, .trfrc_pb_05t = 1, .tx_ref_cnt = 185}}, }; + switch (density) { + /* 4Gb per die (2Gb per channel) */ + case 0x0: + rfcab_grp = tRFCAB_130; + break; + /* 6Gb per die (3Gb per channel) or 8Gb per die (4Gb per channel) */ + case 0x1: + case 0x2: + rfcab_grp = tRFCAB_180; + break; + /* 12Gb per die (6Gb per channel) or 16Gb per die (8Gb per channel) */ + case 0x3: + case 0x4: + rfcab_grp = tRFCAB_280; + break; + /* 24Gb per die (12Gb per channel) or 32Gb per die (16Gb per channel) */ + case 0x5: + case 0x6: + rfcab_grp = tRFCAB_380; + break; + default: + dramc_dbg("density err!\n"); + break; + } + + trfc = rf_cab_opt[freq_group][rfcab_grp].trfc; + trfrc_05t = rf_cab_opt[freq_group][rfcab_grp].trfrc_05t; + trfc_pb = rf_cab_opt[freq_group][rfcab_grp].trfc_pb; + trfrc_pb_05t = rf_cab_opt[freq_group][rfcab_grp].trfrc_pb_05t; + tx_ref_cnt = rf_cab_opt[freq_group][rfcab_grp].tx_ref_cnt; + dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb_05t %d\n", + density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb_05t); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + 0xff << 16, trfc << 16); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + 0x1 << 2, trfrc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + 0x3ff << 0, tx_ref_cnt << 0); clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + 0xff << 0, trfc_pb << 0); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); + 0x1 << 1, trfrc_pb_05t << 1); } } @@ -495,6 +544,7 @@ struct dram_shared_data *shared, const int shuffle, bool *first_run) { + u8 density = 0; const u8 *freq_tbl; if (CONFIG(MT8183_DRAM_EMCP)) @@ -519,7 +569,9 @@ dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; - dramc_ac_timing_optimize(freq_group); + + density = get_dram_infor_after_cal(); + dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index 7b3ba7e..8cadb28 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -11,7 +11,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 2, + DRAMC_PARAM_HEADER_VERSION = 3, }; enum DRAMC_PARAM_STATUS_CODES { @@ -38,11 +38,18 @@ DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, }; +enum DRAMC_PARAM_DDR_SIZE_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + struct dramc_param_header { u32 status; /* DRAMC_PARAM_STATUS_CODES */ u32 magic; - u32 version; - u32 size; /* size of whole dramc_param */ + u32 version; /* DRAMC_PARAM_HEADER_VERSION */ + u32 size; /* size of whole dramc_param */ + u16 ddr_size_type; /* DRAMC_PARAM_DDR_SIZE_TYPE */ u16 config; /* DRAMC_PARAM_CONFIG */ u16 flags; /* DRAMC_PARAM_FLAGS */ u32 checksum; diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 0de86f6..6aa8f0b 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -107,5 +107,6 @@ u32 get_shu_freq(u8 shu); void dramc_hw_dqsosc(u8 chn); void dramc_dqs_precalculation_preset(void); +u8 get_dram_infor_after_cal(void); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 3862d54..46921fe 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -86,6 +86,7 @@ extern const u8 phy_mapping[CHANNEL_MAX][16]; +u32 get_rom_code(void); int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/41949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Gerrit-Change-Number: 41949 Gerrit-PatchSet: 1 Gerrit-Owner: Duan Huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

7 44

Change in coreboot[master]: soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42194 ) Change subject: soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value ...................................................................... soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value Different density should correspond to different tRFCab and tRFCpb timing. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 157 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42194/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0f91d18..531be8b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -131,6 +131,19 @@ dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -2695,6 +2708,55 @@ } } +void get_dram_info_after_cal(u8 *density_result) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5); + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8); + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + *density_result = max_density; +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index c03f945..54891b5 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -50,10 +50,10 @@ }; struct optimize_ac_time { - u8 rfc; - u8 rfc_05t; - u8 rfc_pb; - u8 rfrc_pb05t; + u8 trfc; + u8 trfrc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; u16 tx_ref_cnt; }; @@ -320,30 +320,102 @@ setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } -static void dramc_ac_timing_optimize(u8 freq_group) +static void dramc_ac_timing_optimize(u8 freq_group, u8 density) { - struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, - .rfrc_pb05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, - .rfrc_pb05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, - .rfrc_pb05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, - .rfrc_pb05t = 1, .tx_ref_cnt = 138}, + u8 rfcab_grp = 0; + u8 trfc, trfrc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + enum tRFCAB { + tRFCAB_130 = 0, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM }; + const struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX][tRFCAB_NUM] = { + [LP4X_DDR1600] = { + [tRFCAB_130] = {.trfc = 14, .trfrc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 32}, + [tRFCAB_180] = {.trfc = 24, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 42}, + [tRFCAB_280] = {.trfc = 44, .trfrc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 62}, + [tRFCAB_380] = {.trfc = 64, .trfrc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 82} + }, + [LP4X_DDR2400] = { + [tRFCAB_130] = {.trfc = 27, .trfrc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 46}, + [tRFCAB_180] = {.trfc = 42, .trfrc_05t = 0, .trfc_pb = 15, + .trfrc_pb05t = 0, .tx_ref_cnt = 61}, + [tRFCAB_280] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 91}, + [tRFCAB_380] = {.trfc = 102, .trfrc_05t = 0, .trfc_pb = 45, + .trfrc_pb05t = 0, .tx_ref_cnt = 121} + }, + [LP4X_DDR3200] = { + [tRFCAB_130] = {.trfc = 40, .trfrc_05t = 0, .trfc_pb = 12, + .trfrc_pb05t = 0, .tx_ref_cnt = 59}, + [tRFCAB_180] = {.trfc = 60, .trfrc_05t = 0, .trfc_pb = 24, + .trfrc_pb05t = 0, .tx_ref_cnt = 79}, + [tRFCAB_280] = {.trfc = 100, .trfrc_05t = 0, .trfc_pb = 44, + .trfrc_pb05t = 0, .tx_ref_cnt = 119}, + [tRFCAB_380] = {.trfc = 140, .trfrc_05t = 0, .trfc_pb = 64, + .trfrc_pb05t = 0, .tx_ref_cnt = 159} + }, + [LP4X_DDR3600] = { + [tRFCAB_130] = {.trfc = 48, .trfrc_05t = 1, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + [tRFCAB_180] = {.trfc = 72, .trfrc_05t = 0, .trfc_pb = 30, + .trfrc_pb05t = 0, .tx_ref_cnt = 92}, + [tRFCAB_280] = {.trfc = 118, .trfrc_05t = 1, .trfc_pb = 53, + .trfrc_pb05t = 1, .tx_ref_cnt = 138}, + [tRFCAB_380] = {.trfc = 165, .trfrc_05t = 0, .trfc_pb = 76, + .trfrc_pb05t = 1, .tx_ref_cnt = 185} + }, + }; + + switch (density) { + case 0x0: + rfcab_grp = tRFCAB_130; + break; + case 0x1: + case 0x2: + rfcab_grp = tRFCAB_180; + break; + case 0x3: + case 0x4: + rfcab_grp = tRFCAB_280; + break; + case 0x5: + case 0x6: + rfcab_grp = tRFCAB_380; + break; + default: + dramc_err("density err!\n"); + break; + } + + const struct optimize_ac_time *ac_tim = &rf_cab_opt[freq_group][rfcab_grp]; + trfc = ac_tim->trfc; + trfrc_05t = ac_tim->trfrc_05t; + trfc_pb = ac_tim->trfc_pb; + trfrc_pb05t = ac_tim->trfrc_pb05t; + tx_ref_cnt = ac_tim->tx_ref_cnt; + dramc_dbg("Density %d, trfc %u, trfrc_05t %d, tx_ref_cnt %d, trfc_pb %d, trfrc_pb05t %d\n", + density, trfc, trfrc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 16, rf_cab_opt[freq_group].rfc << 16); + 0xff << 16, trfc << 16); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + 0x1 << 2, trfrc_05t << 2); clrsetbits32(&ch[chn].ao.shu[0].actim[4], - 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + 0x3ff << 0, tx_ref_cnt << 0); clrsetbits32(&ch[chn].ao.shu[0].actim[3], - 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + 0xff << 0, trfc_pb << 0); clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, - 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); + 0x1 << 1, trfrc_pb05t << 1); } } @@ -495,6 +567,7 @@ struct dram_shared_data *shared, const int shuffle, bool *first_run) { + u8 density; const u8 *freq_tbl; if (CONFIG(MT8183_DRAM_EMCP)) @@ -519,7 +592,8 @@ dramc_dbg("Start K (current clock: %u\n", params->frequency); if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0) return -1; - dramc_ac_timing_optimize(freq_group); + get_dram_info_after_cal(&density); + dramc_ac_timing_optimize(freq_group, density); dramc_dbg("K finished (current clock: %u\n", params->frequency); dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 0de86f6..daaa14f 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -107,5 +107,6 @@ u32 get_shu_freq(u8 shu); void dramc_hw_dqsosc(u8 chn); void dramc_dqs_precalculation_preset(void); +void get_dram_info_after_cal(u8 *density); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545 Gerrit-Change-Number: 42194 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
by Duan huayang (Code Review) 06 Aug '20

06 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42193 ) Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ...................................................................... soc/mediatek/mt8183: Fix some programming errors of DRAMC setting Fix some programming errors. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 56 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index cb64e50..082f6bb 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -57,9 +57,9 @@ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle); - setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } @@ -890,12 +890,11 @@ clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -949,11 +948,11 @@ clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { @@ -1057,7 +1056,7 @@ clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); - clrbits32(&ch[0].phy.pll3, 0x1 < 0); + clrbits32(&ch[0].phy.pll3, 0x1 << 0); setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3); @@ -1088,7 +1087,11 @@ for (size_t b = 0; b < 2; b++) setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 5bffc42..580d435 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -48,10 +48,12 @@ broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + } impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -92,7 +94,7 @@ if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4 ); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -151,9 +153,6 @@ sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -203,7 +202,10 @@ SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); } static void transfer_pll_to_spm_control(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b557550..0f91d18 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -366,12 +366,30 @@ clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); } -static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) { + u8 dvs_delay; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0]; - clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + switch (freq_group) { + case LP4X_DDR1600: + dvs_delay = 5; + break; + case LP4X_DDR2400: + dvs_delay = 4; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + dvs_delay = 3; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20); clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } @@ -409,7 +427,13 @@ dramc_hw_gating_onoff(chn, false); clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30); + } + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits32(&ch[chn].ao.mrs, 0x3 << 24); setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -417,21 +441,14 @@ clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); - dramc_rx_input_delay_tracking_init_by_freq(chn); + dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group); setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); else - setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - } - - for (size_t r = 0; r < 2; r++) { - for (size_t b = 0; b < 2; b++) - clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], - (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Gerrit-Change-Number: 42193 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: sb/intel/i82801gx: Use PCI bitwise ops
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42191 ) Change subject: sb/intel/i82801gx: Use PCI bitwise ops ...................................................................... sb/intel/i82801gx: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c 9 files changed, 50 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/42191/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 205fb0d..0ce3316 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -196,37 +196,21 @@ struct resource *res; u32 codec_mask; u8 reg8; - u32 reg32; // ESD - reg32 = pci_read_config32(dev, 0x134); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x134, reg32); + pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16); // Link1 description - reg32 = pci_read_config32(dev, 0x140); - reg32 &= 0xff00ffff; - reg32 |= (2 << 16); - pci_write_config32(dev, 0x140, reg32); + pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16); // Port VC0 Resource Control Register - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~0x000000ff, 1); // VCi traffic class - reg8 = pci_read_config8(dev, 0x44); - reg8 |= (7 << 0); // TC7 - pci_write_config8(dev, 0x44, reg8); + pci_or_config8(dev, 0x44, 7 << 0); // TC7 // VCi Resource Control - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - reg32 |= (1 << 24); // VCi ID - reg32 |= (0x80 << 0); // VCi map - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -246,14 +230,11 @@ reg8 = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status #if 0 /* Set routing pin */ pci_write_config32(dev, 0xf8, 0x0); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index b0f73e8..308dfc8 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -6,13 +6,8 @@ static void enable_spi_prefetch(void) { - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); + /* Prefetching and Caching Enabled */ + pci_update_config8(PCI_DEV(0, 0x1f, 0), BIOS_CNTL, ~(3 << 2), 2 << 2); } void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a913873..61fc8d9 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -61,9 +61,6 @@ #if ENV_ROMSTAGE void i82801gx_early_init(void) { - uint8_t reg8; - uint32_t reg32; - enable_smbus(); /* Setting up Southbridge. In the northbridge code. */ @@ -84,22 +81,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD); /* USB transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17)); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27)); /* Enable IOAPIC */ RCBA8(OIC) = 0x03; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 0bfe8eb..e11e89d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -252,18 +252,13 @@ static void i82801gx_configure_cstates(struct device *dev) { - u8 reg8; - - reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration - reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown - pci_write_config8(dev, 0xa9, reg8); + // Enable Popup & Popdown + pci_or_config8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2)); // Set Deeper Sleep configuration to recommended values - reg8 = pci_read_config8(dev, 0xaa); - reg8 &= 0xf0; - reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us - reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us - pci_write_config8(dev, 0xaa, reg8); + // Deeper Sleep to Stop CPU: 34-40us + // Deeper Sleep to Sleep: 15us + pci_update_config8(dev, 0xaa, ~0x0f, (2 << 2) | (2 << 0)); } static void i82801gx_rtc_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 7472438..d72bd81 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -10,29 +10,21 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); - /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 &= ~PCI_BRIDGE_CTL_SERR; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + /* Disable parity error response and SERR */ + pci_and_config16(dev, PCI_BRIDGE_CONTROL, + ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR)); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); + pci_update_config8(dev, SMLT, 0x07, 0x04 << 3); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index adf0e49..c297ac9 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -41,7 +41,6 @@ static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); @@ -50,41 +49,29 @@ /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it - pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); + pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 |= PCI_BRIDGE_CTL_NO_ISA; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, + PCI_BRIDGE_CTL_NO_ISA); /* Enable IO xAPIC on this PCIe port */ - reg32 = pci_read_config32(dev, 0xd8); - reg32 |= (1 << 7); - pci_write_config32(dev, 0xd8, reg32); + pci_or_config32(dev, 0xd8, 1 << 7); /* Enable Backbone Clock Gating */ - reg32 = pci_read_config32(dev, 0xe1); - reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); - pci_write_config32(dev, 0xe1, reg32); + pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); /* Set VC0 transaction class */ - reg32 = pci_read_config32(dev, 0x114); - reg32 &= 0xffffff00; - reg32 |= 1; - pci_write_config32(dev, 0x114, reg32); + pci_update_config32(dev, 0x114, ~0x000000ff, 1); /* Mask completion timeouts */ - reg32 = pci_read_config32(dev, 0x148); - reg32 |= (1 << 14); - pci_write_config32(dev, 0x148, reg32); + pci_or_config32(dev, 0x148, 1 << 14); /* Enable common clock configuration */ // Are there cases when we don't want that? - reg16 = pci_read_config16(dev, 0x50); - reg16 |= (1 << 6); - pci_write_config16(dev, 0x50, reg16); + pci_or_config16(dev, 0x50, 1 << 6); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); @@ -95,7 +82,7 @@ printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; pci_write_config16(dev, 0x06, reg16); diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index c98a645..1718253 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -61,11 +61,10 @@ if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ - pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); + pci_update_config8(dev, SATA_MAP, (u8)~0xc3, 0x40); } else { - /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); + /* Set map to ide */ + pci_and_config8(dev, SATA_MAP, (u8)~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -73,7 +72,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u8 ports; /* Get the chip configuration */ @@ -96,11 +94,10 @@ case SATA_MODE_IDE_LEGACY_COMBINED: printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0); + /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); pci_write_config8(dev, 0x09, 0x80); @@ -149,9 +146,7 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf @@ -192,23 +187,15 @@ pci_write_config8(dev, 0xa0, 0x78); pci_write_config8(dev, 0xa6, 0x22); pci_write_config8(dev, 0xa0, 0x88); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0c0c0; - reg32 |= 0x1b1b1212; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0c0c0, 0x1b1b1212); pci_write_config8(dev, 0xa0, 0x8c); - reg32 = pci_read_config32(dev, 0xa4); - reg32 &= 0xc0c0ff00; - reg32 |= 0x121200aa; - pci_write_config32(dev, 0xa4, reg32); + pci_update_config32(dev, 0xa4, 0xc0c0ff00, 0x121200aa); pci_write_config8(dev, 0xa0, 0x00); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); /* Sata Initialization Register */ - reg32 = pci_read_config32(dev, SATA_IR); - reg32 |= SCRD; // due to some bug - pci_write_config32(dev, SATA_IR, reg32); + pci_or_config32(dev, SATA_IR, SCRD); // due to some bug } static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8ce57df..08ba3d7 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -9,8 +9,6 @@ static void usb_init(struct device *dev) { - u8 reg8; - /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); @@ -20,9 +18,7 @@ pci_write_config8(dev, 0xca, 0x00); // Yes. Another Erratum - reg8 = pci_read_config8(dev, 0xca); - reg8 |= (1 << 0); - pci_write_config8(dev, 0xca, reg8); + pci_or_config8(dev, 0xca, 1 << 0); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7..0a66136 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -14,19 +14,13 @@ struct resource *res; u8 *base; u32 reg32; - u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - reg32 = pci_read_config32(dev, 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(dev, 0xdc, reg32); + pci_or_config32(dev, 0xdc, (1 << 31) | (1 << 27)); - reg32 = pci_read_config32(dev, 0xfc); - reg32 &= ~(3 << 2); - reg32 |= (2 << 2) | (1 << 29) | (1 << 17); - pci_write_config32(dev, 0xfc, reg32); + pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ res = find_resource(dev, 0x10); @@ -35,9 +29,7 @@ write32(base + 0x24, reg32); /* workaround */ - reg8 = pci_read_config8(dev, 0x84); - reg8 |= (1 << 4); - pci_write_config8(dev, 0x84, reg8); + pci_or_config8(dev, 0x84, 1 << 4); printk(BIOS_DEBUG, "done.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Gerrit-Change-Number: 42191 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: payload/seabios: Fix CBFS location on APL platform
by Felix Singer (Code Review) 04 Aug '20

04 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32327 Change subject: payload/seabios: Fix CBFS location on APL platform ...................................................................... payload/seabios: Fix CBFS location on APL platform Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M payloads/external/SeaBIOS/Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32327/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..594d37a 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -39,6 +39,9 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config -- To view, visit https://review.coreboot.org/c/coreboot/+/32327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Gerrit-Change-Number: 32327 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

8 32

Change in coreboot[master]: nb/intel/gm45: Use PCI bitwise ops
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42189 ) Change subject: nb/intel/gm45: Use PCI bitwise ops ...................................................................... nb/intel/gm45: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/romstage.c 8 files changed, 74 insertions(+), 140 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42189/1 diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 4491746..1783880 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -40,12 +40,12 @@ CxDRBy_BOUND_MB(r+1, 128); } /* Set DCC mode to no operation and do magic 0xf0 thing. */ - MCHBAR32(DCC_MCHBAR) = - (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; + + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + /* Normally, we would set this after successful raminit. */ MCHBAR32(DCC_MCHBAR) |= (1 << 19); diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3d48ca2..c771ea2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -31,8 +31,8 @@ static u32 get_cdclk(struct device *const dev) { - const u16 cdclk_sel = - pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: case VCO_4000: diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 24633cf..102af1c 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -19,9 +19,6 @@ const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0); - u16 reg16; - u32 reg32; - printk(BIOS_DEBUG, "Enabling IGD.\n"); /* HSync/VSync */ @@ -35,15 +32,10 @@ }; const int f0_12 = (pci_read_config16(igd_dev, 0xf0) >> 12) & 1; const int vco = raminit_read_vco_index(); - reg16 = pci_read_config16(igd_dev, 0xcc); - reg16 &= 0xfc00; - reg16 |= display_clock_from_f0_and_vco[f0_12][vco]; - pci_write_config16(igd_dev, 0xcc, reg16); - reg16 = pci_read_config16(mch_dev, D0F0_GGC); - reg16 &= 0xf00f; - reg16 |= sysinfo->ggc; - pci_write_config16(mch_dev, D0F0_GGC, reg16); + pci_update_config16(igd_dev, 0xcc, 0xfc00, display_clock_from_f0_and_vco[f0_12][vco]); + + pci_update_config16(mch_dev, D0F0_GGC, 0xf00f, sysinfo->ggc); if ((sysinfo->gfx_type != GMCH_GL40) && (sysinfo->gfx_type != GMCH_GS40) && @@ -54,21 +46,13 @@ pci_write_config32(mch_dev, D0F0_DEVEN, deven | 2); /* Some IGD related settings on D1:F0. */ - reg16 = pci_read_config16(peg_dev, 0xa08); - reg16 &= ~(1 << 15); - pci_write_config16(peg_dev, 0xa08, reg16); + pci_and_config16(peg_dev, 0xa08, (u16)~(1 << 15)); - reg16 = pci_read_config16(peg_dev, 0xa84); - reg16 |= (1 << 8); - pci_write_config16(peg_dev, 0xa84, reg16); + pci_or_config16(peg_dev, 0xa84, 1 << 8); - reg16 = pci_read_config16(peg_dev, 0xb00); - reg16 |= (3 << 8) | (7 << 3); - pci_write_config16(peg_dev, 0xb00, reg16); + pci_or_config16(peg_dev, 0xb00, (3 << 8) | (7 << 3)); - reg32 = pci_read_config32(peg_dev, 0xb14); - reg32 &= ~(1 << 17); - pci_write_config32(peg_dev, 0xb14, reg32); + pci_and_config32(peg_dev, 0xb14, ~(1 << 17)); if (!(deven & 2) || no_peg) { /* Disable PEG finally. */ @@ -76,16 +60,14 @@ "PEG in favor of IGD.\n"); MCHBAR8(0xc14) |= (1 << 5) | (1 << 0); - reg32 = pci_read_config32(peg_dev, 0x200); - reg32 |= (1 << 18); - pci_write_config32(peg_dev, 0x200, reg32); - reg16 = pci_read_config16(peg_dev, 0x224); - reg16 |= (1 << 8); - pci_write_config16(peg_dev, 0x224, reg16); - reg32 = pci_read_config32(peg_dev, 0x200); - reg32 &= ~(1 << 18); - pci_write_config32(peg_dev, 0x200, reg32); - while (pci_read_config32(peg_dev, 0x214) & 0x000f0000); + pci_or_config32(peg_dev, 0x200, 1 << 18); + + pci_or_config16(peg_dev, 0x224, 1 << 8); + + pci_and_config32(peg_dev, 0x200, ~(1 << 18)); + + while (pci_read_config32(peg_dev, 0x214) & (0xf << 16)) + ; pci_write_config32(mch_dev, D0F0_DEVEN, deven & ~2); MCHBAR8(0xc14) &= ~((1 << 5) | (1 << 0)); @@ -99,12 +81,9 @@ printk(BIOS_DEBUG, "Disabling IGD.\n"); - u16 reg16; + /* Disable Graphics Stolen Memory. */ + pci_update_config16(mch_dev, D0F0_GGC, 0xff0f, 0x0002); - reg16 = pci_read_config16(mch_dev, D0F0_GGC); - reg16 &= 0xff0f; /* Disable Graphics Stolen Memory. */ - reg16 |= 0x0002; /* Disable IGD. */ - pci_write_config16(mch_dev, D0F0_GGC, reg16); MCHBAR8(0xf10) |= (1 << 0); if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) { @@ -114,9 +93,7 @@ } /* Hide IGD. */ - u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN); - deven &= ~(3 << 3); - pci_write_config32(mch_dev, D0F0_DEVEN, deven); + pci_and_config32(mch_dev, D0F0_DEVEN, ~(3 << 3)); } void init_igd(const sysinfo_t *const sysinfo) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 439127d..09df12d 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -50,11 +50,10 @@ if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; const pci_devfn_t peg = PCI_DEV(0, 1, 0); + /* FIXME: proper test? */ - if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { - int val = pci_read_config32(peg, 0xfc) | (1 << 15); - pci_write_config32(peg, 0xfc, val); - } + if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) + pci_or_config32(peg, 0xfc, 1 << 15); } /* final */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index b3dbe16..0308e21 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -259,12 +259,12 @@ break; } for (; fn >= 0; --fn) { - const struct device *const d = - pcidev_on_root(dev, fn); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + const struct device *const d = pcidev_on_root(dev, fn); + if (!d || d->enabled) + continue; + /* FIXME: Using bitwise ops changes the binary */ pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); + pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); } } diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index e4d11e3..88c3cee 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -92,9 +92,6 @@ const int sdvo_enabled, const int peg_x16) { - u8 tmp8; - u16 tmp16; - u32 tmp; const pci_devfn_t mch = PCI_DEV(0, 0, 0); const pci_devfn_t pciex = PCI_DEV(0, 1, 0); @@ -103,20 +100,17 @@ sdvo_enabled?"enabled":"disabled"); if (peg_enabled) { - tmp8 = pci_read_config8(mch, D0F0_DEVEN) | (1 << 1); - pci_write_config8(mch, D0F0_DEVEN, tmp8); + pci_or_config8(mch, D0F0_DEVEN, 1 << 1); - tmp8 = pci_read_config8(pciex, 0x224) & ~31; - pci_write_config8(pciex, 0x224, tmp8 | (peg_x16?16:0) | 1); + pci_write_config8(pciex, 0x224, + (pci_read_config8(pciex, 0x224) & ~31) | (peg_x16 ? 16 : 0) | 1); - tmp16 = pci_read_config16(pciex, 0x224) & ~(1 << 8); - pci_write_config16(pciex, 0x224, tmp16); + pci_and_config16(pciex, 0x224, ~(1 << 8)); /* FIXME: fill in: slot or fixed? -> devicetree */ int peg_is_slot = 0; if (peg_is_slot) { - tmp16 = pci_read_config16(pciex, PEG_CAP) | (1 << 8); - pci_write_config16(pciex, PEG_CAP, tmp16); + pci_or_config16(pciex, PEG_CAP, 1 << 8); } /* FIXME: fill in: slot number, slot power -> devicetree */ @@ -125,20 +119,16 @@ /* peg_power := val * 10^-exp */ int peg_power_val = 75; int peg_power_exp = 0; /* 0..3 */ - tmp = (peg_slot << 17) | (peg_power_exp << 15) | - (peg_power_val << 7); + const u32 tmp = (peg_slot << 17) | (peg_power_exp << 15) | (peg_power_val << 7); pci_write_config32(pciex, SLOTCAP, tmp); /* GPEs */ - tmp8 = pci_read_config8(pciex, PEGLC) | 7; - pci_write_config8(pciex, PEGLC, tmp8); + pci_or_config8(pciex, PEGLC, 7); /* VC0: TC0 only, VC0 only */ - tmp8 = pci_read_config8(pciex, D1F0_VC0RCTL); - pci_write_config8(pciex, D1F0_VC0RCTL, tmp8 & 1); + pci_and_config8(pciex, D1F0_VC0RCTL, 1); - tmp8 = pci_read_config8(pciex, D1F0_VCCAP); - pci_write_config8(pciex, D1F0_VCCAP, tmp8 & ~7); + pci_and_config8(pciex, D1F0_VCCAP, ~7); } } @@ -149,37 +139,26 @@ /* Prerequisites for ASPM: */ if (peg_enabled) { - tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13); - pci_write_config32(pciex, 0x200, tmp32); + pci_or_config32(pciex, 0x200, 3 << 13); - tmp32 = pci_read_config32(pciex, 0x0f0); - tmp32 &= ~((1 << 27) | (1 << 26)); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_and_config32(pciex, 0x0f0, ~((1 << 27) | (1 << 26))); - tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_or_config32(pciex, 0x0f0, 3 << 24); - tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4); - pci_write_config32(pciex, 0x0f4, tmp32); + pci_and_config32(pciex, 0x0f4, ~(1 << 4)); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 0); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 1); - tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_or_config32(pciex, 0x0fc, 1 << 4); - tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5); - pci_write_config32(pciex, 0x0fc, tmp32); + pci_and_config32(pciex, 0x0fc, ~(7 << 5)); /* Set L0s, L1 supported in LCTL? */ - tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0); - pci_write_config32(pciex, 0x0b0, tmp32); + pci_or_config32(pciex, 0x0b0, 3 << 0); - tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24); - pci_write_config32(pciex, 0x0f0, tmp32); + pci_or_config32(pciex, 0x0f0, 3 << 24); tmp32 = pci_read_config32(pciex, 0x0f0); if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1)) @@ -217,38 +196,25 @@ DMIBAR32(0x0e2c) = 0x88d07333; } if (peg_enabled) { - tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15); - pci_write_config32(pciex, 0xa08, tmp32); + pci_and_config32(pciex, 0xa08, ~(1 << 15)); - tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_or_config32(pciex, 0xa84, 1 << 8); - tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17); - pci_write_config32(pciex, 0xb14, tmp32); + pci_and_config32(pciex, 0xb14, ~(1 << 17)); - tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8); - pci_write_config32(pciex, 0xb00, tmp32); + pci_or_config32(pciex, 0xb00, 3 << 8); - tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3); - pci_write_config32(pciex, 0xb00, tmp32); + pci_or_config32(pciex, 0xb00, 7 << 3); - tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_and_config32(pciex, 0xa84, ~(1 << 8)); - tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8); - pci_write_config32(pciex, 0xa84, tmp32); + pci_or_config32(pciex, 0xa84, 1 << 8); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23); - pci_write_config32(pciex, 0xb04, tmp32); + pci_update_config32(pciex, 0xb04, ~(0x1f << 23), 0x0e << 23); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 |= (1 << 31); - pci_write_config32(pciex, 0xb04, tmp32); + pci_or_config32(pciex, 0xb04, 1 << 31); - tmp32 = pci_read_config32(pciex, 0xb04); - tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29); - pci_write_config32(pciex, 0xb04, tmp32); + pci_update_config32(pciex, 0xb04, ~(0x03 << 29), 0x01 << 29); } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index fbf9f01..76f70bc 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -807,8 +807,7 @@ pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); /* Clear update bit. */ - pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, - pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE); + pci_and_config16(GCFGC_PCIDEV, GCFGC_OFFSET, ~GCFGC_UPDATE); /* Set display clock select bit. */ pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, @@ -1228,10 +1227,7 @@ } /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, which requires to have TSEG_BASE aligned to TSEG_SIZE. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); - reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ - pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); + pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0)); uma_sizem += 2; } @@ -1559,10 +1555,9 @@ MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); udelay(2); /* 5 6 7 8 9 10 11 12 */ @@ -1700,7 +1695,6 @@ const timings_t *const timings = &sysinfo->selected_timings; int ch; - u8 reg8; timestamp_add_now(TS_BEFORE_INITRAM); @@ -1772,10 +1766,10 @@ /* Announce normal operation, initialization completed. */ MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + + pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); + + pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); /* Take a breath (the reader). */ @@ -1810,8 +1804,7 @@ dram_optimizations(timings, dimms); /* Mark raminit being finished. :-) */ - u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); raminit_thermal(sysinfo); init_igd(sysinfo); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index f7998c9..22ce9a0 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -79,9 +79,8 @@ mb_post_raminit_setup(); - const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ - pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); + pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000); init_pm(&sysinfo, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/42189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Gerrit-Change-Number: 42189 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: Avoid ROM area
by Keith Hui (Code Review) 04 Aug '20

04 Aug '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41091 ) Change subject: nb/intel/i440bx: Avoid ROM area ...................................................................... nb/intel/i440bx: Avoid ROM area Declare the ROM area to be read only in ACPI, and excludes it from ranges available for MMIO. Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/acpi/i440bx.asl M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 2 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41091/1 diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl index e1e4e61..70c3aaa 100644 --- a/src/northbridge/intel/i440bx/acpi/i440bx.asl +++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl @@ -26,10 +26,26 @@ 0x00100000, // Address Base 0x00000000, // Address Length _Y00) + /* Reserved for firmware flash */ + Memory32Fixed (ReadOnly, + 0x100000000 - CONFIG_ROM_SIZE, // Address Base + CONFIG_ROM_SIZE, // Address Length + _Y01) }) CreateDWordField (BUF1, _Y00._LEN, EMLN) // _LEN: Length + CreateDWordField (BUF1, _Y01._BAS, FLSB) // _BAS: Base + /* + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + + /* Top of 4GB */ + ShiftLeft(0x10000000, 4, Local0) + FLSB = Local0 - CONFIG_ROM_SIZE; EMLN = \_SB.PCI0.NB.TOM1 - 0x100000; - Return (BUF1) + Return (BUF1) /* \_SB_.MEM1._CRS.BUF1 */ } } diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index e40b1fc..fa5948f 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -61,6 +61,7 @@ */ MM1B = \_SB.PCI0.NB.TOM1 ShiftLeft(0x10000000, 4, Local0) + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B Return(TMP) -- To view, visit https://review.coreboot.org/c/coreboot/+/41091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Gerrit-Change-Number: 41091 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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