coreboot-gerrit June 2020

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Change in coreboot[master]: soc/intel/gpio: set default value for RXEVCFG in native mode
by Maxim Polyakov (Code Review) 14 Aug '20

14 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41030 ) Change subject: soc/intel/gpio: set default value for RXEVCFG in native mode ...................................................................... soc/intel/gpio: set default value for RXEVCFG in native mode According to the documentation (Intel document #549921), RX Level/Edge Configuration (RXEVCFG) settings are not applicable in the native mode and BIOS does not need to configure them. Therefore, there is no need to change the default value for this field in the PAD_CFG_DW0 register. Set the RX Level/Edge to disable (2h = Drive '0') for all PAD_CFG_NF* macros. Change-Id: Ia667ae4bac4198fe269091050bf067c0a488289a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/41030/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 6eaaf0c..4bb318b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -190,9 +190,10 @@ #endif /* Native function configuration */ -#define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* * Set native function with RX Level/Edge configuration and disable @@ -207,31 +208,36 @@ /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS */ -#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ - PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) #endif /* Native function configuration for standby state */ -#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) /* Native function configuration for standby state, also configuring iostandby as masked */ -#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) /* Native function configuration for standby state, also configuring iosstate and iosterm */ -#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* Configure native function, iosstate, iosterm and disable input/output buffer */ #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia667ae4bac4198fe269091050bf067c0a488289a Gerrit-Change-Number: 41030 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: {soc,drivers}: Enable ISH 'firmware-name' device property on TGL via ...
by Jes Klinke (Code Review) 13 Aug '20

13 Aug '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39475 to review the following change. Change subject: {soc,drivers}: Enable ISH 'firmware-name' device property on TGL via ACPI _DSD table ...................................................................... {soc,drivers}: Enable ISH 'firmware-name' device property on TGL via ACPI _DSD table Upstream of non-mainboard parts of commit c88f7d29565a5f24603bc6cf235d8f3d7d1caf12. Change-Id: I082c5bdd83a9d9e1a23dbc38b74e5f9752c98c99 Signed-off-by: Hu, Hebo <hebo.hu(a)intel.com> --- M src/drivers/intel/ish/Kconfig M src/drivers/intel/ish/ish.c M src/include/device/pci_ids.h A src/soc/intel/tigerlake/acpi/ish.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 5 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39475/1 diff --git a/src/drivers/intel/ish/Kconfig b/src/drivers/intel/ish/Kconfig index 635864e..a2828d1 100644 --- a/src/drivers/intel/ish/Kconfig +++ b/src/drivers/intel/ish/Kconfig @@ -1,5 +1,6 @@ config DRIVERS_INTEL_ISH bool + default n help When enabled, chip driver/intel/ish will publish information to the SSDT _DSD table for the ISH device. diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index e9d5ae96..d542bd3 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -65,6 +65,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_ISHB, PCI_DEVICE_ID_INTEL_CML_ISHB, + PCI_DEVICE_ID_INTEL_TGL_ISHB, 0 }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ccbfe40..3da326b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2105,6 +2105,7 @@ #define PCI_DEVICE_ID_INTEL_82439TX 0x7100 #define PCI_DEVICE_ID_INTEL_CNL_ISHB 0x9dfc #define PCI_DEVICE_ID_INTEL_CML_ISHB 0x02fc +#define PCI_DEVICE_ID_INTEL_TGL_ISHB 0xa0fc /* Intel 82371FB (PIIX) */ #define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl new file mode 100644 index 0000000..186a147 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/ish.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Integrated Sensor Hub Controller 0:12.0 */ + +Device (ISHB) +{ + Name (_ADR, 0x00120000) + Name (_DDN, "Integrated Sensor Hub Controller") +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07..8e17abb 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -46,6 +46,9 @@ /* SMBus 0:1f.4 */ #include "smbus.asl" +/* ISH 0:12.0 */ +#include "ish.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/39475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I082c5bdd83a9d9e1a23dbc38b74e5f9752c98c99 Gerrit-Change-Number: 39475 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb: Enable ISH 'firmware-name' device property on TGL via ACPI _DSD t...
by Jes Klinke (Code Review) 13 Aug '20

13 Aug '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39482 to review the following change. Change subject: mb: Enable ISH 'firmware-name' device property on TGL via ACPI _DSD table ...................................................................... mb: Enable ISH 'firmware-name' device property on TGL via ACPI _DSD table Upstream of mainboard parts of commit c88f7d29565a5f24603bc6cf235d8f3d7d1caf12. Change-Id: Ibc3d4c4ca5ea12d89cef8a4e37ecd4c3c2eb2e2d Signed-off-by: Hu, Hebo <hebo.hu(a)intel.com> --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/39482/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 2051a05..d60918f 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -14,6 +14,7 @@ select GENERATE_SMBIOS_TABLES select SOC_INTEL_TIGERLAKE select INTEL_LPSS_UART_FOR_CONSOLE + select DRIVERS_INTEL_ISH config CHROMEOS bool diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb..ea2b264 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -133,6 +133,14 @@ device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 + + device pci 12.0 off # SensorHUB 0xA0FC + chip drivers/intel/ish + register "firmware_name" = ""tglrvp_ish.bin"" + device generic 0 on end + end + end + device pci 12.0 off end # SensorHUB 0xA0FC device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 643db36..b3558ca 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -129,7 +129,15 @@ device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 - device pci 12.0 off end # SensorHUB 0xA0FC + + device pci 12.0 off # SensorHUB 0xA0FC + chip drivers/intel/ish + register "firmware_name" = ""tglrvp_ish.bin"" + device generic 0 on end + end + end + + device pci 12.6 off end # GSPI2 0x34FB device pci 13.0 off end # GSPI3 0xA0FD device pci 14.0 on end # USB3.1 xHCI 0xA0ED -- To view, visit https://review.coreboot.org/c/coreboot/+/39482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc3d4c4ca5ea12d89cef8a4e37ecd4c3c2eb2e2d Gerrit-Change-Number: 39482 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [WIP]mb/intel/tglrvp: Set gpio GPP_H1
by Shaunak Saha (Code Review) 13 Aug '20

13 Aug '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41811 ) Change subject: [WIP]mb/intel/tglrvp: Set gpio GPP_H1 ...................................................................... [WIP]mb/intel/tglrvp: Set gpio GPP_H1 BUG=none BRANCH=none TEST=Build and boot tglrvp successfully. Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/41811/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 4457506..6a33dcf 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,6 +54,8 @@ /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + + PAD_CFG_GPO(GPP_H1, 1, DEEP), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516 Gerrit-Change-Number: 41811 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options
by Mike Banon (Code Review) 13 Aug '20

13 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40532 ) Change subject: mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options ...................................................................... mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options Fix the memory interleaving options in accordance with buildOpts.c of the other AMD boards like Lenovo G505S and ASUS A88XM-E. Example: if BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING is defined as FALSE then BLDOPT_REMOVE_NODE_INTERLEAVE should be defined as TRUE. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ib66e86d894c70e710ec67943c9d59c22108a7f2b --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40532/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 71fedaa..48a9fe9 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -61,7 +61,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE @@ -108,9 +108,9 @@ #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #define BLDCFG_ONLINE_SPARE FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/40532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66e86d894c70e710ec67943c9d59c22108a7f2b Gerrit-Change-Number: 40532 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Factor out IOBP API
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41946 ) Change subject: sb/intel/lynxpoint: Factor out IOBP API ...................................................................... sb/intel/lynxpoint: Factor out IOBP API Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Makefile.inc A src/southbridge/intel/lynxpoint/iobp.c A src/southbridge/intel/lynxpoint/iobp.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 11 files changed, 131 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/41946/1 diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fa0ef0b..b887586 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c ramstage-y += pch.c +ramstage-y += iobp.c ramstage-y += azalia.c ramstage-y += lpc.c ramstage-y += pcie.c diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c new file mode 100644 index 0000000..3df6940 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include "pch.h" +#include "iobp.h" + +#define IOBP_RETRY 1000 + +static inline int iobp_poll(void) +{ + unsigned int try; + + for (try = IOBP_RETRY; try > 0; try--) { + u16 status = RCBA16(IOBPS); + if ((status & IOBPS_READY) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); + return 0; +} + +u32 pch_iobp_read(u32 address) +{ + u16 status; + + if (!iobp_poll()) + return 0; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_READ; + RCBA16(IOBPS) = status; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return 0; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); + return 0; + } + + /* Read IOBP data */ + return RCBA32(IOBPD); +} + +void pch_iobp_write(u32 address, u32 data) +{ + u16 status; + + if (!iobp_poll()) + return; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* WRITE OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_WRITE; + RCBA16(IOBPS) = status; + + RCBA32(IOBPD) = data; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); + return; + } + + printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} diff --git a/src/southbridge/intel/lynxpoint/iobp.h b/src/southbridge/intel/lynxpoint/iobp.h new file mode 100644 index 0000000..c8669ba --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H + +#include <stdint.h> + +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 02ea34c..53bcc25 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -15,6 +15,7 @@ #include <cbmem.h> #include <string.h> #include "chip.h" +#include "iobp.h" #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 9564b76..d04eec7 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ @@ -175,110 +176,6 @@ } } -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try; - - for (try = IOBP_RETRY; try > 0; try--) { - u16 status = RCBA16(IOBPS); - if ((status & IOBPS_READY) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); - return 0; -} - -u32 pch_iobp_read(u32 address) -{ - u16 status; - - if (!iobp_poll()) - return 0; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_READ; - RCBA16(IOBPS) = status; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return 0; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); - return 0; - } - - /* Read IOBP data */ - return RCBA32(IOBPD); -} - -void pch_iobp_write(u32 address, u32 data) -{ - u16 status; - - if (!iobp_poll()) - return; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* WRITE OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_WRITE; - RCBA16(IOBPS) = status; - - RCBA32(IOBPD) = data; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - return; - } - - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data = pch_iobp_read(address); - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - pch_iobp_write(address, data); -} - void pch_enable(struct device *dev) { u16 reg16; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6e2bd24..674f20f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -153,9 +153,6 @@ void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 79b9517..0d0b7a6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -9,6 +9,7 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "iobp.h" #include "pch.h" #include <southbridge/intel/common/gpio.h> #include <stddef.h> diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 9515473..4ad41fe 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <delay.h> #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index a75cea0..78ac253 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -8,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "chip.h" +#include "iobp.h" #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 74ef021..8bb7532 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -8,6 +8,7 @@ #include <device/pci_ehci.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 5ab5a2c..fe72ebf 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -8,6 +8,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/41946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be Gerrit-Change-Number: 41946 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: (test) -Werror=unused-variable
by HAOUAS Elyes (Code Review) 11 Aug '20

11 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40614 ) Change subject: (test) -Werror=unused-variable ...................................................................... (test) -Werror=unused-variable Change-Id: I3ee9b577fbd9ba2443fbbd22380e0b3fd368b633 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/40614/1 diff --git a/Makefile.inc b/Makefile.inc index e315732..0ce6c4d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -421,7 +421,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla -CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else +CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else -unused-variable CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/40614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ee9b577fbd9ba2443fbbd22380e0b3fd368b633 Gerrit-Change-Number: 40614 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 15

Change in coreboot[master]: Makefile.inc: Remove '-Wstrict-aliasing'
by HAOUAS Elyes (Code Review) 11 Aug '20

11 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41764 ) Change subject: Makefile.inc: Remove '-Wstrict-aliasing' ...................................................................... Makefile.inc: Remove '-Wstrict-aliasing' '-Wstrict-aliasing' warning flag is already turned on with '-Wall'. Change-Id: I8212cfa5d67fba854ee84dd9d560cd7f8a27632e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41764/1 diff --git a/Makefile.inc b/Makefile.inc index 210e9cf..c401b54 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -407,7 +407,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -- To view, visit https://review.coreboot.org/c/coreboot/+/41764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8212cfa5d67fba854ee84dd9d560cd7f8a27632e Gerrit-Change-Number: 41764 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: src: Write FADT minor version at 'acpi_create_fadt()'
by HAOUAS Elyes (Code Review) 11 Aug '20

11 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42249 ) Change subject: src: Write FADT minor version at 'acpi_create_fadt()' ...................................................................... src: Write FADT minor version at 'acpi_create_fadt()' Change-Id: I5eb12e298bc050c629c3184eb6bb8b6f046fee2b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c 6 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42249/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 47f03c8..a4ea24b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1239,6 +1239,8 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; + fadt->FADT_MinorVersion = 0; + fadt->firmware_ctrl = (unsigned long) facs; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index fe5879c..18626ff 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -149,7 +149,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..2898704 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -121,7 +121,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 719eb54..9fd3141 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -87,7 +87,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index ba277f9..2ecac2e 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -110,7 +110,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8ed0330..b61ec20 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -87,7 +87,6 @@ fadt->reset_value = 6; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb12e298bc050c629c3184eb6bb8b6f046fee2b Gerrit-Change-Number: 42249 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: acpi: Bump FADT Minor Version to 3
by HAOUAS Elyes (Code Review) 11 Aug '20

11 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42250 ) Change subject: acpi: Bump FADT Minor Version to 3 ...................................................................... acpi: Bump FADT Minor Version to 3 Change-Id: I3c7803bcab3a4054280e352fd154cc28bf62f723 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42250/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a4ea24b..15794f1 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1239,7 +1239,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; - fadt->FADT_MinorVersion = 0; + fadt->FADT_MinorVersion = 3; fadt->firmware_ctrl = (unsigned long) facs; fadt->x_firmware_ctl_l = (unsigned long)facs; -- To view, visit https://review.coreboot.org/c/coreboot/+/42250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c7803bcab3a4054280e352fd154cc28bf62f723 Gerrit-Change-Number: 42250 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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