coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: mb/hp: select TPM and TPM1 for all EliteBook laptops
by Iru Cai (vimacs) (Code Review) 17 Aug '20

17 Aug '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41169 to review the following change. Change subject: mb/hp: select TPM and TPM1 for all EliteBook laptops ...................................................................... mb/hp: select TPM and TPM1 for all EliteBook laptops All the EliteBook laptops currently supported by coreboot and on review all support TPM 1.2 according the maintenance and service guide manuals of these laptops. TODO: add the TPM entry in the device tree or override tree Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name 2 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/41169/1 diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 8955ba6..8a6a090 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -23,6 +23,8 @@ select SERIRQ_CONTINUOUS_MODE select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 if BOARD_HP_SNB_IVB_LAPTOPS diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index cf57634..5241099 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -54,8 +54,6 @@ select GFX_GMA_PANEL_1_ON_LVDS select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_LPC47N217 @@ -90,7 +88,6 @@ select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_C216 @@ -105,6 +102,4 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 select SOUTHBRIDGE_INTEL_C216 -- To view, visit https://review.coreboot.org/c/coreboot/+/41169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256 Gerrit-Change-Number: 41169 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mainboard: Add HP EliteBook 2560p
by Iru Cai (vimacs) (Code Review) 17 Aug '20

17 Aug '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41159 to review the following change. Change subject: mainboard: Add HP EliteBook 2560p ...................................................................... mainboard: Add HP EliteBook 2560p Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/2560p.md A Documentation/mainboard/hp/2560p_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads A src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb 11 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41159/1 diff --git a/Documentation/mainboard/hp/2560p.md b/Documentation/mainboard/hp/2560p.md new file mode 100644 index 0000000..e8140e3 --- /dev/null +++ b/Documentation/mainboard/hp/2560p.md @@ -0,0 +1,100 @@ +# HP EliteBook 2560p + +This page is about the notebook [HP EliteBook 2560p]. + +## Release status + +HP EliteBook 2560p was released in 2011 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: +1. EC firmware +2. Intel ME firmware + +EC firmware can be retrieved from the HP firmware update image, or the firmware +backup of the laptop. EC Firmware is part of the coreboot build process. +The guide on extracting EC firmware and using it to build coreboot is in +document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops). + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +## Programming + +The flash chip is located between the memory slots and the PCH, +covered by the base enclosure, which needs to be removed according to +the [Maintenance and Service Guide] to access the flash chip. An SPI +flash programmer using 3.3V voltage such as a ch341a programmer, and +an SOIC-8 clip can be used to read and flash the chip in-circuit. + +Pin 1 of the flash chip is at the side near the PCH. + +![Flash Chip in 2560p](2560p_flash.webp) + +For more details have a look at the general [flashing tutorial]. + + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the back +bottom USB port. + +Schematic of this laptop can be found on [Lab One]. + +## Test status + +### Known issues + +- GRUB payload freezes if at_keyboard module is in the GRUB image + ([bug #141]) + +### Untested + +- Optical Drive +- VGA +- SmartCard +- Fingerprint Reader +- Dock +- Modem +- TPM + +### Working + +- integrated graphics init with libgfxinit +- SATA +- audio: speaker and microphone +- Ethernet +- WLAN +- WWAN +- bluetooth +- ExpressCard +- SD Card Reader +- eSATA +- USB +- DisplayPort +- keyboard, touchpad and trackpoint +- EC ACPI support and thermal control +- internal flashing when IFD is unlocked +- using `me_cleaner` + + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Sandy/Ivy Bridge (FCPGA988) | ++------------------+--------------------------------------------------+ +| PCH | Intel Cougar Point QM67 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 2560p]: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03011618 +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Lab One]: https://www.laboneinside.com/hp-elitebook-2560p-schematic-diagram/ +[bug #141]: https://ticket.coreboot.org/issues/141 diff --git a/Documentation/mainboard/hp/2560p_flash.webp b/Documentation/mainboard/hp/2560p_flash.webp new file mode 100644 index 0000000..8583fa0 --- /dev/null +++ b/Documentation/mainboard/hp/2560p_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e80ff0b..cb31711 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -59,6 +59,7 @@ ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) ## Intel diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 52297fe..8955ba6 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -32,6 +32,7 @@ config VARIANT_DIR string + default "2560p" if BOARD_HP_2560P default "2570p" if BOARD_HP_2570P default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P @@ -42,6 +43,7 @@ config MAINBOARD_PART_NUMBER string + default "EliteBook 2560p" if BOARD_HP_2560P default "EliteBook 2570p" if BOARD_HP_2570P default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P @@ -70,6 +72,7 @@ config USBDEBUG_HCD_INDEX int + default 1 if BOARD_HP_2560P default 2 if BOARD_HP_2570P default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index f013dfc..addb25d 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -12,6 +12,17 @@ ## GNU General Public License for more details. ## +config BOARD_HP_2560P + bool "EliteBook 2560p" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_PANEL_1_ON_LVDS + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_HP_2570P bool "EliteBook 2570p" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt new file mode 100644 index 0000000..a3e8a7b --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-2560p-notebook-pc/5071201 +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c new file mode 100644 index 0000000..3256090 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/early_init.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/hp/kbc1126/ec.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* back bottom USB port, USB debug */ + { 1, 1, 0 }, /* back upper USB port */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* webcam */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 1, 0, 3 }, + { 1, 0, 3 }, /* smartcard */ + { 1, 1, 4 }, /* fingerprint reader */ + { 1, 1, 4 }, /* WWAN */ + { 0, 0, 5 }, + { 1, 0, 5 }, /* docking */ + { 0, 0, 6 }, + { 0, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); + kbc1126_disable4e(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads new file mode 100644 index 0000000..a7dd834 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP3, + HDMI1, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c new file mode 100644 index 0000000..5939f8b --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/gpio.c @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c new file mode 100644 index 0000000..fab19ab --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/hda_verb.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c162b, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c162b), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + + 0x11c11040, /* Codec Vendor / Device ID: LSI */ + 0x103c3066, /* Subsystem ID */ + 1, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(1, 0x103c3066), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb new file mode 100644 index 0000000..d7d63b1 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000155" + register "gpu_pch_backlight" = "0x02880288" + + device domain 0x0 on + subsystemid 0x103c 0x162b inherit + + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # mailbox at 0x200/0x201 and PM1 at 0x220 + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x33" + + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC Host Controller + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/41159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73 Gerrit-Change-Number: 41159 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: lib/imd_cbmem.c: Add a helper function to indicate that cbmem is ready
by Arthur Heymans (Code Review) 17 Aug '20

17 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38736 ) Change subject: lib/imd_cbmem.c: Add a helper function to indicate that cbmem is ready ...................................................................... lib/imd_cbmem.c: Add a helper function to indicate that cbmem is ready This can be used in romstage in particular to know if dram is ready. Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cbmem.h M src/lib/imd_cbmem.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38736/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index cf79f41..a68d65f 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -81,6 +81,9 @@ */ void *cbmem_top_chipset(void); +/* Returns 1 if cbmem is initialized, 0 otherwise */ +int cbmem_ready(void); + /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 5be7dc4..864d73e 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -44,6 +44,22 @@ dead_code(); } +static int cbmem_initialized; + +static void set_cbmem_ready(int unused) +{ + cbmem_initialized = 1; +} + +ROMSTAGE_CBMEM_INIT_HOOK(set_cbmem_ready); +POSTCAR_CBMEM_INIT_HOOK(set_cbmem_ready); +RAMSTAGE_CBMEM_INIT_HOOK(set_cbmem_ready); + +int cbmem_ready(void) +{ + return cbmem_initialized; +} + static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e; -- To view, visit https://review.coreboot.org/c/coreboot/+/38736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf Gerrit-Change-Number: 38736 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram
by Arthur Heymans (Code Review) 17 Aug '20

17 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37212 ) Change subject: arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram ...................................................................... arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37212/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 8c28784..ceb0321 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -38,7 +38,14 @@ movl 4(%esp), %eax movl %eax, _cbmem_top_ptr #endif + /* Make sure _cbmem_top_ptr hits dram before invd */ + movl $1, %eax + cpuid + btl $19, %edx + jz skip_clflush + clflush _cbmem_top_ptr +skip_clflush: /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car -- To view, visit https://review.coreboot.org/c/coreboot/+/37212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Gerrit-Change-Number: 37212 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: WIP: inteltool: Add option to output GPIOs as coreboot macros
by Matt DeVillier (Code Review) 16 Aug '20

16 Aug '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39394 ) Change subject: WIP: inteltool: Add option to output GPIOs as coreboot macros ...................................................................... WIP: inteltool: Add option to output GPIOs as coreboot macros based on Nico's work in CB:25145, but updated to use current macros found in gpio_defs.h in soc/intel/common. Avoids use of "legacy" macros which are only applicable to Skylake/Kabylake. Test: Generate reasonably sane list of macros for out-of-tree Whiskeylake-based device. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ide0f0f529d62b312a719e78b0e2f747f41067a36 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 4 files changed, 212 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/39394/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index e4e3570..05b5181 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1072,7 +1072,7 @@ case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: - print_gpio_groups(sb); + print_gpio_groups(sb, false); return 0; case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 5457109..d034860 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -49,13 +49,185 @@ return "RESERVED"; } +static const char *decode_table_gpio_term(const size_t term) +{ + switch (term) { + case 0: return "NONE"; + case 2: return "DN_5K"; + case 4: return "DN_20K"; + case 9: return "UP_1K"; + case 10: return "UP_5K"; + case 11: return "UP_2K"; + case 12: return "UP_20K"; + case 13: return "UP_667"; + case 15: return "NATIVE"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_reset(const size_t reset) +{ + switch (reset) { + case 0: return "PWROK"; + case 1: return "DEEP"; + case 2: return "PLTRST"; + case 3: return "RSMRST"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_nf(const size_t pad_mode) +{ + switch (pad_mode) { + case 0: return "GPIO"; + case 1: return "NF1"; + case 2: return "NF2"; + case 3: return "NF3"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_trig(const size_t trig_mode) +{ + switch (trig_mode) { + case 0: return "LEVEL"; + case 1: return "EDGE_SINGLE"; + case 2: return "OFF"; + case 3: return "EDGE_BOTH"; + default: return "UNSUPPORTED"; + } +} + +static int print_table_gpio(const struct gpio_group *const group, + const size_t pad, + const uint32_t dw0, const uint32_t dw1) +{ + const size_t tx_state = dw0 >> 0 & 1; + const size_t tx_disable = dw0 >> 8 & 1; + const size_t rx_disable = dw0 >> 9 & 1; + const size_t pad_mode = dw0 >> 10 & 3; + const size_t int_route = dw0 >> 17 & 0x0f; + const size_t rx_invert = dw0 >> 23 & 1; + const size_t rx_evcfg = dw0 >> 25 & 3; + const size_t rx_raw1 = dw0 >> 28 & 1; + const size_t rx_padsel = dw0 >> 29 & 1; + const size_t pad_reset = dw0 >> 30 & 3; + const size_t term = dw1 >> 10 & 0x0f; + const size_t pad_tol = dw1 >> 25 & 0x01; + const size_t driver = dw1 >> 4 & 1; + + const char *const pad_name = group->pad_names[pad * group->func_count]; + + if (rx_padsel || rx_raw1) + return -1; + + if (pad_mode) { + printf("PAD_CFG_NF%s(%s, %s, %s, %s),\n", + pad_tol ? "_1V8" : "", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_nf(pad_mode)); + } else if (!tx_disable) { + if (!rx_disable) { + fprintf(stderr, "WARNING: %s has both TX and RX enabled" + ", disabling RX!\n", pad_name); + } + if (term) { + printf("PAD_CFG_TERM_GPO(%s, %zu, %s, %s),\n", + pad_name, tx_state, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPO(%s, %zu, %s),\n", + pad_name, tx_state, + decode_table_gpio_reset(pad_reset)); + } + } else if (!rx_disable && tx_disable) { + switch (int_route) { + case 0x0: + if (rx_invert || rx_evcfg > 1) + return -1; + if (driver) { + printf("PAD_CFG_GPI_GPIO_DRIVER(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else if (rx_evcfg & ~0x04) { + printf("PAD_CFG_GPI(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPI_INT(%s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } + break; + case 0x1: + return -1; + case 0x2: + if (rx_evcfg == 1) { + printf("PAD_CFG_GPI_SMI_" + "%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } else { + return -1; + } + break; + case 0x4: + if (rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI_SCI_%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + break; + case 0x8: + if (rx_evcfg > 1) + return -1; + if (rx_evcfg && !rx_invert) { + printf("PAD_CFG_GPI_APIC(%s, %s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg), + rx_invert ? "INVERT" : "NONE"); + } else { + printf("PAD_CFG_GPI_APIC%s%s(%s, %s, %s),\n", + rx_evcfg ? "_EDGE" : "", + rx_invert ? "_LOW" : "_HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } + break; + default: + return -1; + } + } else { + printf("PAD_NC(%s, %s),\n", pad_name, decode_table_gpio_term(term)); + } + return 0; +} + static void print_gpio_group(const uint8_t pid, size_t pad_cfg, const struct gpio_group *const group, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t p; - printf("%s\n", group->display); + if (use_macros) + printf("\n/* %s */\n\n", group->display); + else + printf("%s\n", group->display); for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); @@ -63,21 +235,31 @@ const char *const pad_name = group->pad_names[p * group->func_count]; - printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, - (uint64_t)dw1 << 32 | dw0, - pad_name[0] == '*' ? &pad_name[1] : pad_name, - decode_pad_mode(group, p, dw0)); + if (use_macros) { + printf("/* %-8s %-20s */\t", + group->pad_names[p * group->func_count], + decode_pad_mode(group, p, dw0)); + + if (print_table_gpio(group, p, dw0, dw1)) + printf("PAD_CFG_UNSUPPORTED,\n"); + } else { + printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, + (uint64_t)dw1 << 32 | dw0, + pad_name[0] == '*' ? &pad_name[1] : pad_name, + decode_pad_mode(group, p, dw0)); + } } } static void print_gpio_community(const struct gpio_community *const community, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t group, pad_count; size_t pad_cfg; /* offset in bytes under this communities PCR port */ - printf("%s\n\nPCR Port ID: 0x%06zx\n\n", - community->name, (size_t)community->pcr_port_id << 16); + if (!use_macros) + printf("%s\n\nPCR Port ID: 0x%06zx\n\n", + community->name, (size_t)community->pcr_port_id << 16); for (group = 0, pad_count = 0; group < community->group_count; ++group) pad_count += community->groups[group]->pad_count; @@ -92,7 +274,7 @@ for (group = 0; group < community->group_count; ++group) { print_gpio_group(community->pcr_port_id, pad_cfg, community->groups[group], - pad_stepping); + pad_stepping, use_macros); pad_cfg += community->groups[group]->pad_count * pad_stepping; } } @@ -176,7 +358,7 @@ } } -void print_gpio_groups(struct pci_dev *const sb) +void print_gpio_groups(struct pci_dev *const sb, const bool use_macros) { size_t community_count; const struct gpio_community *const *communities; @@ -192,5 +374,5 @@ printf("\n============= GPIOS =============\n\n"); for (; community_count; --community_count) - print_gpio_community(*communities++, pad_stepping); + print_gpio_community(*communities++, pad_stepping, use_macros); } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 555aa2f..bd0e5e9 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -490,7 +490,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMaAsfSRxC]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -510,6 +510,7 @@ " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" + " -C | --macros: dump GPIOs in coreboot macro format\n" " --pcr=PORT_ID: dump all registers of a PCR port\n" " (may be specified max %d times)\n" "\n", MAX_PCR_PORTS); @@ -570,7 +571,7 @@ int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; - int show_gpio_diffs = 0; + int show_gpio_diffs = 0, use_gpio_macros = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -593,11 +594,12 @@ {"gfx", 0, 0, 'f'}, {"ahci", 0, 0, 'R'}, {"sgx", 0, 0, 'x'}, + {"macros", 0, 0, 'C'}, {"pcr", required_argument, 0, LONG_OPT_PCR}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRCS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -665,6 +667,10 @@ case 'x': dump_sgx = 1; break; + case 'C': + dump_gpios = 1; + use_gpio_macros = 1; + break; case LONG_OPT_PCR: if (pcr_count < MAX_PCR_PORTS) { errno = 0; @@ -795,8 +801,12 @@ /* Now do the deed */ if (dump_gpios) { - print_gpios(sb, 1, show_gpio_diffs); - printf("\n\n"); + if (use_gpio_macros) { + print_gpio_groups(sb, use_gpio_macros); + } else { + print_gpios(sb, 1, show_gpio_diffs); + printf("\n\n"); + } } else if (show_gpio_diffs) { print_gpios(sb, 0, show_gpio_diffs); printf("\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index dc55246..5468c21 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -19,6 +19,7 @@ #include <commonlib/helpers.h> +#include <stdbool.h> #include <stdint.h> #if defined(__GLIBC__) @@ -399,7 +400,7 @@ const struct gpio_community *const *get_gpio_communitys(struct pci_dev *const sb, size_t* community_count, size_t* pad_stepping); -void print_gpio_groups(struct pci_dev *sb); +void print_gpio_groups(struct pci_dev *sb, bool use_macros); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); -- To view, visit https://review.coreboot.org/c/coreboot/+/39394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide0f0f529d62b312a719e78b0e2f747f41067a36 Gerrit-Change-Number: 39394 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: ec/kontron: add option to configure I2C frequency
by Maxim Polyakov (Code Review) 16 Aug '20

16 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39845 ) Change subject: ec/kontron: add option to configure I2C frequency ...................................................................... ec/kontron: add option to configure I2C frequency Allows to change the frequency for the I2C bus by overriding 2c_freq option from the devicetree of the board. For example, if the bus is not beyond the board, then we can increase the frequency in order to read DMI parameters from EEPROM faster. Tested on kontron COMe module with T10-TNI carrierboard [1,2] [1] https://review.coreboot.org/c/coreboot/+/39133 [2] Change-Id: I36a7ae30f1197f77854634fac3a9e1911ce92093 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/ec/kontron/kempld/chip.h M src/ec/kontron/kempld/kempld_i2c.c 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39845/1 diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 597f281..2b18faf 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -32,6 +32,7 @@ struct ec_kontron_kempld_config { struct kempld_uart uart[KEMPLD_NUM_UARTS]; + unsigned short i2c_freq; }; #endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index ab41097..24297f0c9 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -27,6 +27,7 @@ #include <timer.h> #include <delay.h> +#include "chip.h" #include "kempld.h" #include "kempld_internal.h" @@ -54,8 +55,8 @@ #define I2C_CMD_READ_NACK 0x29 #define I2C_CMD_IACK 0x01 -#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ -#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD_DEFAULT 100 /* 100 kHz */ #define EIO 5 #define ENXIO 6 @@ -244,12 +245,17 @@ void kempld_i2c_device_init(struct device *const dev) { + const struct ec_kontron_kempld_config *const config = dev->chip_info; + unsigned short frequency; u16 prescale_corr; long prescale; u8 ctrl; u8 stat; u8 cfg; + if (!config) + return; + if (kempld_get_mutex(100) < 0) return; @@ -258,11 +264,20 @@ ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_write8(KEMPLD_I2C_CTRL, ctrl); + frequency = KEMPLD_I2C_FREQ_STD_DEFAULT; + if (config->i2c_freq) { + if (config->i2c_freq <= KEMPLD_I2C_FREQ_MAX) + frequency = config->i2c_freq + else + printk(BIOS_INFO, "kempld_i2c: %d kHz is an invalid frequency value. " + "Set default value %d kHz\n", config->i2c_freq, frequency); + } + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); if (spec_major == 1) - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + prescale = KEMPLD_CLK / (frequency * 5) - 1000; else - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + prescale = KEMPLD_CLK / (frequency * 4) - 3000; if (prescale < 0) prescale = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7ae30f1197f77854634fac3a9e1911ce92093 Gerrit-Change-Number: 39845 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mb/kontron/mal10: increase I2C bus frequency
by Maxim Polyakov (Code Review) 16 Aug '20

16 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39846 ) Change subject: mb/kontron/mal10: increase I2C bus frequency ...................................................................... mb/kontron/mal10: increase I2C bus frequency In accordance with the changes in kontron-ec [1], we can increase the frequency of the I2C bus to reduce the read time of the EEPROM during initialization of the board. Change-Id: Iaa194b9497fe046744e1e298535e2493ab75b6cd Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39846/1 diff --git a/src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb b/src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb index a2cd3b3..47537ea 100644 --- a/src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/baseboard/devicetree.cb @@ -98,6 +98,8 @@ chip ec/kontron/kempld register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" + register "i2c_freq" = "400" # kHz + device generic 0.0 on end # UART #0 device generic 0.1 on end # UART #1 device generic 1.0 on end # I2C -- To view, visit https://review.coreboot.org/c/coreboot/+/39846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa194b9497fe046744e1e298535e2493ab75b6cd Gerrit-Change-Number: 39846 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: util/mtkheader: Port gen-bl-img.py to python3
by Stefan Reinauer (Code Review) 15 Aug '20

15 Aug '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42320 ) Change subject: util/mtkheader: Port gen-bl-img.py to python3 ...................................................................... util/mtkheader: Port gen-bl-img.py to python3 converted with 2to3 and manually changed shebang to reflect python3. Tested by calling the script on the command line. Change-Id: Ia7b46093f1dcecd03d16fbe5f37d1aae7679bac3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/mtkheader/gen-bl-img.py 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/42320/1 diff --git a/util/mtkheader/gen-bl-img.py b/util/mtkheader/gen-bl-img.py index 282dfbf..e1672fa 100755 --- a/util/mtkheader/gen-bl-img.py +++ b/util/mtkheader/gen-bl-img.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: GPL-2.0-only @@ -77,9 +77,9 @@ def main(argv): if len(argv) != 5: - print 'Usage: %s <chip> <flash_type> <input_file> <output_file>' % argv[0] - print '\t flash_type: emmc|sf' - print '\t chip : mt8173|mt8183' + print('Usage: %s <chip> <flash_type> <input_file> <output_file>' % argv[0]) + print('\t flash_type: emmc|sf') + print('\t chip : mt8173|mt8183') exit(1) write(argv[4], gen_preloader(argv[1], argv[2], read(argv[3]))) -- To view, visit https://review.coreboot.org/c/coreboot/+/42320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b46093f1dcecd03d16fbe5f37d1aae7679bac3 Gerrit-Change-Number: 42320 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: util/cavium: port devicetree_convert.py to python3
by Stefan Reinauer (Code Review) 15 Aug '20

15 Aug '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42330 ) Change subject: util/cavium: port devicetree_convert.py to python3 ...................................................................... util/cavium: port devicetree_convert.py to python3 converted with 2to3 and manually changed shebang to reflect python3. Tested by calling the script on the command line. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Iecc29729d01c0096f8b3fc62acb9f306c8fb2958 --- M util/cavium/devicetree_convert.py 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42330/1 diff --git a/util/cavium/devicetree_convert.py b/util/cavium/devicetree_convert.py index 05f85aa..e4eb33b5 100755 --- a/util/cavium/devicetree_convert.py +++ b/util/cavium/devicetree_convert.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: GPL-3.0-or-later # devicetree_convert Tool to convert a DTB to a static C file @@ -27,15 +27,15 @@ path = path.replace("/", "") if len(node) == 1: for i in node: - if type(i) is not unicode: - print "%s: Type is not string" % path + if not isinstance(i, str): + print("%s: Type is not string" % path) continue if args.verbose: - print "%s = %s" % (path, i) + print("%s = %s" % (path, i)) if outfile is not None: outfile.write("{\"%s\", \"%s\"},\n" % (path, i)) else: - print "%s: Arrays aren't supported" % path + print("%s: Arrays aren't supported" % path) if outfile is not None: outfile.write("{0, 0},\n") -- To view, visit https://review.coreboot.org/c/coreboot/+/42330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecc29729d01c0096f8b3fc62acb9f306c8fb2958 Gerrit-Change-Number: 42330 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency
by Mike Banon (Code Review) 14 Aug '20

14 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40533 ) Change subject: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency ...................................................................... mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency Together with the "AMD_XMP" changes, now this board with Crucial BLT8G3D1869DT1TX0 sticks could run at 1600 MHz CL8 (8-8-9-23) speeds. Earlier only 1333 MHz CL9 (9-9-10-27) has been possible with coreboot. tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I192096a8756a9985395ae8e9c8abf6ca0405c2bb --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/40533/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 48a9fe9..51f46de 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -116,7 +116,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_USE_BURST_MODE FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/40533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I192096a8756a9985395ae8e9c8abf6ca0405c2bb Gerrit-Change-Number: 40533 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 9

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020