Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37825 )
Change subject: aopen/dxplplusu: Add early GPIO settings ......................................................................
aopen/dxplplusu: Add early GPIO settings
Required for 2nd COM port to work.
Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 109 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37825/1
diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index db55f95..eb51335 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -13,13 +13,120 @@ * GNU General Public License for more details. */
+#include <arch/io.h> #include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <southbridge/intel/i82801dx/i82801dx.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) +#define GPIO_DEV PNP_DEV(0x2e, LPC47M10X2_PME) +#define PME_BASE 0xe00 + +/* JP3 + * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 + * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 + */ + +static void enable_gpio(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* These should go under sb/. */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); + + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_enable(GPIO_DEV, 0); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO0, PME_BASE); + pnp_set_enable(GPIO_DEV, 1); + pnp_exit_conf_state(GPIO_DEV); + + pci_write_config16(dev, GEN1_DEC, PME_BASE | 0x01); +} + +static void gpio_write(u8 addr, u8 val) +{ + outb(val, PME_BASE + addr); +} + +static void gpio_read_write(u8 addr, u8 amask, u8 omask) +{ + u8 val = inb(PME_BASE + addr); + val &= amask; + val |= omask; + outb(val, PME_BASE + addr); +} + +static void configure_gpios(void) +{ + /* GP10-17 */ + gpio_write(0x23, 0x00); /* push-pull output */ + gpio_write(0x24, 0x81); /* open-drain but input ? */ + gpio_write(0x25, 0x01); + gpio_write(0x26, 0x01); + gpio_write(0x27, 0x01); + gpio_write(0x28, 0x01); + gpio_write(0x29, 0x01); + gpio_write(0x2a, 0x00); /* push-pull output */ + + /* GP20-27 */ + gpio_write(0x2b, 0x01); + gpio_write(0x2c, 0x0c); /* nDS1 floppy select */ + gpio_write(0x2d, 0x00); /* push-pull output */ + gpio_write(0x2f, 0x01); + gpio_write(0x30, 0x01); + gpio_write(0x31, 0x01); + gpio_write(0x32, 0x04); /* nIO_SMI */ + + /* GP30-37 */ + gpio_write(0x33, 0x04); /* FAN_TACH2 */ + gpio_write(0x34, 0x01); + gpio_write(0x35, 0x01); + gpio_write(0x36, 0x01); + gpio_write(0x37, 0x01); + gpio_write(0x38, 0x01); + gpio_write(0x39, 0x04); /* nKBDRESET */ + gpio_write(0x3a, 0x04); /* A20M */ + + /* GP40-43 */ + gpio_write(0x3b, 0x84); /* DRVDEN0 open-drain */ + gpio_write(0x3c, 0x04); /* DRVDEN1 push/pull */ + gpio_write(0x3d, 0x84); /* nIO_PME open-drain */ + gpio_write(0x3e, 0x01); + + /* GP50-GP57 to UART signals */ + gpio_write(0x3f, 0x05); + gpio_write(0x40, 0x05); + gpio_write(0x41, 0x05); + gpio_write(0x42, 0x04); + gpio_write(0x43, 0x05); + gpio_write(0x44, 0x04); + gpio_write(0x45, 0x05); + gpio_write(0x46, 0x04); + + /* GP60-GP61 */ + gpio_write(0x47, 0x86); /* LED1 invert open-drain*/ + gpio_write(0x48, 0x81); /* open-drain but input */ + + /* Set initial output bits */ + gpio_read_write(0x4b, 0xff, 0x81); /* GP1 */ + gpio_read_write(0x4c, ~0x01, 0x00); /* GP2 */ + gpio_read_write(0x4d, 0xff, 0x80); /* GP3 */ + gpio_read_write(0x4e, ~0x08, 0x00); /* GP4 */ + + /* LED1 off */ + gpio_write(0x5d, 0x00); +}
void bootblock_mainboard_early_init(void) { + enable_gpio(); + configure_gpios(); + /* Get the serial port configured. */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index bc80e87..b3449a1 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -59,7 +59,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d8..7a8fee4 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -92,6 +92,7 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37825 )
Change subject: aopen/dxplplusu: Add early GPIO settings ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/37825/1/src/mainboard/aopen/dxplplu... File src/mainboard/aopen/dxplplusu/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37825/1/src/mainboard/aopen/dxplplu... PS1, Line 28: /* JP3 : * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 : * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 : */ /* * JP3 * … */
Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37825
to look at the new patch set (#2).
Change subject: aopen/dxplplusu: Add early GPIO settings ......................................................................
aopen/dxplplusu: Add early GPIO settings
Required for 2nd COM port to work.
Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 110 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37825/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37825 )
Change subject: aopen/dxplplusu: Add early GPIO settings ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37825/1/src/mainboard/aopen/dxplplu... File src/mainboard/aopen/dxplplusu/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37825/1/src/mainboard/aopen/dxplplu... PS1, Line 28: /* JP3 : * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 : * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 : */
/* […]
Done
Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37825 )
Change subject: aopen/dxplplusu: Add early GPIO settings ......................................................................
Abandoned
-
Kyösti Mälkki (Code Review) -
Paul Menzel (Code Review)