coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/intel/mipi_camera: Add camera power resource to SSDT
by Sugnan Prabhu S (Code Review) 22 Jun '20

22 Jun '20

Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Furquan Shaikh, Wonkyu Kim, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41624 to look at the new patch set (#24). Change subject: drivers/intel/mipi_camera: Add camera power resource to SSDT ...................................................................... drivers/intel/mipi_camera: Add camera power resource to SSDT This change adds support function to parse entries in the devicetree to generate PowerResource entries for the MIPI camera. Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 162 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41624/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 24 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer/var/terrador: Enable CA Mirror
by David Wu (Code Review) 22 Jun '20

22 Jun '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42274 ) Change subject: mb/google/volteer/var/terrador: Enable CA Mirror ...................................................................... mb/google/volteer/var/terrador: Enable CA Mirror BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686 --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42274/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 75422d8..8236890 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -1,4 +1,5 @@ chip soc/intel/tigerlake + register "CmdMirror" = "0x00000033" device domain 0 on end end diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e693699..2c7b604 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -83,6 +83,9 @@ /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; + /* LPDDR4x Command Pins Mirrored */ + uint32_t CmdMirror; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b77bb66 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,9 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + /* LPDDR4x Command Pins Mirrored */ + m_cfg->CmdMirror[0] = config->CmdMirror; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686 Gerrit-Change-Number: 42274 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: soc/intel/tigerlake: Configure CA Mirror
by David Wu (Code Review) 22 Jun '20

22 Jun '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42276 ) Change subject: soc/intel/tigerlake: Configure CA Mirror ...................................................................... soc/intel/tigerlake: Configure CA Mirror BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42276/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e693699..2c7b604 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -83,6 +83,9 @@ /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; + /* LPDDR4x Command Pins Mirrored */ + uint32_t CmdMirror; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index f7956c8..b77bb66 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -196,6 +196,9 @@ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + /* LPDDR4x Command Pins Mirrored */ + m_cfg->CmdMirror[0] = config->CmdMirror; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/42276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Gerrit-Change-Number: 42276 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: mb/emulation/qemu-i440fx,q35: Fix comment style
by Paul Menzel (Code Review) 22 Jun '20

22 Jun '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42615 ) Change subject: mb/emulation/qemu-i440fx,q35: Fix comment style ...................................................................... mb/emulation/qemu-i440fx,q35: Fix comment style The comment fits in 96 characters, so do it, also getting rid of the unwanted multi-line comment style. Add a dot/period to the end of the sentence. Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/mainboard.c 2 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42615/1 diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 04bbb7d..929743a 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -20,9 +20,7 @@ for (i = 0; i < 6; i++) pci_write_config8(dev, 0x5a + i, 0x33); - /* This sneaked in here, because Qemu does not - * emulate a SuperIO chip - */ + /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */ pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing */ diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index c7e983a..d329e5a 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -26,9 +26,7 @@ pci_write_config8(dev, Q35_PAM0 + 5, 0x33); pci_write_config8(dev, Q35_PAM0 + 6, 0x33); - /* This sneaked in here, because Qemu does not - * emulate a SuperIO chip - */ + /* This sneaked in here, because Qemu does not emulate a SuperIO chip. */ pc_keyboard_init(NO_AUX_DEVICE); /* setup IRQ routing for pci slots */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec Gerrit-Change-Number: 42615 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()
by Jonathan Zhang (Code Review) 22 Jun '20

22 Jun '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42439 to review the following change. Change subject: soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count() ...................................................................... soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count() Rename function from xeon_sp_get_cpu_count() to xeon_sp_get_sku_count(). The function returns CPU socket count, by getting it from the field named as numCpus in FSP HOB. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1 --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42439/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 33c85ca..654f761 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -454,7 +454,7 @@ static unsigned long acpi_fill_slit(unsigned long current) { - unsigned int nodes = xeon_sp_get_cpu_count(); + unsigned int nodes = xeon_sp_get_skt_count(); uint8_t *p = (uint8_t *)current; memset(p, 0, 8 + nodes * nodes); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index ee2b68b..1bcd222 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -34,7 +34,8 @@ void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); -unsigned int xeon_sp_get_cpu_count(void); +/* Return socket count, as obtained from FSP HOB */ +unsigned int xeon_sp_get_skt_count(void); int get_platform_thread_count(void); int get_threads_per_package(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 9837cd9..09237d0 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -22,7 +22,7 @@ int get_platform_thread_count(void) { - return xeon_sp_get_cpu_count() * get_threads_per_package(); + return xeon_sp_get_skt_count() * get_threads_per_package(); } const struct SystemMemoryMapHob *get_system_memory_map(void) @@ -82,8 +82,9 @@ return hob; } -unsigned int xeon_sp_get_cpu_count(void) +unsigned int xeon_sp_get_skt_count(void) { + /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ return get_iio_uds()->SystemStatus.numCpus; } @@ -114,9 +115,7 @@ if (num_apics > 1) bubblesort(apic_ids, num_apics, NUM_ASCENDING); - /* Here num_cpus is the number of processors */ - /* The FSP HOB parameter has it named as num_cpus */ - num_cpus = xeon_sp_get_cpu_count(); + num_cpus = xeon_sp_get_skt_count(); cpu_read_topology(&core_count, &thread_count); assert(num_apics == (num_cpus * thread_count)); @@ -307,7 +306,7 @@ * According to the BIOS writer's guide, this needs to be set on non-SBSP * first, before set on SBSP. */ - for (uint32_t socket = 0; socket < xeon_sp_get_cpu_count(); ++socket) { + for (uint32_t socket = 0; socket < xeon_sp_get_skt_count(); ++socket) { if (socket == sbsp_socket_id) continue; set_bios_init_completion_for_package(socket); -- To view, visit https://review.coreboot.org/c/coreboot/+/42439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1 Gerrit-Change-Number: 42439 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/volteer/variants/volteer: clean up gpio.c
by Nick Vaccaro (Code Review) 22 Jun '20

22 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42577 ) Change subject: mb/google/volteer/variants/volteer: clean up gpio.c ...................................................................... mb/google/volteer/variants/volteer: clean up gpio.c Remove an unneccessary comment and group the variant_early_gpio_table together based on GPIO group. Changed static variable names to be more descriptive. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/volteer/gpio.c 1 file changed, 6 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42577/1 diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c index 33167e3..85dfb95 100644 --- a/src/mainboard/google/volteer/variants/volteer/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer/gpio.c @@ -5,8 +5,7 @@ #include <commonlib/helpers.h> /* Pad configuration in ramstage */ -/* Leave eSPI pins untouched from default settings */ -static const struct pad_config gpio_table[] = { +static const struct pad_config override_gpio_table[] = { /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_A7, 1, DEEP), /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ @@ -210,34 +209,27 @@ }; /* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { +static const struct pad_config override_early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* B11 : PMCALERT# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), - /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* C0 : SMBCLK ==> EN_PP3300_WLAN */ PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), @@ -246,7 +238,6 @@ /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), - /* F12 : GSXDOUT ==> WWAN_RST_ODL To meet timing constrains - drive reset low. Deasserted in ramstage. */ @@ -258,12 +249,12 @@ const struct pad_config *variant_override_gpio_table(size_t *num) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + *num = ARRAY_SIZE(override_early_gpio_table); + return override_early_gpio_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/42577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Gerrit-Change-Number: 42577 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/volteer: add overridetree.cb for volteer
by Nick Vaccaro (Code Review) 22 Jun '20

22 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42550 ) Change subject: mb/google/volteer: add overridetree.cb for volteer ...................................................................... mb/google/volteer: add overridetree.cb for volteer Move volteer-specific devices from baseboard's devicetree.cb into volteer's overridetree.cb file. Adjust the other variant's overridetree.cb files to correspond to the changes made to the baseboard's devicetree.cb in this change. BUG=b:159241303, b:154646959 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer to kernel and verify that the trackpad works. Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/trondo/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb 6 files changed, 334 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42550/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 4478a96..abd4535 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -303,70 +303,9 @@ register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 end - device pci 15.0 on end # I2C #0 0xA0E8 - device pci 15.1 on - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.reset_delay_ms" = "20" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 10 on end - end - end # I2C1 0xA0E9 - device pci 15.2 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR0 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "0" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C2 0xA0EA + device pci 15.0 on end # I2C #0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA device pci 15.3 on end # I2C3 0xA0EB device pci 16.0 on end # HECI1 0xA0E0 @@ -379,16 +318,7 @@ device pci 17.0 on end # SATA 0xA0D3 device pci 19.0 on end # I2C4 0xA0C5 - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" - register "wake" = "GPE0_DW2_15" - register "probed" = "1" - device i2c 15 on end - end - end # I2C5 0xA0C6 + device pci 19.1 on end # I2C5 0xA0C6 device pci 19.2 off end # UART2 0xA0C7 device pci 1c.0 on end # RP1 0xA0B8 diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 20a90cc..e53132a 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -46,6 +46,79 @@ device i2c 32 on end end end # I2C #0 0xA0E8 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 device pci 1f.3 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 8d4c6ea..84493f8 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -19,6 +19,47 @@ device i2c 5d on end end end # I2C1 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 end - end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 75422d8..4bff10d 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -1,4 +1,77 @@ chip soc/intel/tigerlake device domain 0 on + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 end end diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index 75422d8..4bff10d 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -1,4 +1,77 @@ chip soc/intel/tigerlake device domain 0 on + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 end end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 9e5ef4b..4bff10d 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,92 +1,77 @@ chip soc/intel/tigerlake device domain 0 on - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Headset Codec"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO MAX98357_ALC5682I_I2S - probe AUDIO MAX98373_ALC5682I_I2S - end + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 31 on - probe AUDIO MAX98373_ALC5682I_I2S - end + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" - register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 32 on - probe AUDIO MAX98373_ALC5682I_I2S - end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end end - end - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" - register "sdmode_delay" = "5" - device generic 0 on - probe AUDIO MAX98357_ALC5682I_I2S - end - end - chip drivers/intel/soundwire - device generic 0 on - probe AUDIO MAX98373_ALC5682_SNDW - chip drivers/soundwire/alc5682 - # SoundWire Link 0 ID 1 - register "desc" = ""Headset Codec"" - device generic 0.1 on end - end - chip drivers/soundwire/max98373 - # SoundWire Link 1 ID 3 - register "desc" = ""Left Speaker Amp"" - device generic 1.3 on end - end - chip drivers/soundwire/max98373 - # SoundWire Link 1 ID 7 - register "desc" = ""Right Speaker Amp"" - device generic 1.7 on end - end - end - end - end - device pci 1f.2 hidden - # The pmc_mux chip driver is a placeholder for the - # PMC.MUX device in the ACPI hierarchy. - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/con - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" - # SBU & HSL follow CC - device generic 0 on end - end - chip drivers/intel/pmc_mux/con - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end - end - end - end - end # PMC + end # I2C5 0xA0C6 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59 Gerrit-Change-Number: 42550 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/google/volteer: update volteer cbi definition
by Nick Vaccaro (Code Review) 22 Jun '20

22 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42331 ) Change subject: mb/google/volteer: update volteer cbi definition ...................................................................... mb/google/volteer: update volteer cbi definition Update volteer's cbi definition in devicetree.cb to match the current definition for volteer. BUG=none TEST=emerge-volteer coreboot chromeos-bootimage, flash and boot volteer to kernel. Change-Id: I761893818231880d86fd13cfa61319157d06a7d5 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42331/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a55ef7d..ac2a22a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -1,8 +1,10 @@ fw_config field USB_DB 0 3 - option NONE 0 - option USB4 1 - option USB3 2 + option DB_NONE 0 + option DB_USB4_GEN2 1 + option DB_USB3 2 + option DB_USB4_GEN3 3 + option DB_USB3_PASSIVE 4 end field THERMAL 4 7 end field AUDIO 8 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/42331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I761893818231880d86fd13cfa61319157d06a7d5 Gerrit-Change-Number: 42331 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Initialize video console conditionally
by Yu-Ping Wu (Code Review) 22 Jun '20

22 Jun '20

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42505 ) Change subject: libpayload: Initialize video console conditionally ...................................................................... libpayload: Initialize video console conditionally Initialize video console only if LP_VIDEO_CONSOLE is set. BRANCH=none BUG=none TEST=USE="menu_ui" emerge-gale depthcharge Change-Id: Ic45f9073330258cb77301003484ec525b2404180 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M payloads/libpayload/gdb/stub.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/42505/1 diff --git a/payloads/libpayload/gdb/stub.c b/payloads/libpayload/gdb/stub.c index 694577e..395579b4 100644 --- a/payloads/libpayload/gdb/stub.c +++ b/payloads/libpayload/gdb/stub.c @@ -73,9 +73,11 @@ if (!gdb_state.resumed) { /* Must be a die_if() in GDB (or a bug), so bail out and die. */ gdb_exit(-1); - video_console_init(); puts("GDB died, redirecting its last words to the screen:\n"); - console_write(buffer, count); + if (CONFIG(LP_VIDEO_CONSOLE)) { + video_console_init(); + console_write(buffer, count); + } } else { reply.used = 0; reply.buf[reply.used++] = 'O'; -- To view, visit https://review.coreboot.org/c/coreboot/+/42505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic45f9073330258cb77301003484ec525b2404180 Gerrit-Change-Number: 42505 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: Disable D3Code along with pass through mode
by John Zhao (Code Review) 22 Jun '20

22 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42504 ) Change subject: Disable D3Code along with pass through mode ...................................................................... Disable D3Code along with pass through mode The pass through mode(SW CM) RTD3 is not support until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware. BUG=b:159050315 TEST=Verfiy S0ix along with upstream TBT firmware. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42504/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926c..4bc8345 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + register "TcssD3ColdEnable" = "0" # DP port register "DdiPortAConfig" = "1" # eDP -- To view, visit https://review.coreboot.org/c/coreboot/+/42504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Gerrit-Change-Number: 42504 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

6 14

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coreboot-gerrit June 2020