coreboot-gerrit June 2020

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Change in coreboot[master]: soc/amd/picasso/bootblock: Clear BSS section
by Raul Rangel (Code Review) 22 Jun '20

22 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42475 ) Change subject: soc/amd/picasso/bootblock: Clear BSS section ...................................................................... soc/amd/picasso/bootblock: Clear BSS section We are currently relying on the assumption that the amdcompress tool will zero out the bss section. Instead of relying on this assumption, lets explicitly clear it. The implementation was copied from assembly_entry.S. BUG=b:147042464 TEST=Cold boot trembyle and also s3 resume trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c --- M src/soc/amd/picasso/bootblock/pre_c.S 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/42475/1 diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 83e5491..6fae1ed 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -23,6 +23,15 @@ bootblock_pre_c_entry: post_code(0xa0) + /* Clear .bss section */ + cld + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx + shrl $2, %ecx + rep stosl + movl $_eearlyram_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c Gerrit-Change-Number: 42475 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: soc/amd/picass: Write EIP to enable S3
by Raul Rangel (Code Review) 22 Jun '20

22 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42088 ) Change subject: WIP: soc/amd/picass: Write EIP to enable S3 ...................................................................... WIP: soc/amd/picass: Write EIP to enable S3 This now allows S3 to jump to boot block. The TSC value is still wrong. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 BUG=b:147042464 TEST=Resume trembyle and see bootblock start. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 --- M src/soc/amd/picasso/bootblock/bootblock.c A src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/root_complex.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42088/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 1ff6896..9c268af 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -11,7 +11,12 @@ #include <cpu/amd/mtrr.h> #include <soc/southbridge.h> #include <soc/i2c.h> +#include <soc/msr.h> #include <amdblocks/amd_pci_mmconf.h> +#include <stdbool.h> +#include <acpi/acpi.h> + +asmlinkage void bootblock_pre_c_entry(void); static void set_caching(void) { @@ -39,6 +44,22 @@ enable_cache(); } +static void write_eip(void) +{ + bool s3_resume; + msr_t s3_resume_entry = { + .hi = (uint64_t)(uintptr_t)bootblock_pre_c_entry >> 32, + .lo = (uintptr_t)bootblock_pre_c_entry & 0xffffffff, + }; + + s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + + /* Trigger the microcode to stash the CPU state and resume vector + * into the C6 save area. */ + if (!s3_resume) + wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); @@ -57,5 +78,7 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + write_eip(); + fch_early_init(); } diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h new file mode 100644 index 0000000..e7cdf9d --- /dev/null +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_MSR_H__ +#define __PICASSO_MSR_H__ + +#define S3_RESUME_EIP_MSR 0xC00110E0 + +#endif /* __PICASSO_MSR_H__ */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index f621eea..8002048 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -11,6 +11,8 @@ #include <fsp/util.h> #include <stdint.h> +#define RESET_VECTOR_SIZE 0x10 + static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); @@ -30,6 +32,13 @@ /* 1MB to top of low usable RAM */ ram_resource(dev, idx++, 1 * MiB / KiB, (mem_usable - 1 * MiB) / KiB); + /* HACK: Reserve bootblock */ + reserved_ram_resource( + dev, idx++, + (CONFIG_X86_RESET_VECTOR + RESET_VECTOR_SIZE - CONFIG_C_ENV_BOOTBLOCK_SIZE) + / KiB, + CONFIG_C_ENV_BOOTBLOCK_SIZE / KiB); + mmconf_resource(dev, MMIO_CONF_BASE); if (!hob) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Gerrit-Change-Number: 42088 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add VCM and NVM entry for OV8856 sensor
by Varshit B Pandya (Code Review) 22 Jun '20

22 Jun '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41173 ) Change subject: mb/google/dedede: Add VCM and NVM entry for OV8856 sensor ...................................................................... mb/google/dedede: Add VCM and NVM entry for OV8856 sensor Add support for DW9768 and AT24 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl 1 file changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41173/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl index 7cc9034..f631511 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -173,4 +173,128 @@ } }) } + + Device(VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + + Name (_UID, 0x00) /* _UID: Unique ID */ + + Name (_DDN, "DW9768 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9768" + } + } + }) + } + + Device (NVM0) + { + Name (_HID, "PRP0001") // _HID: Hardware ID + + Name (_UID, 0x01) // _UID: Unique ID + + Name (_DDN, "AT24 EEPROM") // _DDN: DOS Device Name + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBusV2 (0x0058, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + CAM0 + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package (0x05) + { + Package (0x02) + { + "size", + 0x2800 + }, + + Package (0x02) + { + "pagesize", + One + }, + + Package (0x02) + { + "read-only", + One + }, + + Package (0x02) + { + "address-width", + 0x0D + }, + + Package (0x02) + { + "compatible", + "atmel,24c1024" + } + } + }) + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/41173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19e4a4107c5bc9d96f718d654df50e2705b98c03 Gerrit-Change-Number: 41173 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mb/ocp/tiogapass: Add documentation
by Jonathan Zhang (Code Review) 22 Jun '20

22 Jun '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40925 to review the following change. Change subject: Documentation/mb/ocp/tiogapass: Add documentation ...................................................................... Documentation/mb/ocp/tiogapass: Add documentation Add OCP platform TiogaPass documentation. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: If4c2832d5bd006c572dab035040b4242f8a3d53b --- A Documentation/mainboard/ocp/tiogapass.md M MAINTAINERS 2 files changed, 105 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40925/1 diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md new file mode 100644 index 0000000..33c5e10 --- /dev/null +++ b/Documentation/mainboard/ocp/tiogapass.md @@ -0,0 +1,95 @@ +# OCP TiogaPass + +This page describes coreboot support status for the OCP (Open Compute Project) +TiogaPass server platform. + +## Introduction + +OCP TiogaPass server platform was contributed by Facebook, and was accepted +in 2019. The design collatoral including datasheet can be found at [OCP TiogaPass]. + +Since complete EE design collaboral is open sourced, anyone can build a variant +based on the original design. It can also be purchased from [OCP Market Place]. +An off-the-shelf version is available, as well as rack ready version. With the +off-the-shelf version, the server can be plugged into wall power outlet. + +With the off-the-shelf version of TiogaPass, a complete software solution is +available. [Off-the-shelf Host Firmware] takes the approach of UEFI/Linuxboot. + +Coreboot as of release 4.13 is a proof-of-concept project between Facebook, +Intel, Wiwynn and Quanta. More context can be referenced at [OCP TiogaPass POC Blog]. +## Required blobs + +This board currently requires: +fsp blob - The blob is not available to the public. The binary is at POC +status, hopefully there is a IBV stepping up to maintain the binary. +Microcode - 3rdparty/intel-microcode/intel-ucode/06-55-04 +ME binary - The binary can be extracted from [Off-the-shelf Host Firmware]. +Linuxboot binary - This is optional. U-root as initramfs, is used in the POC +activity. It can be extracted from [Off-the-shelf Host Firmware], or it can be +built according to [All about u-root]. + +## Flashing coreboot + +### Internal programming + +Using [flashrom] is not verified. + +### External programming + +From OpenBMC, to update FW image: +fw-util mb --force --update <path to coreboot image> + +To power off/on the host: +power-util mb off +power-util mb on + +To connect to console through SOL (Serial Over Lan): +sol-util mb + +## Known issues / feature gaps +- c6 state is not supported. Workaround is to disable c6 support through +target OS and Linuxboot kernel paramter. +- SMI handlers are not implemented. +- xSDT tables are not fully populated, such as processor/socket devices, +PCIe bridge devices. +- There is boot stability issue. +- If [CB 40500 patchset] is not merged, when PCIe riser card is used, +boot fails. +- PCIe devices connected to socket 1 may not work, due to FSP issue. +- Some TiogaPass SKUs do not have all PCIe devices working. +- SMBIOS type 7 and type 17 are not populated. + +- None + +## Working +- Most SMBIOS types. +- BMC integration: +-- BMC readiness check +-- IPMI commands +-- watchdog timer +-- POST complete pin acknowledgement. +- SEL record generation. +- Early serial output. +- port 80h direct to GPIO. +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| SoC (2 sockets) | Intel SkyLake Scalable Processor LGA3647 | ++------------------+--------------------------------------------------+ +| BMC | Aspeed 2500 | ++------------------+--------------------------------------------------+ +| PCH | Intel Lewisburg C620 | ++------------------+--------------------------------------------------+ +``` + +[flashrom]: https://flashrom.org/Flashrom +[OCP TiogaPass]: https://www.opencompute.org/contributions?query=Tioga%20Pass%20v1.0 +[OCP Market Place]: https://www.opencompute.org/products/109/wiwynn-tioga-pass-advanced-2u-ocp-… +[Off-the-shelf Host Firmware]: https://github.com/linuxboot/book/blob/master/case_studies/TiogaPass/README… +[OCP TiogaPass POC Blog]: https://www.opencompute.org/blog/linux-firmware-boots-up-server-powered-by-… +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[CB 40500 patchset]: https://review.coreboot.org/c/coreboot/+/40500 diff --git a/MAINTAINERS b/MAINTAINERS index bc1e1fc..3531292 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,6 +362,16 @@ S: Maintained F: src/mainboard/facebook/monolith/ +OCP TIOGAPASS MAINBOARD +M: Jonathan Zhang <jonzhang(a)fb.com> +M: Reddy Chagam <anjaneya.chagam(a)intel.com> +M: Johnny Lin <Johnny_Lin(a)wiwynn.com> +M: Morgan Jang <Morgan_Jang(a)wiwynn.com> +M: Ryback Hung <<Ryback.Hung(a)quantatw.com> +M: Bryant Ou <Bryant.Ou(a)quantatw.com> +S: Maintained +F: src/mainboard/ocp/tiogapass + PORTWELL PQ-M107 MAINBOARD M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/40925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c2832d5bd006c572dab035040b4242f8a3d53b Gerrit-Change-Number: 40925 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma/intel_ddi.c: Clean up
by HAOUAS Elyes (Code Review) 22 Jun '20

22 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41996 ) Change subject: drivers/intel/gma/intel_ddi.c: Clean up ...................................................................... drivers/intel/gma/intel_ddi.c: Clean up Remove unused includes. Change-Id: I91dd92b54822dd0d10051ccd600ce787860c8ff6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/intel_ddi.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/41996/1 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 3893664..24bc162 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: MIT */ #include <types.h> -#include <device/device.h> -#include <device/pci_def.h> #include <console/console.h> -#include <acpi/acpi.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> -#include <cpu/x86/tsc.h> -#include <edid.h> #include <drivers/intel/gma/i915.h> /* HDMI/DVI modes ignore everything but the last 2 items. So we share -- To view, visit https://review.coreboot.org/c/coreboot/+/41996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91dd92b54822dd0d10051ccd600ce787860c8ff6 Gerrit-Change-Number: 41996 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/sc7180/qupv3_config.c: Add missing <string.h>
by HAOUAS Elyes (Code Review) 22 Jun '20

22 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42343 ) Change subject: soc/qualcomm/sc7180/qupv3_config.c: Add missing <string.h> ...................................................................... soc/qualcomm/sc7180/qupv3_config.c: Add missing <string.h> Also add missing 'commonlib/bsd/cbfs_serialized.h' Change-Id: I7e66a3cbf50fa27b4f6be6885b324de90eddd387 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/sc7180/qupv3_config.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42343/1 diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 2c4554d..8878a1a 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/cbfs_serialized.h> #include <soc/qupv3_config.h> +#include <string.h> static struct elf_se_hdr *fw_list[SE_PROTOCOL_MAX]; -- To view, visit https://review.coreboot.org/c/coreboot/+/42343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e66a3cbf50fa27b4f6be6885b324de90eddd387 Gerrit-Change-Number: 42343 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42426 ) Change subject: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/42426/4/src/southbridge/intel/i828… File src/southbridge/intel/i82801gx/smihandler.c: https://review.coreboot.org/c/coreboot/+/42426/4/src/southbridge/intel/i828… PS4, Line 26: /* WAS BROKEN */ What's the purpose here: is that a TODO that the function needs to be filled in with a correct implementation? Is this only overriding a default because even that default behavior isn't needed anymore? As-is, it's hard to figure out what the intent of both the comment and the function is without lots of digging, so please make that clearer. -- To view, visit https://review.coreboot.org/c/coreboot/+/42426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Gerrit-Change-Number: 42426 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Jun 2020 11:48:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801dx: Drop APM_CNT_GNVS_UPDATE
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42425 ) Change subject: sb/intel/i82801dx: Drop APM_CNT_GNVS_UPDATE ...................................................................... sb/intel/i82801dx: Drop APM_CNT_GNVS_UPDATE In commit 96cb252 the accompanying implementation of smm_setup_structures() was already dropped. Change-Id: I9cff0cbaa85cf771cc7761b6c5286ec34a76ee9a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42425 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/i82801dx/smihandler.c 1 file changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9f9f2f3..b526a1a 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -25,7 +25,6 @@ * initialize it with a sane value */ u16 pmbase = PMBASE_ADDR; -u8 smm_initialized = 0; unsigned char *mbi = NULL; u32 mbi_len; @@ -362,17 +361,6 @@ outl(pmctrl, pmbase + PM1_CNT); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); - return; - } - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); - break; case APM_CNT_MBI_UPDATE: // FIXME if (mbi_initialized) { printk(BIOS_DEBUG, "SMI#: mbi already registered!\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/42425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cff0cbaa85cf771cc7761b6c5286ec34a76ee9a Gerrit-Change-Number: 42425 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCI
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42619 ) Change subject: cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCI ...................................................................... cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCI Change-Id: I0bc321f499278e0cdbfb40be9a2b2ae21828d2f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42619 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/x86/smm.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_xhci.c 3 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 513b6df..9db1461 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -24,6 +24,7 @@ #define APM_CNT_ACPI_ENABLE 0xe1 #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc #define APM_CNT_SMMINFO 0xec diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8bbe3fe..be842c5 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -330,7 +330,7 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; - case 0xca: + case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break; case APM_CNT_ELOG_GSMI: diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 8684aa9..1cfec1b 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/smm.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> #include "chip.h" @@ -356,7 +356,7 @@ usb_xhci_reset_usb3(dev, 0); } else if (config->xhci_default) { /* Route all ports to XHCI */ - outb(0xca, 0xb2); + apm_control(APM_CNT_ROUTE_ALL_XHCI); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bc321f499278e0cdbfb40be9a2b2ae21828d2f4 Gerrit-Change-Number: 42619 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/lynxpoint: Drop stale code paths
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42618 ) Change subject: sb/intel/lynxpoint: Drop stale code paths ...................................................................... sb/intel/lynxpoint: Drop stale code paths These appear to be leftovers from old SMM relocation code. Change-Id: I689bee55943b29990f54cb798b999940eae180bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42618 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/smi.c 1 file changed, 0 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 102ed24..48b76e2 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -58,38 +58,6 @@ smm_southbridge_enable(PWRBTN_EN | GBL_EN); } -static void __unused southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local APIC is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - apm_control(APM_CNT_NOOP_SMI); -} - -static void __unused southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I689bee55943b29990f54cb798b999940eae180bc Gerrit-Change-Number: 42618 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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