coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/hatch: Make puff and variants share common ec.h
by Edward O'Callaghan (Code Review) 22 Jun '20

22 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42552 ) Change subject: mb/google/hatch: Make puff and variants share common ec.h ...................................................................... mb/google/hatch: Make puff and variants share common ec.h Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- A src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h M src/mainboard/google/hatch/variants/duffy/include/variant/ec.h M src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h M src/mainboard/google/hatch/variants/noibat/include/variant/ec.h M src/mainboard/google/hatch/variants/puff/include/variant/ec.h 5 files changed, 67 insertions(+), 212 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42552/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h new file mode 100644 index 0000000..7af174d --- /dev/null +++ b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. + */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h index 7af174d..59fb378 100644 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h @@ -3,57 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <ec/google/chromeec/ec_commands.h> -#include <variant/gpio.h> +#include <puff/ec.h> -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS 0 - -/* EC can wake from S5 with power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with power button */ -#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable cros_ec_keyb device */ -#define EC_ENABLE_MKBP_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* - * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# - * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. - */ -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ - -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - -#endif /* VARIANT_EC_H */ +#endif diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h index 7af174d..59fb378 100644 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h @@ -3,57 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <ec/google/chromeec/ec_commands.h> -#include <variant/gpio.h> +#include <puff/ec.h> -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS 0 - -/* EC can wake from S5 with power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with power button */ -#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable cros_ec_keyb device */ -#define EC_ENABLE_MKBP_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* - * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# - * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. - */ -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ - -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - -#endif /* VARIANT_EC_H */ +#endif diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h b/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h index 7af174d..59fb378 100644 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h @@ -3,57 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <ec/google/chromeec/ec_commands.h> -#include <variant/gpio.h> +#include <puff/ec.h> -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS 0 - -/* EC can wake from S5 with power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with power button */ -#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable cros_ec_keyb device */ -#define EC_ENABLE_MKBP_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* - * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# - * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. - */ -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ - -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - -#endif /* VARIANT_EC_H */ +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h index 7af174d..59fb378 100644 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -3,57 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <ec/google/chromeec/ec_commands.h> -#include <variant/gpio.h> +#include <puff/ec.h> -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) - -#define MAINBOARD_EC_SMI_EVENTS 0 - -/* EC can wake from S5 with power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with power button */ -#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ - (MAINBOARD_EC_S3_WAKE_EVENTS | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable cros_ec_keyb device */ -#define EC_ENABLE_MKBP_DEVICE - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* - * Defines EC wake pin route. - * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# - * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. - */ -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ - -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - -#endif /* VARIANT_EC_H */ +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Gerrit-Change-Number: 42552 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: post_code: add defines for missing postcode values
by Sindhoor Tilak (Code Review) 22 Jun '20

22 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42278 to look at the new patch set (#7). Change subject: post_code: add defines for missing postcode values ...................................................................... post_code: add defines for missing postcode values The change introduces new POST codes define for post codes missing their respective defines The newly added POST code sets are arranged in logical order of coreboot stages. The change also is an effort to ensure the added defines reflect postcodes at the entry of function. Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc --- M src/include/console/post_codes.h 1 file changed, 305 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42278/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc Gerrit-Change-Number: 42278 Gerrit-PatchSet: 7 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: payloads/Kconfig: Allow compressing Linux
by Angel Pons (Code Review) 21 Jun '20

21 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42670 ) Change subject: payloads/Kconfig: Allow compressing Linux ...................................................................... payloads/Kconfig: Allow compressing Linux Can we do this? Does it work? Change-Id: I370df9b5612b3c30d4ccafcbc9b1599914349640 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42670/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index cfb28d6..66e0e54 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -57,8 +57,8 @@ choice prompt "Payload compression algorithm" default COMPRESSED_PAYLOAD_LZMA - default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT - depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT + default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUXBOOT || PAYLOAD_FIT + depends on !PAYLOAD_NONE && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT help Choose the compression algorithm for the chosen payloads. You can choose between None, LZMA, or LZ4. -- To view, visit https://review.coreboot.org/c/coreboot/+/42670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I370df9b5612b3c30d4ccafcbc9b1599914349640 Gerrit-Change-Number: 42670 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/protectli/vault_kbl: Enable Intel PTT
by Michał Żygowski (Code Review) 21 Jun '20

21 Jun '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42565 ) Change subject: mb/protectli/vault_kbl: Enable Intel PTT ...................................................................... mb/protectli/vault_kbl: Enable Intel PTT TEST=tweak PCR banks in SeaBIOS TPM menu, run tpm2_pcrlist in Linux Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e --- M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/protectli/vault_kbl/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/42565/1 diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 8c09a60..518bb6d 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -11,6 +11,9 @@ select SOC_INTEL_KABYLAKE select SPI_FLASH_MACRONIX select SUPERIO_ITE_IT8772F + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 config IRQ_SLOT_COUNT int diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d3e8b23..bb408a4 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -305,4 +305,7 @@ device pci 1f.5 off end # PCH SPI device pci 1f.6 off end # GbE end + chip drivers/crb + device mmio 0xfed40000 on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c443a25ca7259df9c0a07615d0502f47d25792e Gerrit-Change-Number: 42565 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: _WIP_ mb/amd/mandolin: Add Picasso CRB
by Marshall Dawson (Code Review) 21 Jun '20

21 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33772 Change subject: _WIP_ mb/amd/mandolin: Add Picasso CRB ...................................................................... _WIP_ mb/amd/mandolin: Add Picasso CRB We can get into ramstage with the state of Mandolin. Still no AGESA running, and therefore we hang when trying to scan the PCI bus. Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/mainboard/amd/mandolin/Kconfig A src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/acpi/gpe.asl A src/mainboard/amd/mandolin/acpi/mainboard.asl A src/mainboard/amd/mandolin/acpi/routing.asl A src/mainboard/amd/mandolin/acpi/sleep.asl A src/mainboard/amd/mandolin/acpi/usb_oc.asl A src/mainboard/amd/mandolin/acpi_tables.c A src/mainboard/amd/mandolin/board_info.txt A src/mainboard/amd/mandolin/devicetree.cb A src/mainboard/amd/mandolin/dsdt.asl A src/mainboard/amd/mandolin/gpio.c A src/mainboard/amd/mandolin/gpio.h A src/mainboard/amd/mandolin/irq_tables.c A src/mainboard/amd/mandolin/mainboard.c A src/mainboard/amd/mandolin/mptable.c A src/mainboard/amd/mandolin/romstage.c 18 files changed, 1,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33772/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig new file mode 100644 index 0000000..5d1c287 --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig @@ -0,0 +1,98 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_MANDOLIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_PICASSO + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config AMD_LPC_DEBUG_CARD + bool "Enable LPC-Serial debug card on the debug header" + default n + select SUPERIO_SMSC_SIO1036 + help + AMD's debug card contains an SMSC SIO1036 device which provides + an I/O-based UART in the system. This feature is not compatible with + CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. + Note that Kconfig does not currently enforce this restriction. + +config CBFS_SIZE + default 0x400000 + help + TODO: Adjust this! Right now it's simply making a lot of room for + amdfw.rom and EC firmware. + +config MAINBOARD_DIR + string + default amd/mandolin + +config MAINBOARD_PART_NUMBER + string + default "MANDOLIN" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config PICASSO_LEGACY_FREE + bool + default y + +config MANDOLIN_HAVE_APCB_BLOB + bool "Have AGESA PSP Customization Block file?" + default n + help + The PSP requires the APCB file to know how to configure memory, as + well as other settings it will initialize. To build an image that + will get to POST, select 'y' and provide the file path/name. The + default of 'n' allows the board to build successfully but it avoids + redistributing the APCB blob extracted from UEFI. + TODO: Add the ability to construct APCB on the fly for any mainboard. + +config PSP_APCB_FILE + string "APCB file" + depends on MANDOLIN_HAVE_APCB_BLOB + default "3rdparty/blobs/mainboard/amd/mandolin/apcb.bin" + help + The name of the AGESA Parameter Customization Block. TODO: will we + be able to generate this at build-time? Build it offline for + inclusion? + +config MANDOLIN_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + select AMDFW_OUTSIDE_CBFS + # todo: fix build the "inside" build. + +config MANDOLIN_MCHP_FW_FILE + string + depends on MANDOLIN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin" + +endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name new file mode 100644 index 0000000..7dbfc3f --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MANDOLIN + bool "Mandolin" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc new file mode 100644 index 0000000..fe17e8e --- /dev/null +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -0,0 +1,41 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += gpio.c +ramstage-y += gpio.c + +PHONY+=add_mchp_fw +INTERMEDIATE+=add_mchp_fw + +ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) + +MANDOLIN_MICROCHIP_FW_OFFSET=0 +add_mchp_fw: + printf " DD Adding Microchip firmware at ROM offset 0x%x\n" \ + "$(MANDOLIN_MICROCHIP_FW_OFFSET)" + dd if=$(CONFIG_MANDOLIN_MCHP_FW_FILE) \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 \ + seek=$(MANDOLIN_MICROCHIP_FW_OFFSET) >/dev/null 2>&1 + +else +files_added:: warn_no_mchp +endif # CONFIG_MANDOLIN_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC.\n" + printf "Do not flash this image. Your Mandolin's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/mandolin/acpi/gpe.asl b/src/mainboard/amd/mandolin/acpi/gpe.asl new file mode 100644 index 0000000..d3c89fd --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/gpe.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/mandolin/acpi/mainboard.asl b/src/mainboard/amd/mandolin/acpi/mainboard.asl new file mode 100644 index 0000000..d73fbea --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/mainboard.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/mandolin/acpi/routing.asl b/src/mainboard/amd/mandolin/acpi/routing.asl new file mode 100644 index 0000000..969def7 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/routing.asl @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, +}) + + +/* GPP 0 */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl new file mode 100644 index 0000000..baf3ca5 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/sleep.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/mandolin/acpi/usb_oc.asl b/src/mainboard/amd/mandolin/acpi/usb_oc.asl new file mode 100644 index 0000000..ea7bd27 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/usb_oc.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// - file had a todo to update for Gardenia +// +// +// + +/* simple name description */ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ diff --git a/src/mainboard/amd/mandolin/acpi_tables.c b/src/mainboard/amd/mandolin/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/mandolin/board_info.txt b/src/mainboard/amd/mandolin/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/mandolin/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb new file mode 100644 index 0000000..8cb7da9 --- /dev/null +++ b/src/mainboard/amd/mandolin/devicetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/picasso + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.2 on end # Bridge + device pci 1.3 on end # Bridge + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on end # Bridge + device pci 8.2 on end # Bridge + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + device i2c 51 on end + end + chip superio/smsc/sio1036 # optional debug card + end + end # SM + device pci 14.3 on end # LPC + device pci 14.6 on end # + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + # todo: on a separate bus now: + # 2:0.0 15D8 display controller + # 2:0.1 15DE HD Audio + # 2:0.2 15DF Crypto Coprocessor + # 2:0.3 15E0 serial + # 2:0.4 15E1 serial + # 2:0.5 15E2 Audio Processor + # 2:0.6 15E3 Audio Processor - HD Audio Controller + # 2:0.7 15E6 Non-Sensor Fusion hub device + # 3:0.0 7901 SATA + # 3:0.1 1458 10GbE (per HDT) + # 3:0.2 1458 10GbE (per HDT) +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl new file mode 100644 index 0000000..25c0e78 --- /dev/null +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// +// +// +// todo: check file for accuracy +// +// +// + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c new file mode 100644 index 0000000..aa16826 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/southbridge.h> +#include <stdlib.h> +#include <soc/gpio.h> + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC5_L */ + PAD_GPI(GPIO_13, PULL_UP), + /* not USB_OC4_L */ + PAD_GPI(GPIO_14, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe SSD power enable */ + PAD_GPO(GPIO_23, HIGH), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0_S5, PULL_NONE), + /* SATA Express DEVSLP */ + PAD_NF(GPIO_6, DEVSLP1_S5, PULL_NONE), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h new file mode 100644 index 0000000..1d3a8a2 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mandolin/irq_tables.c b/src/mainboard/amd/mandolin/irq_tables.c new file mode 100644 index 0000000..bf1daec --- /dev/null +++ b/src/mainboard/amd/mandolin/irq_tables.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c new file mode 100644 index 0000000..6f2d1d9 --- /dev/null +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/southbridge.h> + +#include "gpio.h" +// +// +// +// todo: check file for accuracy +// +// +// + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in mandolin board. + *************************************************/ +static void mandolin_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mandolin_enable, +}; diff --git a/src/mainboard/amd/mandolin/mptable.c b/src/mainboard/amd/mandolin/mptable.c new file mode 100644 index 0000000..4e80ce1 --- /dev/null +++ b/src/mainboard/amd/mandolin/mptable.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/x86/lapic.h> +#include <soc/southbridge.h> +#include <amdblocks/amd_pci_util.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c new file mode 100644 index 0000000..1741a39 --- /dev/null +++ b/src/mainboard/amd/mandolin/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <superio/smsc/sio1036/sio1036.h> +#include <soc/gpio.h> +#include "gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) + +void romstage_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + + if (CONFIG(SUPERIO_SMSC_SIO1036)) + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Gerrit-Change-Number: 33772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 65

Change in coreboot[master]: util/abuild: Use absolute paths for (failed|passed)_boards
by Angel Pons (Code Review) 21 Jun '20

21 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29451 ) Change subject: util/abuild: Use absolute paths for (failed|passed)_boards ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief00e28e09a4714b0106c35ad4f4e9c696f6aad4 Gerrit-Change-Number: 29451 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 21 Jun 2020 15:22:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: fmap: Avoid unaligned access
by Simon Glass (Code Review) 21 Jun '20

21 Jun '20

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40243 ) Change subject: fmap: Avoid unaligned access ...................................................................... fmap: Avoid unaligned access The fmap header has unaligned fields in it. Some CPUs do not like this, and it is not very friendly to hide this sort of thing in innocuous code. Fix it by copying the data into an aligned location first. BUG=b:153203967 TEST=See this output now: Getting SPI ROM info. FMAP: Found "FLASH" version 1.1 at 0xb04000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 29 Signed-off-by: Simon Glass <sjg(a)chromium.org> Change-Id: I6ac83766616cb2107b75eba6995cd09b4fc90968 --- M src/lib/fmap.c 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40243/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index ecd23f6..4a67053 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -35,10 +35,15 @@ static void report(const struct fmap *fmap) { + uint64_t base; + uint32_t size; + print_once(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %#x.\n", fmap->name, fmap->ver_major, fmap->ver_minor, FMAP_OFFSET); + memcpy(&base, &fmap->base, sizeof(fmap->base)); + memcpy(&size, &fmap->size, sizeof(fmap->size)); print_once(BIOS_DEBUG, "FMAP: base = %#llx size = %#x #areas = %d\n", - (long long)fmap->base, fmap->size, fmap->nareas); + base, size, fmap->nareas); fmap_print_once = 1; } @@ -155,6 +160,7 @@ while (1) { struct fmap_area *area; + uint32_t area_offset, area_size; area = rdev_mmap(&fmrd, offset, sizeof(*area)); @@ -166,12 +172,14 @@ offset += sizeof(struct fmap_area); continue; } + memcpy(&area_offset, &area->offset, sizeof(area->offset)); + memcpy(&area_size, &area->size, sizeof(area->size)); printk(BIOS_DEBUG, "FMAP: area %s found @ %x (%d bytes)\n", - name, area->offset, area->size); + name, area_offset, area_size); - ar->offset = area->offset; - ar->size = area->size; + ar->offset = area_offset; + ar->size = area_size; rdev_munmap(&fmrd, area); -- To view, visit https://review.coreboot.org/c/coreboot/+/40243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ac83766616cb2107b75eba6995cd09b4fc90968 Gerrit-Change-Number: 40243 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: [WIP] payloads/external: Provide generic Makefile.git
by HAOUAS Elyes (Code Review) 21 Jun '20

21 Jun '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21163 ) Change subject: [WIP] payloads/external: Provide generic Makefile.git ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/21163/1/payloads/external/Makefile… File payloads/external/Makefile.git: https://review.coreboot.org/c/coreboot/+/21163/1/payloads/external/Makefile… PS1, Line 1: ## : ## This file is part of the coreboot project. : ## : ## Copyright (C) 2017 Nico Huber <nico.h(a)gmx.de> : ## : ## This program is free software; you can redistribute it and/or modify : ## it under the terms of the GNU General Public License as published by : ## the Free Software Foundation; version 2 of the License. : ## : ## This program is distributed in the hope that it will be useful, : ## but WITHOUT ANY WARRANTY; without even the implied warranty of : ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : ## GNU General Public License for more details. : ## :) no, seriously, is this still in progress? -- To view, visit https://review.coreboot.org/c/coreboot/+/21163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7557ca81fa1e32cd5c17c757e9458d048ff1ec99 Gerrit-Change-Number: 21163 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 21 Jun 2020 12:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src: s/__FUNCTION__/__func__/
by Angel Pons (Code Review) 21 Jun '20

21 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42516 ) Change subject: src: s/__FUNCTION__/__func__/ ...................................................................... src: s/__FUNCTION__/__func__/ The former is not standard C, and we primarily use the latter form. Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/commonlib/include/commonlib/stdlib.h M src/drivers/pc80/tpm/tis.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c M src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c M src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c M src/vendorcode/cavium/bdk/libdram/dram-internal.h M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c M src/vendorcode/cavium/bdk/libdram/libdram.c 12 files changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42516/1 diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index 307406f..374fe16 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -29,7 +29,7 @@ } return ret; } -#define xmalloc(size) xmalloc_work((size), __FILE__, __FUNCTION__, __LINE__) +#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__) static inline void *xzalloc_work(size_t size, const char *file, const char *func, int line) @@ -38,7 +38,7 @@ memset(ret, 0, size); return ret; } -#define xzalloc(size) xzalloc_work((size), __FILE__, __FUNCTION__, __LINE__) +#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__) void *dma_malloc(size_t size); int dma_coherent(void *ptr); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..e18f9af 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -395,7 +395,7 @@ didvid = tpm_read_did_vid(0); if (!didvid || (didvid == 0xffffffff)) { - printf("%s: No TPM device found\n", __FUNCTION__); + printf("%s: No TPM device found\n", __func__); return TPM_DRIVER_ERR; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e65b8e5..1f267f9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -416,7 +416,7 @@ u32 eop_ack; /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; @@ -513,7 +513,7 @@ /* Check if the MBP is ready */ if (!gmes.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __func__); path = ME_ERROR_BIOS_PATH; } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index aeab0c7..cdae271 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -529,7 +529,7 @@ }; /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { /* No response means reset will happen shortly... */ halt(); @@ -551,7 +551,7 @@ u32 eop_ack; /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; @@ -698,7 +698,7 @@ /* Check if the MBP is ready */ if (!hfs2.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __func__); path = ME_ERROR_BIOS_PATH; } diff --git a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c index fc9ac35..9b17745 100644 --- a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c +++ b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c @@ -70,7 +70,7 @@ case BDK_CSR_TYPE_RVU_PFVF_BAR2: case BDK_CSR_TYPE_RVU_VF_BAR2: /* Handled by inline code, we should never get here */ - bdk_error("%s: Passed type that should be handled inline\n", __FUNCTION__); + bdk_error("%s: Passed type that should be handled inline\n", __func__); break; case BDK_CSR_TYPE_PCCBR: @@ -80,7 +80,7 @@ case BDK_CSR_TYPE_MDSB: case BDK_CSR_TYPE_PCICONFIGEP_SHADOW: case BDK_CSR_TYPE_PCICONFIGEPVF: - bdk_error("%s: Register not supported\n", __FUNCTION__); + bdk_error("%s: Register not supported\n", __func__); break; case BDK_CSR_TYPE_SYSREG: @@ -99,7 +99,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC0_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 1: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -109,7 +109,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC1_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 2: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -119,7 +119,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC2_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 3: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -127,7 +127,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN83XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC3_CN83XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 4: dev_con.u = BDK_PCC_DEV_CON_E_PCIERC4; @@ -136,7 +136,7 @@ dev_con.u = BDK_PCC_DEV_CON_E_PCIERC5; break; default: - bdk_error("%s: Illegal PCIe bus number\n", __FUNCTION__); + bdk_error("%s: Illegal PCIe bus number\n", __func__); return -1; } return bdk_pcie_config_read32(node, 100 + dev_con.cn8.ecam, dev_con.s.bus, dev_con.s.func >> 3, dev_con.s.func & 7, address); @@ -180,7 +180,7 @@ case BDK_CSR_TYPE_RVU_PFVF_BAR2: case BDK_CSR_TYPE_RVU_VF_BAR2: /* Handled by inline code, we should never get here */ - bdk_error("%s: Passed type that should be handled inline\n", __FUNCTION__); + bdk_error("%s: Passed type that should be handled inline\n", __func__); break; case BDK_CSR_TYPE_PCCBR: @@ -190,7 +190,7 @@ case BDK_CSR_TYPE_MDSB: case BDK_CSR_TYPE_PCICONFIGEP_SHADOW: case BDK_CSR_TYPE_PCICONFIGEPVF: - bdk_error("%s: Register not supported\n", __FUNCTION__); + bdk_error("%s: Register not supported\n", __func__); break; case BDK_CSR_TYPE_SYSREG: @@ -210,7 +210,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC0_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 1: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -220,7 +220,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC1_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 2: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -230,7 +230,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC2_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 3: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -238,7 +238,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN83XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC3_CN83XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 4: dev_con.u = BDK_PCC_DEV_CON_E_PCIERC4; @@ -247,7 +247,7 @@ dev_con.u = BDK_PCC_DEV_CON_E_PCIERC5; break; default: - bdk_error("%s: Illegal PCIe bus number\n", __FUNCTION__); + bdk_error("%s: Illegal PCIe bus number\n", __func__); return; } bdk_pcie_config_write32(node, 100 + dev_con.cn8.ecam, dev_con.s.bus, dev_con.s.func >> 3, dev_con.s.func & 7, address, value); diff --git a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c index 0f75da2..81e1a78 100644 --- a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c @@ -162,7 +162,7 @@ } } else - bdk_error("N%d.QLM%d: Unsupported chip, update %s()\n", node, qlm, __FUNCTION__); + bdk_error("N%d.QLM%d: Unsupported chip, update %s()\n", node, qlm, __func__); } /** diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c index 0efe697..6c92a59 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c @@ -49,7 +49,7 @@ { int phy_status = 0; - BDK_TRACE(PHY, "%s In SGMII mode for Marvell PHY 88E1512\n", __FUNCTION__); + BDK_TRACE(PHY, "%s In SGMII mode for Marvell PHY 88E1512\n", __func__); /* Switch to Page 18 */ phy_status = bdk_mdio_write(node, mdio_bus, mdio_addr, 22, 18); if (phy_status < 0) @@ -89,7 +89,7 @@ int bdk_if_phy_marvell_setup(bdk_node_t node, int qlm, int mdio_bus, int phy_addr) { - BDK_TRACE(PHY,"In %s\n",__FUNCTION__); + BDK_TRACE(PHY,"In %s\n",__func__); /* Check if the PHY is marvell PHY we expect */ int phy_status = bdk_mdio_read(node, mdio_bus, phy_addr, BDK_MDIO_PHY_REG_ID1); @@ -100,13 +100,13 @@ /* Switch the marvell PHY to the correct mode */ bdk_qlm_modes_t qlm_mode = bdk_qlm_get_mode(node, qlm); - BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__FUNCTION__, qlm, qlm_mode); + BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__func__, qlm, qlm_mode); if ((qlm_mode != BDK_QLM_MODE_SGMII_1X1) && (qlm_mode != BDK_QLM_MODE_SGMII_2X1)) return 0; - BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__); + BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __func__); for (int port = 0; port < 2; port++) { setup_marvell_phy(node, mdio_bus, phy_addr + port); diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c index 26c4fd4..796d699 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c @@ -91,7 +91,7 @@ uint16_t reg_val; uint16_t mask; - BDK_TRACE(PHY,"In %s\n",__FUNCTION__); + BDK_TRACE(PHY,"In %s\n",__func__); BDK_TRACE(PHY,"Loading init script for VSC8514\n"); ptr = init_script_rev_a; diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c index 303b276..5582e08 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c @@ -773,7 +773,7 @@ } else { - bdk_error("Update %s for qlm auto config of this chip\n",__FUNCTION__); + bdk_error("Update %s for qlm auto config of this chip\n",__func__); return; } BDK_CSR_MODIFY(c, node, BDK_GSERX_REFCLK_SEL(qlm), diff --git a/src/vendorcode/cavium/bdk/libdram/dram-internal.h b/src/vendorcode/cavium/bdk/libdram/dram-internal.h index 02bf0d0..a54d2a4 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-internal.h +++ b/src/vendorcode/cavium/bdk/libdram/dram-internal.h @@ -158,7 +158,7 @@ #define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4 spd_ddr_type = read_spd(node, dimm_config, DEVICE_TYPE); - debug_print("%s:%d spd_ddr_type=0x%02x\n", __FUNCTION__, __LINE__, spd_ddr_type); + debug_print("%s:%d spd_ddr_type=0x%02x\n", __func__, __LINE__, spd_ddr_type); /* we return only DDR4 or DDR3 */ return (spd_ddr_type == 0x0C) ? DDR4_DRAM : DDR3_DRAM; diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 291fe85..ebbe836 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -199,7 +199,7 @@ } debug_print("N%d.LMC%d: %s: returning bin %d for MTS %d\n", - node, lmc, __FUNCTION__, ret, mts_speed); + node, lmc, __func__, ret, mts_speed); return ret; } @@ -857,9 +857,9 @@ // run the test one last time // print whether there are errors or not, but only when verbose... bdk_watchdog_poke(); - debug_print("N%d: %s: Start running test one last time\n", node, __FUNCTION__); + debug_print("N%d: %s: Start running test one last time\n", node, __func__); tot_errors = run_dram_tuning_threads(node, num_lmcs, bytemask); - debug_print("N%d: %s: Finished running test one last time\n", node, __FUNCTION__); + debug_print("N%d: %s: Finished running test one last time\n", node, __func__); if (tot_errors) ddr_print2("%s Timing Final Test: errors 0x%x\n", mode_str, tot_errors); @@ -893,7 +893,7 @@ orig_coremask = bdk_get_running_coremask(node); /* FIXME(dhendrix): %lx --> %llx */ ddr_print4("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, orig_coremask); + node, __func__, orig_coremask); /* FIXME(dhendrix): don't call bdk_init_cores(). */ // bdk_init_cores(node, ~0ULL & ~orig_coremask); dram_tune_max_cores = bdk_get_num_running_cores(node); @@ -979,7 +979,7 @@ ddr_interface_64b = !lmc_config.s.mode32b; // do setup for each active LMC - debug_print("N%d: %s: starting LMCs setup.\n", node, __FUNCTION__); + debug_print("N%d: %s: starting LMCs setup.\n", node, __func__); for (lmc = 0; lmc < num_lmcs; lmc++) { #if 0 @@ -1019,7 +1019,7 @@ #endif // perform cleanup on all active LMCs - debug_print("N%d: %s: starting LMCs cleanup.\n", node, __FUNCTION__); + debug_print("N%d: %s: starting LMCs cleanup.\n", node, __func__); for (lmc = 0; lmc < num_lmcs; lmc++) { /* Restore ECC for DRAM tests */ @@ -1066,12 +1066,12 @@ uint64_t reset_coremask = 0; if (reset_coremask) { /* FIXME(dhendrix): %lx --> %llx */ - ddr_print4("N%d: %s: Stopping cores 0x%llx\n", node, __FUNCTION__, + ddr_print4("N%d: %s: Stopping cores 0x%llx\n", node, __func__, reset_coremask); bdk_reset_cores(node, reset_coremask); } else { /* FIXME(dhendrix): %lx --> %llx */ - ddr_print4("N%d: %s: leaving cores set to 0x%llx\n", node, __FUNCTION__, + ddr_print4("N%d: %s: leaving cores set to 0x%llx\n", node, __func__, orig_coremask); } @@ -1215,7 +1215,7 @@ setup_lfsr_pattern(node, lmc, 0); errors = test_dram_byte_hw(node, lmc, phys_addr, mode, xor_data); VB_PRT(VBL_DEV2, "%s: LFSR at A:0x%012llx errors 0x%x\n", - __FUNCTION__, phys_addr, errors); + __func__, phys_addr, errors); } else { for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) { pattern_p = byte_patterns[pattern]; @@ -1224,7 +1224,7 @@ errs = test_dram_byte_hw(node, lmc, phys_addr, mode, xor_data); VB_PRT(VBL_DEV2, "%s: PATTERN %d at A:0x%012llx errors 0x%x\n", - __FUNCTION__, pattern, phys_addr, errs); + __func__, pattern, phys_addr, errs); errors |= errs; } /* for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) */ @@ -1270,7 +1270,7 @@ hw_rank_offset = 1ull << (28 + lmcx_config.s.pbank_lsb - lmcx_config.s.rank_ena + (num_lmcs/2)); debug_print("N%d: %s: starting LMC%d with rank offset 0x%lx\n", - node, __FUNCTION__, lmc, hw_rank_offset); + node, __func__, lmc, hw_rank_offset); // start of pattern loop // we do the set of tests for each pattern supplied... diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c index 740de84..e2c6017 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram.c @@ -437,21 +437,21 @@ // so, enable any non-running cores on this node, and leave them // running at the end... ddr_print("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, bdk_get_running_coremask(node)); + node, __func__, bdk_get_running_coremask(node)); bdk_init_cores(node, ~0ULL); // must test for L2C locked here, cannot go on with it unlocked // FIXME: but we only need to worry about Node 0??? if (node == 0) { if (!l2c_is_locked) { // is unlocked, must lock it now - ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __func__); // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_lock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); } // call the tuning routines, no filtering... @@ -464,10 +464,10 @@ // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_unlock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); } // make sure to clear memory and any ECC errs when done... @@ -605,21 +605,21 @@ // so, enable any non-running cores on this node, and leave them // running at the end... ddr_print("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, bdk_get_running_coremask(node)); + node, __func__, bdk_get_running_coremask(node)); bdk_init_cores(node, ~0ULL); // must test for L2C locked here, cannot go on with it unlocked // FIXME: but we only need to worry about Node 0??? if (node == 0) { if (!l2c_is_locked) { // is unlocked, must lock it now - ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __func__); // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_lock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); } debug_print("N%d: Starting DRAM Margin ALL\n", node); @@ -659,10 +659,10 @@ // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_unlock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); } return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5 Gerrit-Change-Number: 42516 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: ACPI: Replace smm_setup_structures()
by Kyösti Mälkki (Code Review) 21 Jun '20

21 Jun '20

Hello build bot (Jenkins), Raul Rangel, David Guckian, Vanessa Eusebio, Angel Pons, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42362 to look at the new patch set (#8). Change subject: ACPI: Replace smm_setup_structures() ...................................................................... ACPI: Replace smm_setup_structures() Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/arch/x86/acpi_s3.c M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/smi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/smi.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 34 files changed, 57 insertions(+), 178 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42362/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/42362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Gerrit-Change-Number: 42362 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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