coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/x86/smm: Use already defined APM_CNT messages
by Kyösti Mälkki (Code Review) 20 Jun '20

20 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42616 ) Change subject: cpu/x86/smm: Use already defined APM_CNT messages ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9635e10dffe2f5fbef7cfbd556c3152dee58ccc Gerrit-Change-Number: 42616 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 20 Jun 2020 21:50:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/google/chromeos/elog.c: Clean up code
by Angel Pons (Code Review) 20 Jun '20

20 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42514 ) Change subject: vc/google/chromeos/elog.c: Clean up code ...................................................................... vc/google/chromeos/elog.c: Clean up code Constify local variables and drop redundant logic, while preserving the original behavior. While we are at it, also reflow print statements. Change-Id: Id024f3ac717dad98c4287add9b33defde7a0028d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/google/chromeos/elog.c 1 file changed, 9 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42514/1 diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 4dd8b19..523b7c4 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -8,32 +8,21 @@ static void elog_add_boot_reason(void *unused) { - int rec = vboot_recovery_mode_enabled(); - int dev = vboot_developer_mode_enabled(); - - if (!rec && !dev) - return; + const int rec = vboot_recovery_mode_enabled(); + const int dev = vboot_developer_mode_enabled(); if (rec) { - u8 reason = vboot_check_recovery_request(); + const u8 reason = vboot_check_recovery_request(); elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE, reason); - printk(BIOS_DEBUG, "%s: Logged recovery mode boot%s, " - "reason: 0x%02x\n", __func__, - dev ? " (Dev-switch on)" : "", reason); + printk(BIOS_DEBUG, "%s: Logged recovery mode boot%s, reason: 0x%02x\n", + __func__, dev ? " (Dev-switch on)" : "", reason); } - if (dev) { - int log_event = 1; + /* Skip logging developer mode in ACPI resume path */ + if (dev && !acpi_is_wakeup()) { - /* Skip logging developer mode in ACPI resume path */ - if (acpi_is_wakeup()) - log_event = 0; - - if (log_event) { - elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); - printk(BIOS_DEBUG, "%s: Logged dev mode boot\n", - __func__); - } + elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); + printk(BIOS_DEBUG, "%s: Logged dev mode boot\n", __func__); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id024f3ac717dad98c4287add9b33defde7a0028d Gerrit-Change-Number: 42514 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Tom Hiller (Code Review) 20 Jun '20

20 Jun '20

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 10: > Patch Set 10: > > > I finally got around to testing this patch. Seems to be working well for the most part. I just want to confirm that the brightness adjustment is still is not functional. Based on the comments, it is waiting on Nitrocaster to release the firmware to possibly find a software workaround for it? Is this correct? > > No. brightness control is working, but there might be some artifacts from the ADC. When changing the brightness in a smooth way it shows you high brightness steps. Hmm. When I use the function keys to change the brightness, the onscreen indicator shows that it is changing but the brightness stays the same. Same when I unplug my laptop, the power settings are supposed to dim the screen. I recompiled using v4.12 and patch v10, in a fresh directory, and flashed a second it again to ensure that didn't miss a step. Here is the deconfig I am using, https://github.com/Thrilleratplay/coreboot-builder-scripts/blob/x230_fhd/x2… and the nitrocast board is a v5 if that makes a difference. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 10 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-Comment-Date: Sat, 20 Jun 2020 20:58:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Alexander Couzens (Code Review) 20 Jun '20

20 Jun '20

Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 10: > I finally got around to testing this patch. Seems to be working well for the most part. I just want to confirm that the brightness adjustment is still is not functional. Based on the comments, it is waiting on Nitrocaster to release the firmware to possibly find a software workaround for it? Is this correct? No. brightness control is working, but there might be some artifacts from the ADC. When changing the brightness in a smooth way it shows you high brightness steps. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 10 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-Comment-Date: Sat, 20 Jun 2020 20:30:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/jecht: hda_verb.c: Correct mic pin configs
by Matt DeVillier (Code Review) 20 Jun '20

20 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42518 ) Change subject: mb/google/jecht: hda_verb.c: Correct mic pin configs ...................................................................... mb/google/jecht: hda_verb.c: Correct mic pin configs Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot guado variant, verify mic attached to 3.5mm jack functional Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/jecht/hda_verb.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/42518/1 diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 170d0a6..3609de9 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -27,15 +27,15 @@ /* Pin Complex (NID 0x17) MONO Out - Disabled */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - /* Pin Complex (NID 0x18) MIC1 PORTB */ + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 // black, jack detect // mic in, analog // connector, left panel - AZALIA_PIN_CFG(0, 0x18, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), -- To view, visit https://review.coreboot.org/c/coreboot/+/42518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f Gerrit-Change-Number: 42518 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/beltino/**/hda_verb.c: Correct mic pin configs
by Matt DeVillier (Code Review) 20 Jun '20

20 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42499 ) Change subject: mb/google/beltino/**/hda_verb.c: Correct mic pin configs ...................................................................... mb/google/beltino/**/hda_verb.c: Correct mic pin configs Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the identifer in the NID comments were flipepd, which was the source of the confusion originally_. Test: build/boot panther and zako variants, verify mic attached to 3.5mm jack functional Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/zako/hda_verb.c 4 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42499/1 diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 878314b..c45b409 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -27,15 +27,15 @@ /* Pin Complex (NID 0x17) MONO Out - Disabled */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - /* Pin Complex (NID 0x18) MIC1 PORTB */ + /* Pin Complex (NID 0x18) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC1 PORTB */ // group 1, cap 1 // black, jack detect // mic in, analog // connector, left panel - AZALIA_PIN_CFG(0, 0x18, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 878314b..c45b409 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -27,15 +27,15 @@ /* Pin Complex (NID 0x17) MONO Out - Disabled */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - /* Pin Complex (NID 0x18) MIC1 PORTB */ + /* Pin Complex (NID 0x18) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC1 PORTB */ // group 1, cap 1 // black, jack detect // mic in, analog // connector, left panel - AZALIA_PIN_CFG(0, 0x18, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 878314b..c45b409 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -27,15 +27,15 @@ /* Pin Complex (NID 0x17) MONO Out - Disabled */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - /* Pin Complex (NID 0x18) MIC1 PORTB */ + /* Pin Complex (NID 0x18) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC1 PORTB */ // group 1, cap 1 // black, jack detect // mic in, analog // connector, left panel - AZALIA_PIN_CFG(0, 0x18, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 878314b..c45b409 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -27,15 +27,15 @@ /* Pin Complex (NID 0x17) MONO Out - Disabled */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - /* Pin Complex (NID 0x18) MIC1 PORTB */ + /* Pin Complex (NID 0x18) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC1 PORTB */ // group 1, cap 1 // black, jack detect // mic in, analog // connector, left panel - AZALIA_PIN_CFG(0, 0x18, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), -- To view, visit https://review.coreboot.org/c/coreboot/+/42499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad Gerrit-Change-Number: 42499 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI: Drop some HAVE_ACPI_RESUME preprocessor use
by Angel Pons (Code Review) 20 Jun '20

20 Jun '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42458 ) Change subject: ACPI: Drop some HAVE_ACPI_RESUME preprocessor use ...................................................................... ACPI: Drop some HAVE_ACPI_RESUME preprocessor use Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/intel/fsp1_1/raminit.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/vendorcode/google/chromeos/elog.c 4 files changed, 1 insertion(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index dfa3258..dd08d77 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -145,12 +145,10 @@ fsp_reserved_bytes); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes)) { -#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ full_reset(); -#endif } /* Save the FSP runtime parameters. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 1d1bd30..5cedf22 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -166,11 +166,9 @@ if (prev_sleep_state != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { - #if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); - #endif } print_dram_info(mp->mainboard.dram_data[0]); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8c194fc..4165c67 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -91,11 +91,9 @@ if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { -#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ system_reset(); -#endif } printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index 14163a5..4dd8b19 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -1,14 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <bootstate.h> #include <console/console.h> #include <elog.h> #include <security/vboot/vboot_common.h> -#if CONFIG(HAVE_ACPI_RESUME) -#include <acpi/acpi.h> -#endif - static void elog_add_boot_reason(void *unused) { int rec = vboot_recovery_mode_enabled(); @@ -28,11 +25,9 @@ if (dev) { int log_event = 1; -#if CONFIG(HAVE_ACPI_RESUME) /* Skip logging developer mode in ACPI resume path */ if (acpi_is_wakeup()) log_event = 0; -#endif if (log_event) { elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); -- To view, visit https://review.coreboot.org/c/coreboot/+/42458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599 Gerrit-Change-Number: 42458 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Tom Hiller (Code Review) 20 Jun '20

20 Jun '20

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 10: > Patch Set 9: > > > U1 acts as a smart translator for EN/PWM signals - whenever EN is high, PWM from the system is translated to the FHD display. Otherwise, EN and PWM are translated high if there's a DC bias on DisplayPort TX lane, which means something is being transmitted to the display. Initially I had an idea that some displays may have PWM brightness regulation, so I also set output PWM frequency to around 1kHz to make it less disgusting. With proper support in the system firmware the adapter board could be completely passive. U1 expects the default 230Hz frequency (or is it 220Hz?), but I believe it should work with 1kHz just as well. > > > > > > With the default assembly, panel power is sourced directly from VCC3M power rail, so you can't control it. By removing F1 and bridging J1 panel power is switched to VCC3P, which is sourced from a load switch on the motherboard, so you can control it. Note that actually moving F1 to J1 isn't necessary because there's already a fuse on the motherboard. > > Thanks for the explanation. Now I understand also the bug which I have with the display. > My lid does not trigger suspend (I configured it this way). So when my lid is closed, the EN line must be low, but the display is on full brightness. I will try to desolder the sense pin. > > @nitrocaster I could imagine the firmware of the STM8 is not much. Do you thought about open sourcing it? I finally got around to testing this patch. Seems to be working well for the most part. I just want to confirm that the brightness adjustment is still is not functional. Based on the comments, it is waiting on Nitrocaster to release the firmware to possibly find a software workaround for it? Is this correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 10 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-Comment-Date: Sat, 20 Jun 2020 20:08:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: rename fch_apic_routing struct to fch_irq_routing
by Felix Held (Code Review) 20 Jun '20

20 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42569 ) Change subject: mb/google/zork: rename fch_apic_routing struct to fch_irq_routing ...................................................................... mb/google/zork: rename fch_apic_routing struct to fch_irq_routing fch_apic_routing is used as name of an array that init_tables() populates with the APIC IRQ routing information. Also the fch_pirq array where fch_apic_routing was used as struct name contains the IRQ mapping for both PIC and APIC mode, so rename it to fch_irq_routing. Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/42569/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index b17c7f8..f87066a 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -70,7 +70,7 @@ * This controls the device -> IRQ routing. * The PIC values are limited to 0,1, 3 - 12, 14, 15. */ -static const struct fch_apic_routing { +static const struct fch_irq_routing { uint8_t intr_index; uint8_t pic_irq_num; uint8_t apic_irq_num; @@ -96,7 +96,7 @@ static void init_tables(void) { - const struct fch_apic_routing *entry; + const struct fch_irq_routing *entry; int i; memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); -- To view, visit https://review.coreboot.org/c/coreboot/+/42569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1 Gerrit-Change-Number: 42569 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: remove redundant IRQ routing configuration
by Felix Held (Code Review) 20 Jun '20

20 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42568 ) Change subject: mb/google/zork: remove redundant IRQ routing configuration ...................................................................... mb/google/zork: remove redundant IRQ routing configuration The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in init_tables(), so the fch_pirq table entries where both IRQ numbers are set to fch_pirq are redundant and can be removed. Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/mainboard.c 1 file changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42568/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index c6b4bdd..b17c7f8 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -79,41 +79,13 @@ { PIRQ_B, 6, 17 }, { PIRQ_C, 14, 18 }, { PIRQ_D, 15, 19 }, - { PIRQ_E, PIRQ_NC, PIRQ_NC }, - { PIRQ_F, PIRQ_NC, PIRQ_NC }, - { PIRQ_G, PIRQ_NC, PIRQ_NC }, - { PIRQ_H, PIRQ_NC, PIRQ_NC }, - { PIRQ_SIRQA, PIRQ_NC, PIRQ_NC }, - { PIRQ_SIRQB, PIRQ_NC, PIRQ_NC }, - { PIRQ_SIRQC, PIRQ_NC, PIRQ_NC }, - { PIRQ_SIRQD, PIRQ_NC, PIRQ_NC }, { PIRQ_SCI, 9, 9 }, - { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, - { PIRQ_ASF, PIRQ_NC, PIRQ_NC }, - { PIRQ_PMON, PIRQ_NC, PIRQ_NC }, - { PIRQ_SD, PIRQ_NC, PIRQ_NC }, - { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, - { PIRQ_CIR, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIOA, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIOB, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIOC, PIRQ_NC, PIRQ_NC }, - { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, { PIRQ_EMMC, 5, 5 }, - { PIRQ_GPP0, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPP1, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPP2, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPP3, PIRQ_NC, PIRQ_NC }, { PIRQ_GPIO, 7, 7 }, - { PIRQ_I2C0, PIRQ_NC, PIRQ_NC }, - { PIRQ_I2C1, PIRQ_NC, PIRQ_NC }, { PIRQ_I2C2, 10, 10 }, { PIRQ_I2C3, 11, 11 }, { PIRQ_UART0, 4, 4 }, { PIRQ_UART1, 3, 3 }, - { PIRQ_I2C4, PIRQ_NC, PIRQ_NC }, - { PIRQ_I2C5, PIRQ_NC, PIRQ_NC }, - { PIRQ_UART2, PIRQ_NC, PIRQ_NC }, - { PIRQ_UART3, PIRQ_NC, PIRQ_NC }, /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/42568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a Gerrit-Change-Number: 42568 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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