coreboot-gerrit June 2020

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Change in coreboot[master]: soc/amd/picasso: don't increment boot count twice
by Aaron Durbin (Code Review) 22 Jun '20

22 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42546 ) Change subject: soc/amd/picasso: don't increment boot count twice ...................................................................... soc/amd/picasso: don't increment boot count twice The FSP-M path increments the boot count already. Therefore, remove the double increment. BUG=b:159359278 Change-Id: I96cabce58d7114f708cad157600f0ccd3aa8a536 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/amd/picasso/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42546/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 83243d3..ce8ab5d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -81,7 +81,6 @@ post_code(0x41); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); - elog_boot_notify(s3_resume); post_code(0x42); u32 val = cpuid_eax(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/42546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96cabce58d7114f708cad157600f0ccd3aa8a536 Gerrit-Change-Number: 42546 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/prodrive/hermes: Disable xDCI
by Patrick Rudolph (Code Review) 22 Jun '20

22 Jun '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42509 ) Change subject: mb/prodrive/hermes: Disable xDCI ...................................................................... mb/prodrive/hermes: Disable xDCI The PCI devices is used for debugging only and as Windows 10 has no default driver for it, disable it to not scare endusers about "missing" drivers. Change-Id: I0b42a9b55f00826c5920c1c259b38382bdcdde72 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/42509/1 diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 45bd422..37f2eb7 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -21,7 +21,7 @@ device pci 08.0 on end # Gaussian Mixture device pci 12.0 on end # Thermal Subsystem device pci 14.0 on end # USB xHCI - device pci 14.1 on end # USB xDCI (OTG) + device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # RAM controller device pci 14.5 off end # SDCard -- To view, visit https://review.coreboot.org/c/coreboot/+/42509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b42a9b55f00826c5920c1c259b38382bdcdde72 Gerrit-Change-Number: 42509 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Finalize PCU configuration
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40386 ) Change subject: soc/intel/xeon_sp/cpx: Finalize PCU configuration ...................................................................... soc/intel/xeon_sp/cpx: Finalize PCU configuration Program PCU (Power Control Unit) during chip_final(). This is needed to allow ACPI power control related feature to work in target OS. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I1f5b18d66b351acecdc7b3f515a552c36f08eb61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40386 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c 4 files changed, 170 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index c2d448c..c3159fe 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -585,6 +585,8 @@ static void chip_final(void *data) { p2sb_hide(); + + set_bios_init_completion(); } static void chip_init(void *data) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index d660d89..71c68cf 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -4,6 +4,7 @@ #define _SOC_PCI_DEVS_H_ #include <device/pci_def.h> +#include <types.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) @@ -23,6 +24,32 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44 +#define PCU_IIO_STACK 1 +#define PCU_DEV 30 +#define PCU_CR1_FUN 1 + +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c + +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x01 + +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12) + +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) + #define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 #define UBOX_DECS_FUNC 2 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 1c3ca66..2d33d0e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -40,4 +40,6 @@ int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); +void set_bios_init_completion(void); + #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 2e183ef..6919fc2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -2,12 +2,16 @@ #include <assert.h> #include <commonlib/sort.h> +#include <delay.h> #include <device/device.h> +#include <device/pci.h> #include <intelblocks/cpulib.h> #include <soc/cpu.h> +#include <soc/pci_devs.h> #include <soc/soc_util.h> #include <stdlib.h> #include <string.h> +#include <timer.h> int get_threads_per_package(void) { @@ -179,3 +183,138 @@ return hob->PlatformData.Pci64BitResourceAllocation; } + +/* return true if command timed out else false */ +static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, + uint32_t target) +{ + const uint32_t max_delay = 5000; /* 5 seconds max */ + const uint32_t step_delay = 50; /* 50 us */ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, max_delay); + while ((pci_s_read_config32(dev, reg) & mask) != target) { + udelay(step_delay); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); + return true; /* timedout */ + } + } + return false; /* successful */ +} + +/* return true if command timed out else false */ +static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) +{ + /* verify bios is not in busy state */ + if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + return true; /* timed out */ + + /* write data to data register */ + printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write the command */ + printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); + pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + command | BIOS_MB_RUN_BUSY_MASK); + + /* wait for completion or time out*/ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); +} + +static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +{ + const IIO_UDS *hob = get_iio_uds(); + + assert(socket < hob->SystemStatus.numCpus && stack < MAX_LOGIC_IIO_STACK); + + return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; +} + +/* return true if command timed out else false */ +static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= val; + + /* update BIOS RESET completion bit */ + pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); + + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); +} + +static void set_bios_init_completion_for_package(uint32_t socket) +{ + uint32_t data; + bool timedout; + const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + /* read PCU config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) { + /* 2nd try */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) + die("BIOS PCU Misc Config Read timed out.\n"); + + /* Since the 1st try failed, we need to make sure PCU is in stable state */ + data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n", + __func__, PCU_CR1_BIOS_MB_DATA_REG, data); + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + if (timedout) + die("BIOS PCU Misc Config Write timed out.\n"); + } + + /* update RST_CPL3, PCODE_INIT_DONE3 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, + PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); + if (timedout) + die("BIOS RESET CPL3 timed out.\n"); + + /* update RST_CPL4, PCODE_INIT_DONE4 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, + PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); + if (timedout) + die("BIOS RESET CPL4 timed out.\n"); + + /* set CSR_DESIRED_CORES_CFG2 lock bit */ + data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); + data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; + printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", + __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); + pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); +} + +void set_bios_init_completion(void) +{ + /* FIXME: This may need to be changed for multi-socket platforms */ + uint32_t sbsp_socket_id = 0; + + /* + * According to the BIOS Writer's Guide, the SBSP must be the last socket + * to receive the BIOS init completion message. So, we send it to all non-SBSP + * sockets first. + */ + for (uint32_t socket = 0; socket < xeon_sp_get_cpu_count(); ++socket) { + if (socket == sbsp_socket_id) + continue; + set_bios_init_completion_for_package(socket); + } + + /* And finally, take care of the SBSP */ + set_bios_init_completion_for_package(sbsp_socket_id); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f5b18d66b351acecdc7b3f515a552c36f08eb61 Gerrit-Change-Number: 40386 Gerrit-PatchSet: 30 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: UPTREAM: mb/google/volteer: Fix VCM and EEPROM configs for ov8856 wor...
by Daniel Kang (Code Review) 22 Jun '20

22 Jun '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42048 ) Change subject: UPTREAM: mb/google/volteer: Fix VCM and EEPROM configs for ov8856 world-facing camera ...................................................................... UPTREAM: mb/google/volteer: Fix VCM and EEPROM configs for ov8856 world-facing camera Volteer proto 2 camera module's VCM and EEPROM configs. BUG=b:148428976 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: I792608f86a59b16545dfa4edf6508de7a444bb26 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42048/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 777ab7a..a5756626 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -331,8 +331,8 @@ Device (VCM0) { Name (_HID, "PRP0001") /* _HID: Hardware ID */ - Name (_UID, 0x03) /* _UID: Unique ID */ - Name (_DDN, "GT9769 VCM") /* _DDN: DOS Device Name */ + Name (_UID, 0x00) /* _UID: Unique ID */ + Name (_DDN, "DW9768 VCM") /* _DDN: DOS Device Name */ Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) @@ -364,7 +364,7 @@ Package (0x02) { "compatible", - "giantec,gt9769-vcm" + "dongwoon,dw9768" } } }) @@ -372,8 +372,8 @@ Device (NVM0) { Name (_HID, "PRP0001") // _HID: Hardware ID - Name (_UID, 0x03) // _UID: Unique ID - Name (_DDN, "GT9769 EEPROM") // _DDN: DOS Device Name + Name (_UID, 0x01) // _UID: Unique ID + Name (_DDN, "AT24 EEPROM") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) @@ -425,7 +425,7 @@ Package (0x02) { "compatible", - "giantec,gt9769-eeprom" + "atmel,24c1024" } } }) -- To view, visit https://review.coreboot.org/c/coreboot/+/42048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792608f86a59b16545dfa4edf6508de7a444bb26 Gerrit-Change-Number: 42048 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax
by V Sowmya (Code Review) 22 Jun '20

22 Jun '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42506 ) Change subject: soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax ...................................................................... soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax This change updates platform.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for volteer. Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/tigerlake/acpi/platform.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42506/1 diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl index 7345864..4b01aeb 100644 --- a/src/soc/intel/tigerlake/acpi/platform.asl +++ b/src/soc/intel/tigerlake/acpi/platform.asl @@ -16,5 +16,5 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/42506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a Gerrit-Change-Number: 42506 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/amd/picasso: Enable IDT in all stages
by Furquan Shaikh (Code Review) 22 Jun '20

22 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42500 ) Change subject: soc/amd/picasso: Enable IDT in all stages ...................................................................... soc/amd/picasso: Enable IDT in all stages This change selects IDT_IN_EVERY_STAGE so that the interrupt handlers are provided for all stages. Change-Id: I25ced7758264fb14998ab5f31ff778c1af11eb05 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42500/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..9630ad3 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -19,6 +19,7 @@ select ACPI_AMD_HARDWARE_SLEEP_VALUES select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB + select IDT_IN_EVERY_STAGE select IOAPIC select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/42500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25ced7758264fb14998ab5f31ff778c1af11eb05 Gerrit-Change-Number: 42500 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/dedede: Fix the USB ACPI configuration
by Karthik Ramasubramanian (Code Review) 22 Jun '20

22 Jun '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42554 ) Change subject: mb/google/dedede: Fix the USB ACPI configuration ...................................................................... mb/google/dedede: Fix the USB ACPI configuration Only waddledee and waddledoo route discrete and integrated BT signals to different USB ports. In all the other variant boards, discrete and integrated BT signals are routed to the same USB port (port 8 - index 7). Fix the USB ACPI configuration. Also device configuration in override tree are applied only if there is a matching device in base devicetree. So configure all the USB devices in base devicetree and turn them off. BUG=b:154064148 TEST=Ensure that the SSDT contains the ACPI objects for enabled USB devices. Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/waddledee/overridetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 38 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42554/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 8b68beb..7fdf438 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -187,13 +187,16 @@ device usb 2.3 on end end chip drivers/usb/acpi - register "desc" = ""Discrete Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" - device usb 2.4 on end + device usb 2.4 off end end chip drivers/usb/acpi - register "desc" = ""Integrated Bluetooth"" + device usb 2.5 off end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" device usb 2.7 on end diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb index ee1abc9..33c578c 100644 --- a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -37,6 +37,24 @@ }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Discrete Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index b8be926..2936cdd 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -54,10 +54,22 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""Discrete Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.4 on end + end + chip drivers/usb/acpi register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.5 on end end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end end end end # USB xHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/42554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b8bf7f4db1d2661f310bf4874428a6d1de222c6 Gerrit-Change-Number: 42554 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Constify struct southbridge_intel_i82801gx_config
by HAOUAS Elyes (Code Review) 22 Jun '20

22 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40773 ) Change subject: sb/intel/i82801gx: Constify struct southbridge_intel_i82801gx_config ...................................................................... sb/intel/i82801gx: Constify struct southbridge_intel_i82801gx_config Change-Id: Ia5af84782d41a007be04c3dccc291b788ddfddfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c 5 files changed, 8 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/40773/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 4a2b50e..f8bce44 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -16,8 +16,6 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -typedef struct southbridge_intel_i82801gx_config config_t; - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index b6b30ef..708821b 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -9,8 +9,6 @@ #include "chip.h" #include "i82801gx.h" -typedef struct southbridge_intel_i82801gx_config config_t; - static void ide_init(struct device *dev) { u16 ideTimingConfig; @@ -18,7 +16,7 @@ u32 enable_primary, enable_secondary; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; printk(BIOS_DEBUG, "i82801gx_ide: initializing..."); if (config == NULL) { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c24460c..a23a996 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -28,8 +28,6 @@ #define NMI_OFF 0 -typedef struct southbridge_intel_i82801gx_config config_t; - /** * Set miscellaneous static southbridge features. * @@ -80,7 +78,7 @@ { struct device *irq_dev; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); @@ -125,7 +123,7 @@ static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; u32 reg32 = 0; /* An array would be much nicer here, or some other method of doing this. */ @@ -156,7 +154,7 @@ u32 reg32; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -432,7 +430,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { struct device *dev = pcidev_on_root(0x1f, 0); - config_t *chip = dev->chip_info; + const struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4398ad5..cf1688a 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -169,7 +169,7 @@ int coalesce = 0; if (dev->chip_info != NULL) { - struct southbridge_intel_i82801gx_config *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; coalesce = config->pcie_port_coalesce; } diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 4b4511c..9252ed1 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -10,8 +10,6 @@ #include "i82801gx.h" #include "sata.h" -typedef struct southbridge_intel_i82801gx_config config_t; - static u8 get_ich7_sata_ports(void) { struct device *lpc; @@ -36,7 +34,7 @@ void sata_enable(struct device *dev) { /* Get the chip configuration */ - struct southbridge_intel_i82801gx_config *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; if (config->sata_mode == SATA_MODE_AHCI) { /* Check if the southbridge supports AHCI */ @@ -78,7 +76,7 @@ u8 ports; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_i82801gx_config *config = dev->chip_info; printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/40773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5af84782d41a007be04c3dccc291b788ddfddfd Gerrit-Change-Number: 40773 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [WIP] device/smbus_host: Declare common early SMBUS prototypes
by Kyösti Mälkki (Code Review) 22 Jun '20

22 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38233 ) Change subject: [WIP] device/smbus_host: Declare common early SMBUS prototypes ...................................................................... [WIP] device/smbus_host: Declare common early SMBUS prototypes Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/smbus.h M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 27 files changed, 39 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38233/1 diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index cae4f3f..5782d5e 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -29,6 +29,7 @@ struct bus *get_pbus_smbus(struct device *dev); +#if !DEVTREE_EARLY static inline int smbus_recv_byte(struct device *const dev) { return i2c_dev_readb(dev); @@ -51,5 +52,6 @@ int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); +#endif #endif /* DEVICE_SMBUS_H */ diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 4d67e18..0236c5c 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -51,4 +51,36 @@ printk(BIOS_DEBUG, "SMBus controller enabled\n"); } +#if DEVTREE_EARLY +static inline int smbus_read_byte(u8 device, u8 address) +{ + uintptr_t base = smbus_base(); + return do_smbus_read_byte(base, device, address); +} + +static inline int smbus_write_byte(u8 device, u8 address, u8 data) +{ + uintptr_t base = smbus_base(); + return do_smbus_write_byte(base, device, address, data); +} + +static inline int smbus_block_read(u8 device, u8 cmd, size_t max_bytes, u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_smbus_block_read(base, device, cmd, max_bytes, buf); +} + +static inline int smbus_block_write(u8 device, u8 cmd, size_t bytes, const u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_smbus_block_write(base, device, cmd, bytes, buf); +} + +static inline int i2c_eeprom_read(u8 device, u8 offset, size_t bytes, u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_i2c_eeprom_read(base, device, offset, bytes, buf); +} +#endif + #endif diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index ebbcc15..c647f96 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,7 +20,6 @@ #include <device/smbus_host.h> #include <arch/romstage.h> -#include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index b885f86..5fed7c5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index bbf53bc..4e5c355 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 8ec579c..971255a4 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7bab957..e5f511d 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -19,8 +19,8 @@ #include <stdint.h> #include <arch/io.h> #include <ec/acpi/ec.h> +#include <device/smbus_host.h> -#include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 2acbc57..6361a58 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -17,6 +17,7 @@ #include <spd.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <console/console.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f0ea142..b6d9e6f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -18,6 +18,7 @@ #include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 215e9b8..42e6ebe 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cpu/x86/msr.h> #include <cbmem.h> #include <cf9_reset.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index df2d31e..0809998 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -15,17 +15,13 @@ */ #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ -#else -#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ -#endif #include <spd.h> #include <string.h> #include <device/dram/ddr2.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 91f1bc3..7fa6f88 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -45,8 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5348478..67dbf69 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,10 +64,6 @@ void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 99fe128..1775706 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -52,8 +52,3 @@ return 0; } - -int smbus_read_byte(u8 device, u8 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index ea7efef..9076829 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,10 +21,6 @@ void enable_pm(void); -#if ENV_ROMSTAGE -int smbus_read_byte(u8 device, u8 address); -#endif - #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6e1f1f7..51110c4 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -37,8 +37,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 9895de1..06f0f57 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -32,10 +32,8 @@ #if !defined(__ASSEMBLER__) #include <device/device.h> -#include "chip.h" void i82801dx_enable(struct device *dev); -int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index b89e57d..54aaa4f 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -45,24 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 688f1c3..7c326a7 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,15 +41,7 @@ void i82801gx_setup_bars(void); void i82801gx_early_init(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); void ich7_setup_cir(void); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 60f49d2..f6ce713 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -47,8 +47,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index f60aad3..667bd50 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -213,10 +213,6 @@ void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - #endif #endif diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 8e3329c..18a61b7 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -42,24 +42,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index abf6187..2372014 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -225,14 +225,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); -#endif void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 52d483d..7fa6f88 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -45,23 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 424bf42..8ac506d 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -54,13 +54,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int smbus_write_byte(unsigned int device, unsigned int address, u8 data); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -#endif - void early_pch_init(void); void early_thermal_init(void); diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 91f1bc3..7fa6f88 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -45,8 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9622c67..b6bf00b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,11 +174,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); - -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/38233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Gerrit-Change-Number: 38233 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/x86/lapic: Cleanup code
by Patrick Rudolph (Code Review) 22 Jun '20

22 Jun '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36777 ) Change subject: cpu/x86/lapic: Cleanup code ...................................................................... cpu/x86/lapic: Cleanup code * Don't use long as it compiles to 64bit on x86_64, which breaks interrupts in qemu and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on Qemu Q35 with x86_64 enabled: Interrupts working again. Tested on Qemu Q35 with x86_32 enabled: Interrupts are still working. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 3 files changed, 18 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36777/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 755fbe2..6eb72f9 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -58,6 +58,6 @@ LAPIC_DELIVERY_MODE_NMI) ); - printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid()); + printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid()); printk(BIOS_INFO, "done.\n"); } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e7dfc57..1e5c96a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -101,7 +101,7 @@ static int lapic_start_cpu(unsigned long apicid) { int timeout; - unsigned long send_status, accept_status; + uint32_t send_status, accept_status; int j, maxlvt; /* @@ -133,11 +133,11 @@ printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " "Disabling\n", apicid); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } return 0; @@ -230,7 +230,7 @@ if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) - printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + printk(BIOS_WARNING, "APIC delivery error (%x).\n", accept_status); if (send_status || accept_status) return 0; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6fd1997..8800ad2 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -6,14 +6,14 @@ #include <halt.h> #include <smp/node.h> -static __always_inline unsigned long lapic_read(unsigned long reg) +static __always_inline uint32_t lapic_read(unsigned long reg) { - return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); + return *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)); } -static __always_inline void lapic_write(unsigned long reg, unsigned long v) +static __always_inline void lapic_write(unsigned long reg, uint32_t v) { - *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; + *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)) = v; } static __always_inline void lapic_wait_icr_idle(void) @@ -40,7 +40,7 @@ wrmsr(LAPIC_BASE_MSR, msr); } -static __always_inline unsigned long lapicid(void) +static __always_inline uint32_t lapicid(void) { return lapic_read(LAPIC_ID) >> 24; } @@ -58,58 +58,19 @@ void stop_this_cpu(void); #endif -#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ - sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* - * Note: no "lock" prefix even on SMP: xchg always implies lock anyway - * Note 2: xchg has side effect, so that attribute volatile is necessary, - * but generally the primitive is invalid, *ptr is output argument. --ANK - */ -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) +static inline void lapic_write_atomic(unsigned long reg, volatile uint32_t v) { - switch (size) { - case 1: - __asm__ __volatile__("xchgb %b0,%1" - : "=q" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 2: - __asm__ __volatile__("xchgw %w0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 4: - __asm__ __volatile__("xchgl %0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - } - return x; + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg); + + asm volatile ("xchgl %0, %1\n" + : "+r" (v), "+m" (*(ptr)) + : : "memory", "cc"); } -static inline void lapic_write_atomic(unsigned long reg, unsigned long v) -{ - (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); -} - - -#ifdef X86_GOOD_APIC -# define FORCE_READ_AROUND_WRITE 0 -# define lapic_read_around(x) lapic_read(x) -# define lapic_write_around(x, y) lapic_write((x), (y)) -#else -# define FORCE_READ_AROUND_WRITE 1 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -#endif void do_lapic_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Gerrit-Change-Number: 36777 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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