Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42361 )
Change subject: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42361/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/42361/5//COMMIT_MSG@9
PS5, Line 9: These are the simple cbmem_find() cases.
> Maybe mention this as well: […]
Done
https://review.coreboot.org/c/coreboot/+/42361/2/src/acpi/gnvs.c
File src/acpi/gnvs.c:
PS2:
> I find the mixed usage of `gnvs` and `!gnvs` in conditions rather confusing. […]
Done
https://review.coreboot.org/c/coreboot/+/42361/3/src/include/cbmem.h
File src/include/cbmem.h:
https://review.coreboot.org/c/coreboot/+/42361/3/src/include/cbmem.h@11
PS3, Line 11: /* FIXME: Lots of includes to fix. */
: void *acpi_get_gnvs(void);
> Probably there yes, and do not resolve this comment until fixed. […]
Done
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Gerrit-Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42361
to look at the new patch set (#7).
Change subject: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
......................................................................
ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
These are the simple cbmem_find() cases. Also drop the redundant
error messages.
Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/google/kahlee/mainboard.c
M src/mainboard/google/zork/mainboard.c
M src/soc/amd/picasso/southbridge.c
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/scc.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/scc.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/common/acpi_wake_source.c
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/nhlt.c
M src/southbridge/intel/lynxpoint/acpi.c
M src/southbridge/intel/lynxpoint/serialio.c
18 files changed, 47 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/42361/7
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42426
to look at the new patch set (#5).
Change subject: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
......................................................................
sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
The smm_setup_structures() calls placed GNVS address into
register %ebx. Old code on i82801dx used these low memory
addresses.
Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/southbridge/intel/i82801gx/smihandler.c
M src/southbridge/intel/i82801ix/smihandler.c
M src/southbridge/intel/i82801jx/smihandler.c
3 files changed, 11 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42426/5
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Gerrit-MessageType: newpatchset
Patrick Georgi has uploaded a new patch set (#21) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
soc/intel/denverton_ns: Implement PCIe post config + lock
- Configure PCIe maximum payload size to fix Intel SSD
- Lock Down PCIe Configuration
Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/21
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Gerrit-MessageType: newpatchset
Patrick Georgi has uploaded a new patch set (#20) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25441 )
Change subject: soc/intel/denverton_ns: Lock SPIBAR
......................................................................
soc/intel/denverton_ns: Lock SPIBAR
- Allow flash access when "Security Override" is set.
- Don't lock when relax_security is set.
Change-Id: I6934918d0c70245f03a1642f9a05e0110a205bc9
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/common/block/fast_spi/fast_spi_def.h
M src/soc/intel/denverton_ns/lpc.c
2 files changed, 57 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25441/20
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Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 )
Change subject: drivers/intel/mipi_camera: Add camera power resource to SSDT
......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41624/23//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/41624/23//COMMIT_MSG@7
PS23, Line 7: drivers/intel/mipi_camera: SSDT add camera power resource
> Mayeb: […]
Done
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