coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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2826 discussions

Change in coreboot[master]: mb/google/volteer: Enable HECI interface
by Jamie Ryu (Code Review) 23 Jun '20

23 Jun '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Rizwan Qureshi, Paul Menzel, Angel Pons, Sridhar Siricilla, Patrick Rudolph, V Sowmya, Nick Vaccaro, Duncan Laurie, Raj Astekar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42308 to look at the new patch set (#4). Change subject: mb/google/volteer: Enable HECI interface ...................................................................... mb/google/volteer: Enable HECI interface This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. BUG=b:159615125 TEST=Build and boot volteer. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42308/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/42308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Gerrit-Change-Number: 42308 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbmem: Remove IDs for TSEG and BERT
by Marshall Dawson (Code Review) 23 Jun '20

23 Jun '20

Hello Raul Rangel, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42532 to review the following change. Change subject: cbmem: Remove IDs for TSEG and BERT ...................................................................... cbmem: Remove IDs for TSEG and BERT Remove the changes added in 80df052d3 cbmem: Add IDs for TSEG and BERT table data No platform uses either ID. TSEG in cbmem is incompatible with stage cache. BERT reserved data in cbmem is unusable in Linux. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6 --- M src/commonlib/include/commonlib/cbmem_id.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42532/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 65973c3..ac271a0 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -46,8 +46,6 @@ #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_SMBIOS 0x534d4254 -#define CBMEM_ID_BERT_RAW_DATA 0x42455254 -#define CBMEM_ID_SMM_TSEG_SPACE 0x54534547 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 @@ -113,8 +111,6 @@ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ { CBMEM_ID_SMBIOS, "SMBIOS " }, \ - { CBMEM_ID_BERT_RAW_DATA, "BERT DATA " }, \ - { CBMEM_ID_SMM_TSEG_SPACE, "TSEG " }, \ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/42532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6 Gerrit-Change-Number: 42532 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Set BERT_SIZE to 0 when no table generated
by Marshall Dawson (Code Review) 23 Jun '20

23 Jun '20

Hello Raul Rangel, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42531 to review the following change. Change subject: soc/amd/picasso: Set BERT_SIZE to 0 when no table generated ...................................................................... soc/amd/picasso: Set BERT_SIZE to 0 when no table generated BUG=b:136987699 TEST=Verify no region reserved when CONFIG_ACPI_BERT=n Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6 --- M src/soc/amd/picasso/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42531/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..40e3c90 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -331,7 +331,8 @@ config ACPI_BERT_SIZE hex - default 0x4000 + default 0x4000 if ACPI_BERT + default 0x0 help Specify the amount of DRAM reserved for gathering the data used to generate the ACPI table. -- To view, visit https://review.coreboot.org/c/coreboot/+/42531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6 Gerrit-Change-Number: 42531 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Convert BERT reserved region from cbmem
by Marshall Dawson (Code Review) 23 Jun '20

23 Jun '20

Hello Raul Rangel, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42530 to review the following change. Change subject: soc/amd/picasso: Convert BERT reserved region from cbmem ...................................................................... soc/amd/picasso: Convert BERT reserved region from cbmem Picasso's BERT region should not have been moved to cbmem in commit 901cb9c "soc/amd/picasso: Move BERT region to cbmem". This causes an error of "APEI: Can not request [] for APEI BERT registers. FSP has been modified to set aside a requested region size for BERT, simiar to TSEG. Remove the cbmem reservation and locate the region by searching for the HOB. BUG=b:136987699 TEST=Check that BERT is allocated Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb --- M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/romstage.c 3 files changed, 21 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42530/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index cea1c51..69363f5 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -193,31 +193,3 @@ for (i = 0 ; i < num_banks ; i++) wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } - -void bert_reserved_region(void **start, size_t *size) -{ - const struct cbmem_entry *bert; - - *start = NULL; - *size = 0; - - bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); - if (!bert) - return; - - *start = cbmem_entry_start(bert); - *size = cbmem_entry_size(bert); -} - -static void alloc_bert_in_cbmem(int unused) -{ - void *p; - - if (CONFIG(ACPI_BERT)) { - p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE); - if (!p) - printk(BIOS_ERR, "Error: BERT region was not added\n"); - } -} - -ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem) diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 42a3307..74a6c70 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/amd/msr.h> +#include <arch/bert_storage.h> #include <memrange.h> #include <fsp/util.h> #include <FspGuids.h> @@ -60,6 +61,25 @@ } } +void bert_reserved_region(void **start, size_t *size) +{ + struct range_entry bert; + int status; + + *start = NULL; + *size = 0; + + status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b); + + if (status < 0) { + printk(BIOS_ERR, "Error: unable to find BERT HOB\n"); + return; + } + + *start = (void *)(uintptr_t)range_entry_base(&bert); + *size = range_entry_size(&bert); +} + void memmap_stash_early_dram_usage(void) { struct memmap_early_dram *e; diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 83243d3..60a1b04 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -32,6 +32,7 @@ mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/42530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb Gerrit-Change-Number: 42530 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: early audio subsystem selection
by Caveh Jalali (Code Review) 22 Jun '20

22 Jun '20

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41166 ) Change subject: mb/google/volteer: early audio subsystem selection ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/41166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87e83325d2d0f57edf315e253b56bb881cf4ed18 Gerrit-Change-Number: 41166 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Julius Werner (Code Review) 22 Jun '20

22 Jun '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 5: CPPFLAGS_verstage += -I$(src)/soc/amd/picasso/psp_verstage/include > Exactly, and the same for io.h. […] Why are you replacing arch/mmio.h at all? Looks like your versions aren't doing anything fundamentally different, they're just removing the dmb()s and the __builtin_assume_aligned(). The dmb()s are there so that programmers don't need to explicitly put memory barriers in their hardware access code (this roughly matches Linux behavior of readl()/writel() type functions). While that could be done differently (I've thought about this a couple of times but never enough to do anything) to save some instructions where this isn't necessary, that would be something that should be done at the whole architecture level, not one individual SoC (e.g. we'd probably introduce separate write8_relaxed() calls like Linux has them for people who explicitly know they don't need barriers). Right now the global assumption is that MMIO accessors are implicitly ordered against each other and SoCs shouldn't individually break that. The __builtin_assume_aligned() was there because some specific compiler version would otherwise sometimes generate LDRB instead of LDR instructions in certain specific inlining edge cases. This just fixes that rare bug, but in most cases it has no effect. (I don't think you should rely on include order magic if possible, so at least getting rid of arch/mmio.h would be good. arch/io.h doesn't seem as bad because at least there's no other version of that under arch/arm, although an SoC providing an arch/ header is still kinda weird.) -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 7 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Jun 2020 20:34:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 22 Jun '20

22 Jun '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/memlay… File src/soc/amd/picasso/memlayout.ld: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/memlay… PS7, Line 3: #if ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) > I had done it based on ENV_X86/ENV_ARM here: https://chromium.googlesource. […] Sounds good. I definitely like that option better. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 5: CPPFLAGS_verstage += -I$(src)/soc/amd/picasso/psp_verstage/include > Are there now two candidates for <arch/mmio. […] Exactly, and the same for io.h. The other way I saw to do this cleanly was to put them in the ARMv7 code, which didn't seem to make sense since it's only used in the one place. This is safe (until the makefiles gets refactored) as the other include path gets added to verstage-generic-ccopts which gets evaluated after CPPFLAGS_verstage by create_cc_template in the top level Makefile. $(CC_$(1)) \ -MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \ $(3) -c -o $$$$@ $$$$< verstage-generic-ccopts is the '$(3)' here. I'll add a comment as to why this is getting added to CPPFLAGS_verstage instead of verstage-generic-ccopts. The other 2 include paths can be added to whichever, so I just added them to the same variable, but could switch them if that's the preference. -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 7 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Jun 2020 18:59:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Enable HECI interface
by Tim Wawrzynczak (Code Review) 22 Jun '20

22 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42308 ) Change subject: mb/google/volteer: Enable HECI interface ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/42308/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42308/3//COMMIT_MSG@9 PS3, Line 9: by can you mention HECI #1 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/42308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Gerrit-Change-Number: 42308 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jun 2020 18:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Add framework for GNVS initialisation
by Kyösti Mälkki (Code Review) 22 Jun '20

22 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42423 ) Change subject: ACPI: Add framework for GNVS initialisation ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c File src/acpi/chromeos-gnvs.c: https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c@14 PS5, Line 14: gnvs_chromeos->vbt2 = ACTIVE_ECFW_RO; > Why not just put this inside chromeos_init_chromeos_acpi()? I do not want to span under vendorcode/ with my change. https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/gnvs.c File src/acpi/gnvs.c: https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/gnvs.c@55 PS5, Line 55: gnvs_assign_chromeos(); > Briefly looking it's just assigning to fields. I don't see any side effects. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Gerrit-Change-Number: 42423 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Jun 2020 18:36:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
by Nico Huber (Code Review) 22 Jun '20

22 Jun '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42361 ) Change subject: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Gerrit-Change-Number: 42361 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Jun 2020 18:21:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2020