coreboot-gerrit June 2020

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Change in coreboot[master]: TEST Volteer : To fine tune Touchpad I2C CLK
by Mice Lin (Code Review) 23 Jun '20

23 Jun '20

Mice Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42501 ) Change subject: TEST Volteer : To fine tune Touchpad I2C CLK ...................................................................... TEST Volteer : To fine tune Touchpad I2C CLK The I2C CLK be measured = 389 KHz. BUG=b:157999726 TEST=To measure the I2C CLK accordingly. Change-Id: Icafbca53c1c9813a2ae7450cb490c7f0686f4586 Signed-off-by: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42501/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 9e5ef4b..3a54d5d 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -1,4 +1,16 @@ chip soc/intel/tigerlake + register "common_soc_config" = "{ + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/42501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icafbca53c1c9813a2ae7450cb490c7f0686f4586 Gerrit-Change-Number: 42501 Gerrit-PatchSet: 1 Gerrit-Owner: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Clean up SMM_ASEG
by Patrick Rudolph (Code Review) 23 Jun '20

23 Jun '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42372 ) Change subject: cpu/x86/smm: Clean up SMM_ASEG ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/42372/1/src/cpu/x86/smm/aseg_regio… File src/cpu/x86/smm/aseg_region.c: https://review.coreboot.org/c/coreboot/+/42372/1/src/cpu/x86/smm/aseg_regio… PS1, Line 19: 0x20000 Use a define for that? -- To view, visit https://review.coreboot.org/c/coreboot/+/42372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I519c242aa3b837f3e09fd34dee5aa4a2dc3c97ba Gerrit-Change-Number: 42372 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Jun 2020 06:01:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Add FSP_M_FILE and FSP_S_FILE selection to Kconfig
by Furquan Shaikh (Code Review) 23 Jun '20

23 Jun '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42337 ) Change subject: mb/google/zork: Add FSP_M_FILE and FSP_S_FILE selection to Kconfig ...................................................................... mb/google/zork: Add FSP_M_FILE and FSP_S_FILE selection to Kconfig This change adds FSP_M_FILE and FSP_S_FILE selection to Kconfig dependent on ADD_FSP_BINARIES. This relieves each variant from setting this config separately in config.${VARIANT} in chromiumos-overlay in chromium tree. Change-Id: Ib1db5e1a53afb9eb2d2bf200f8e806160014e06c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42337/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index ab24213..442d569 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -136,4 +136,14 @@ help Which board version did FW_CONFIG become valid in CBI. +config FSP_M_FILE + string + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" + +config FSP_S_FILE + string + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" + endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ -- To view, visit https://review.coreboot.org/c/coreboot/+/42337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1db5e1a53afb9eb2d2bf200f8e806160014e06c Gerrit-Change-Number: 42337 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
by Edward O'Callaghan (Code Review) 23 Jun '20

23 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42676 ) Change subject: util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports ...................................................................... util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports Switch USB2 port1 and port3 due to circuit change from rev0. BUG=b:154071868,b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/mainboard/google/puff/template/overridetree.cb 1 file changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/42676/1 diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index ededac4..55ce5ea 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -21,9 +21,6 @@ }" # USB configuration - # NOTE: This only applies to Puff, - # usb2_ports[1] and usb2_ports[3] were swapped on - # reference schematics after Puff has been built. register "usb2_ports[0]" = "{ .enable = 1, .ocpin = OC2, @@ -32,7 +29,14 @@ .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -41,14 +45,7 @@ .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 3 - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port register "usb2_ports[4]" = "{ .enable = 1, .ocpin = OC_SKIP, -- To view, visit https://review.coreboot.org/c/coreboot/+/42676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166 Gerrit-Change-Number: 42676 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/mb/google/tmpl/puff: Import overridetree.cb copy
by Edward O'Callaghan (Code Review) 23 Jun '20

23 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42675 ) Change subject: util/mb/google/tmpl/puff: Import overridetree.cb copy ...................................................................... util/mb/google/tmpl/puff: Import overridetree.cb copy BUG=b:154071868 BRANCH=none TEST=none Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/mainboard/google/puff/template/overridetree.cb 1 file changed, 400 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/42675/1 diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index abbcaaa..ededac4 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -1,6 +1,406 @@ chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" + + # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # USB configuration + # NOTE: This only applies to Puff, + # usb2_ports[1] and usb2_ports[3] were swapped on + # reference schematics after Puff has been built. + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 3 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port 4 + register "usb2_ports[5]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A port 0 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkDmic0" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 60, + }, + }" + + # PCIe port 7 for LAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # Uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "6" + register "PcieClkSrcClkReq[0]" = "0" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # SATA port 1 Gen3 Strength + # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB + register "sata_port[1].TxGen3DeEmphEnable" = "1" + register "sata_port[1].TxGen3DeEmph" = "0x20" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""1AF80175"" + register "name" = ""PS17"" + register "desc" = ""Parade PS175"" + device i2c 4a on end + end + end # I2C #2, PCON PS175. + device pci 15.3 on + chip drivers/i2c/generic + register "hid" = ""10EC2142"" + register "name" = ""RTD2"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end + end + end # I2C #3, Realtek RTD2142. + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1c.6 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111H Ethernet NIC + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1e.3 off end # GSPI #1 end + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1004, + .dc_loadline = 1004, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 181, + .dc_loadline = 181, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 319, + .dc_loadline = 319, + }" + end -- To view, visit https://review.coreboot.org/c/coreboot/+/42675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1 Gerrit-Change-Number: 42675 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: palkia: separate the gpio pins control for the second touch
by Zhuohao Lee (Code Review) 23 Jun '20

23 Jun '20

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42185 ) Change subject: palkia: separate the gpio pins control for the second touch ...................................................................... palkia: separate the gpio pins control for the second touch We use the different gpio pins to control the second touch, so we need to modify the devicetree to adopt this change. With this change, we can control the primary touch controller and secondary touch controller respectively. BUG=b:149714955 TEST=touch works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/hatch/variants/palkia/gpio.c M src/mainboard/google/hatch/variants/palkia/overridetree.cb 2 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/42185/1 diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 04f1d85..ff02b25 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -45,6 +45,10 @@ /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), + /* D4 : USI_BASE_REPORT_EN */ + PAD_CFG_GPO(GPP_D4, 0, DEEP), + /* D10 : GPP_D10 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), /* D16 : USI_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 31017bc..7de423b 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -76,7 +76,7 @@ device usb 2.5 off end end chip drivers/usb/acpi - # No Right Tpype-C port + # No Right Type-C port device usb 3.1 off end end chip drivers/usb/acpi @@ -136,12 +136,12 @@ "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D10)" register "generic.enable_delay_ms" = "12" register "generic.enable_off_delay_ms" = "10" register "generic.has_power_resource" = "1" register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" register "generic.stop_delay_ms" = "15" register "generic.stop_off_delay_ms" = "5" register "hid_desc_reg_offset" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/42185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Gerrit-Change-Number: 42185 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[4.11_branch]: mb/facebook/watson: support firmware version
by Jonathan Zhang (Code Review) 23 Jun '20

23 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42022 ) Change subject: mb/facebook/watson: support firmware version ...................................................................... mb/facebook/watson: support firmware version SMBIOS type 0 has a field for overall firmware version. This version is the semantic version of the entire host firmware, with coreboot being part of it. In build/release process, overall firmware version is expected to be updated into version variable in VPD_RO flash region. If "version" key is found in VPD_RO flash region, use its value to fill in SMBIOS type 0. Otherwise, generate a BIOS_ERR message, concatenate "cb_ver:" and coreboot_version to fill in SMBIOS type 0. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I831fe7019ddd75beb6824b8e09445f339bf7cc8d --- M src/mainboard/facebook/watson/Makefile.inc A src/mainboard/facebook/watson/ramstage.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42022/1 diff --git a/src/mainboard/facebook/watson/Makefile.inc b/src/mainboard/facebook/watson/Makefile.inc index f1384f7..17a5918 100644 --- a/src/mainboard/facebook/watson/Makefile.inc +++ b/src/mainboard/facebook/watson/Makefile.inc @@ -14,5 +14,6 @@ ## ramstage-y += irqroute.c +ramstage-y += ramstage.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/facebook/watson/ramstage.c b/src/mainboard/facebook/watson/ramstage.c new file mode 100644 index 0000000..f844d03 --- /dev/null +++ b/src/mainboard/facebook/watson/ramstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <smbios.h> +#include <version.h> +#include <string.h> + +#define VER_LEN 20 + +/* + * If "version" key is found in VPD_RO, use its value as overall + * firmware version; otherwise use coreboot_version as overall + * firmware version. + */ +const char *smbios_mainboard_bios_version(void) +{ + static char version[VER_LEN] = {0}; + + if (vpd_gets("version", version, VER_LEN, VPD_RO)) { + printk(BIOS_DEBUG, "Got version from VPD: %s\n", version); + } else { + static char cb_ver[] = "cb_ver:"; + strcpy(version, cb_ver); + strncpy(version + strlen(cb_ver), coreboot_version, + VER_LEN - strlen(cb_ver) - 1); + printk(BIOS_ERR, "Unable to get version from VPD, use %s\n", version); + } + return version; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I831fe7019ddd75beb6824b8e09445f339bf7cc8d Gerrit-Change-Number: 42022 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: util/mb/google/tmpl/puff: Generate correct gpio muxing
by Edward O'Callaghan (Code Review) 23 Jun '20

23 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42674 ) Change subject: util/mb/google/tmpl/puff: Generate correct gpio muxing ...................................................................... util/mb/google/tmpl/puff: Generate correct gpio muxing BUG=b:154071868 BRANCH=none TEST=none Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/mainboard/google/puff/template/Makefile.inc A util/mainboard/google/puff/template/gpio.c 2 files changed, 117 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42674/1 diff --git a/util/mainboard/google/puff/template/Makefile.inc b/util/mainboard/google/puff/template/Makefile.inc index 61b23ed..3b5b7d0 100644 --- a/util/mainboard/google/puff/template/Makefile.inc +++ b/util/mainboard/google/puff/template/Makefile.inc @@ -1,4 +1,4 @@ -## ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/util/mainboard/google/puff/template/gpio.c b/util/mainboard/google/puff/template/gpio.c new file mode 100644 index 0000000..5a911fc --- /dev/null +++ b/util/mainboard/google/puff/template/gpio.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + /* C15 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0 Gerrit-Change-Number: 42674 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: util/mb/google/tmpl/puff: Fix include paths for gen board
by Edward O'Callaghan (Code Review) 23 Jun '20

23 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42673 ) Change subject: util/mb/google/tmpl/puff: Fix include paths for gen board ...................................................................... util/mb/google/tmpl/puff: Fix include paths for gen board BUG=b:154071868 BRANCH=none TEST=none Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/mainboard/google/puff/template/include/variant/acpi/dptf.asl M util/mainboard/google/puff/template/include/variant/ec.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/42673/1 diff --git a/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl b/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl index fd3b5cf..6694063 100644 --- a/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl +++ b/util/mainboard/google/puff/template/include/variant/acpi/dptf.asl @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/acpi/dptf.asl> +#include <puff/acpi/dptf.asl> diff --git a/util/mainboard/google/puff/template/include/variant/ec.h b/util/mainboard/google/puff/template/include/variant/ec.h index ce6fbfe..59fb378 100644 --- a/util/mainboard/google/puff/template/include/variant/ec.h +++ b/util/mainboard/google/puff/template/include/variant/ec.h @@ -3,6 +3,6 @@ #ifndef VARIANT_EC_H #define VARIANT_EC_H -#include <baseboard/ec.h> +#include <puff/ec.h> #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c Gerrit-Change-Number: 42673 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/hatch: Make puff and variants share common mainboard.c
by Edward O'Callaghan (Code Review) 23 Jun '20

23 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42672 ) Change subject: mb/google/hatch: Make puff and variants share common mainboard.c ...................................................................... mb/google/hatch: Make puff and variants share common mainboard.c Here we consolidate some of the mainboard.c duplication between Puff and it's variants. Customizations can be done later via introducing a devicetree parameterisation. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/Makefile.inc R src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/hatch/variants/duffy/Makefile.inc D src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/kaisa/Makefile.inc D src/mainboard/google/hatch/variants/kaisa/mainboard.c M src/mainboard/google/hatch/variants/noibat/Makefile.inc D src/mainboard/google/hatch/variants/noibat/mainboard.c M src/mainboard/google/hatch/variants/puff/Makefile.inc 9 files changed, 1 insertion(+), 485 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42672/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index c051437..c92d1bb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -6,6 +6,7 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-$(BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c verstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c similarity index 100% rename from src/mainboard/google/hatch/variants/puff/mainboard.c rename to src/mainboard/google/hatch/variants/baseboard/mainboard.c diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc +++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c deleted file mode 100644 index 253a7c9..0000000 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <soc/pci_devs.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) -#define PUFF_U22_PL2 (35) -#define PUFF_U62_U42_PL2 (51) -#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) -#define PUFF_CORE_CPU_PSYSPL2 (90) -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | - * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----------------+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | - * +-------------+-----+-----------+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value - u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - dev = pcidev_path_on_root(SA_DEVFN_IGD); - u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - /* set psyspl2 to 90% of adapter rating */ - psyspl2 = SET_PSYSPL2(watts); - - /* Limit PL2 if the adapter is with lower capability */ - if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || - mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) - pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; - else - pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; - - conf->tdp_psyspl3 = psyspl2; - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ - conf->tdp_pl4 = psyspl2; - } else { - /* - * Input type is barrel jack, from the SKU matrix: - * 1. i3/i5/i7 SKUs use 90W BJ - * 2. Celeron and Pentium use 65W BJ (default) - */ - volts_mv = BJ_VOLTS_MV; - /* Use IGD ID to check if CPU is Core SKUs */ - if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && - igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { - psyspl2 = PUFF_CORE_CPU_PSYSPL2; - if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || - mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) - pl2 = PUFF_U62_U42_PL2; - } - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = pl2; - conf->tdp_psyspl2 = psyspl2; -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *confg = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &confg->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c deleted file mode 100644 index 253a7c9..0000000 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <soc/pci_devs.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) -#define PUFF_U22_PL2 (35) -#define PUFF_U62_U42_PL2 (51) -#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) -#define PUFF_CORE_CPU_PSYSPL2 (90) -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | - * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----------------+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.9n, PL2) | 0.9n | 0.9n | 0.9n | - * +-------------+-----+-----------+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value - u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - dev = pcidev_path_on_root(SA_DEVFN_IGD); - u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - /* set psyspl2 to 90% of adapter rating */ - psyspl2 = SET_PSYSPL2(watts); - - /* Limit PL2 if the adapter is with lower capability */ - if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || - mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) - pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; - else - pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; - - conf->tdp_psyspl3 = psyspl2; - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ - conf->tdp_pl4 = psyspl2; - } else { - /* - * Input type is barrel jack, from the SKU matrix: - * 1. i3/i5/i7 SKUs use 90W BJ - * 2. Celeron and Pentium use 65W BJ (default) - */ - volts_mv = BJ_VOLTS_MV; - /* Use IGD ID to check if CPU is Core SKUs */ - if (igd_id != PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 && - igd_id != PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5) { - psyspl2 = PUFF_CORE_CPU_PSYSPL2; - if (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT || - mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2) - pl2 = PUFF_U62_U42_PL2; - } - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = pl2; - conf->tdp_psyspl2 = psyspl2; -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *confg = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &confg->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/hatch/variants/noibat/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/noibat/Makefile.inc +++ b/src/mainboard/google/hatch/variants/noibat/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/noibat/mainboard.c b/src/mainboard/google/hatch/variants/noibat/mainboard.c deleted file mode 100644 index b5bc699..0000000 --- a/src/mainboard/google/hatch/variants/noibat/mainboard.c +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) - -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); - } else { - /* Input type is barrel jack */ - volts_mv = BJ_VOLTS_MV; - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *conf = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &conf->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Gerrit-Change-Number: 42672 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020