coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: Override power limits with SKU-specific limits
by Tim Wawrzynczak (Code Review) 22 Jun '20

22 Jun '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42436 ) Change subject: mb/google/volteer: Override power limits with SKU-specific limits ...................................................................... mb/google/volteer: Override power limits with SKU-specific limits Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available from. They are dependent upon the SKU of the CPU that the mainboard is running on. This is distinguished via System Agent PCI ID and the appropriate limits specified in devtree are overriden. BUG=152639350 TEST=On a Volteer SKU4, verified the following console output: CPU TDP = 28 Watts CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 41 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42436/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 1ede7f2..b24e97a 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,16 +1,16 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -25,6 +25,40 @@ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } +static void override_power_limits(void) +{ + struct soc_intel_tigerlake_config *config; + struct device *sa; + uint16_t sa_pci_id; + + sa = pcidev_path_on_root(SA_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + config = config_of_soc(); + + /* + * Reconfigure power limits depending on which processor SKU is on this particular + * mainboard. This is detected via System Agent PCI ID. + */ + switch (sa_pci_id) { + case PCI_DEVICE_ID_INTEL_TGL_ID_U: + case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: + /* 4 cores, allow for higher power limits (in W) */ + config->power_limits_config.tdp_pl1_override = 15; + config->power_limits_config.tdp_pl2_override = 60; + config->power_limits_config.tdp_pl4 = 105; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: + /* 2 cores, allow for lower power limits (in W) */ + config->power_limits_config.tdp_pl1_override = 15; + config->power_limits_config.tdp_pl2_override = 38; + config->power_limits_config.tdp_pl4 = 71; + break; + default: + printk(BIOS_ERR, "Volteer: unknown SA ID: 0x%4x", sa_pci_id); + break; + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; @@ -36,6 +70,8 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + override_power_limits(); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/42436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Gerrit-Change-Number: 42436 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: amd/picasso/acpi: Add power resources for I2C and UART
by Raul Rangel (Code Review) 22 Jun '20

22 Jun '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42473 ) Change subject: amd/picasso/acpi: Add power resources for I2C and UART ...................................................................... amd/picasso/acpi: Add power resources for I2C and UART This allows the kernel to runtime suspend these devices and properly shut them down. If a tty is not used, the kernel will disable the device. I omitted UART0 because the PSP will not power the controller before accessing it. This causes PSP boot failures. See b/158772504. We also can't enable UART0 D3 until we stop using the mmio kernel command line `console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART controller before it notices that the mmio address matches ttyS0. This causes the kernel to fail writing to the UART. So we need to move over to `console=ttyS0`. BUG=b:153001807, b:157617092, b:157858890, b:158772504 TEST=Boot trembyle and see I2C devices entering and exiting D3. * See the UART devices entering D3 * Made sure the i2c peripherals were still functional. * Ran suspend stress test for 40+ iterations. [ 0.349094] power-0362 __acpi_power_on : Power resource [FUR1] turned on [ 0.350627] power-0362 __acpi_power_on : Power resource [FUR2] turned on [ 0.352094] power-0362 __acpi_power_on : Power resource [FUR3] turned on [ 0.353626] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 0.376980] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.399997] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.401953] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 0.403460] power-0362 __acpi_power_on : Power resource [I2C4] turned on [ 0.483646] power-0418 __acpi_power_off : Power resource [I2C4] turned off [ 1.028404] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 1.448426] power-0418 __acpi_power_off : Power resource [I2C2] turned off [ 5.308094] power-0418 __acpi_power_off : Power resource [FUR1] turned off [ 5.340833] power-0418 __acpi_power_off : Power resource [FUR2] turned off [ 5.382041] power-0418 __acpi_power_off : Power resource [FUR3] turned off [ 5.423861] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 6.698225] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 6.856573] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 8.246970] power-0418 __acpi_power_off : Power resource [I2C2] turned off Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600 --- A src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/picasso/acpi/soc.asl 3 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/42473/1 diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl new file mode 100644 index 0000000..6577cfc --- /dev/null +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio_map.h> + +#define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \ + PowerResource(DEV_NAME, SX, 0) { \ + OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \ + Field (AOAC, ByteAcc, NoLock, Preserve) { \ + /* \ + * Target Device State \ + * \ + * 0 = D0 - Uninitialized \ + * 1 = D0 - Initialized \ + * 2 = D1/D2/D3Hot \ + * 3 = D3Cold \ + * \ + * This field is only used to cut off register access. It does not \ + * control any power states. D3Cold is the only value that will \ + * cut off register access. All other values will allow register \ + * access and are purely informational. \ + */ \ + TDS, 2, \ +\ + DS, 1, /* Device State - Purely informational */ \ +\ + /* \ + * Power On Dev \ + * \ + * 1 = Perform hardware sequence to power on the device \ + * 0 = Perform hardware sequence to power off the device \ + * \ + * This register is only valid when Is Software Control = 0. \ + */ \ + POD, 1, \ +\ + /* Software Power On Reset B */ \ + SPRB, 1, \ + /* Software Ref Clock OK */ \ + SRCO, 1, \ + /* Software Reset B */ \ + SRB, 1, \ + /* \ + * Is Software Control \ + * \ + * 1 = Allow software to control Power On Reset B, \ + * Ref Clock OK, and Reset B. \ + * 0 = Hardware control \ + */ \ + ISWC, 1, \ +\ + /* Power Reset B State */ \ + PRBS, 1, \ + /* Ref Clock OK State */ \ + RCOS, 1, \ + /* Reset B State */ \ + RBS, 1, \ + /* Device Off Gating State */ \ + DOGS, 1, \ + /* D3 Cold State */ \ + D3CS, 1, \ + /* Device Clock OK State */ \ + COS, 1, \ + /* State of device */ \ + STA0, 1, \ + /* State of device */ \ + STA1, 1, \ + } \ + Method(_STA) { \ + Local0 = (PRBS && RCOS && RBS) \ +\ + Printf("AOAC.%s._STA: %o", #DEV_NAME, Local0) \ +\ + If (Local0) { \ + Return (1) \ + } Else { \ + Return (0) \ + } \ + } \ + Method(_ON, 0, Serialized) { \ + Printf("AOAC.%s._ON", #DEV_NAME) \ +\ + ISWC=0 \ + POD=1 \ +\ + While (!PRBS || !RCOS || !RBS) { \ + Printf ("Waiting for device to power on") \ + Stall (100) \ + } \ +\ + Printf("Done waiting") \ + } \ + Method(_OFF, 0, Serialized) { \ + Printf("AOAC.%s._OFF", #DEV_NAME) \ +\ + ISWC=0 \ + POD=0 \ +\ + While (PRBS || RCOS || RBS) { \ + Printf ("Waiting for device to power off") \ + Stall (100) \ + } \ +\ + Printf("Done waiting") \ + } \ + Method(_RST, 0, Serialized) { \ + Printf("AOAC.%s._RST", #DEV_NAME) \ +\ + ISWC=1 \ + SRB=1 \ +\ + /* Assert the SwRstB signal for 200 us */ \ + Stall (200) \ +\ + SRB=0 \ + ISWC=0 \ +\ + While (!PRBS || !RCOS || !RBS) { \ + Printf ("Waiting for device to complete reset") \ + Stall (100) \ + } \ + } \ + } + + +Device (AOAC) { + Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + + Method (_STA, 0x0, NotSerialized) + { + /* + * This case is used to indicate a valid device for which no + * device driver should be loaded (for example, a bridge + * device.) Children of this device may be present and valid. + * OSPM should continue enumeration below a device whose _STA + * returns this bit combination. + */ + Return (0x08) + } + + AOAC_DEVICE(I2C2, 7, 0) + AOAC_DEVICE(I2C3, 8, 0) + AOAC_DEVICE(I2C4, 9, 5) + AOAC_DEVICE(FUR1, 12, 0) + AOAC_DEVICE(FUR2, 16, 0) + AOAC_DEVICE(FUR3, 26, 0) +} diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 0801c11..00774fd 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -153,6 +153,18 @@ Return (Local0) } } + + Name (_PR0, Package () { \_SB.AOAC.FUR1 }) + Name (_PR2, Package () { \_SB.AOAC.FUR1 }) + Name (_PR3, Package () { \_SB.AOAC.FUR1 }) + Method (_PS0, 0, Serialized) { + Printf("FUR1._PS0") + \_SB.AOAC.FUR1.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR1._PS3") + \_SB.AOAC.FUR1.TDS = 3 + } } Device (FUR2) { @@ -184,6 +196,18 @@ Return (Local0) } } + + Name (_PR0, Package () { \_SB.AOAC.FUR2 }) + Name (_PR2, Package () { \_SB.AOAC.FUR2 }) + Name (_PR3, Package () { \_SB.AOAC.FUR2 }) + Method (_PS0, 0, Serialized) { + Printf("FUR2._PS0") + \_SB.AOAC.FUR2.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR2._PS3") + \_SB.AOAC.FUR2.TDS = 3 + } } Device (FUR3) { @@ -215,6 +239,18 @@ Return (Local0) } } + + Name (_PR0, Package () { \_SB.AOAC.FUR3 }) + Name (_PR2, Package () { \_SB.AOAC.FUR3 }) + Name (_PR3, Package () { \_SB.AOAC.FUR3 }) + Method (_PS0, 0, Serialized) { + Printf("FUR3._PS0") + \_SB.AOAC.FUR3.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR3._PS3") + \_SB.AOAC.FUR3.TDS = 3 + } } Device (I2C2) { @@ -249,6 +285,18 @@ { Return (0x0F) } + + Name (_PR0, Package () { \_SB.AOAC.I2C2 }) + Name (_PR2, Package () { \_SB.AOAC.I2C2 }) + Name (_PR3, Package () { \_SB.AOAC.I2C2 }) + Method (_PS0, 0, Serialized) { + Printf("I2C2._PS0") + \_SB.AOAC.I2C2.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("I2C2._PS3") + \_SB.AOAC.I2C2.TDS = 3 + } } Device (I2C3) @@ -283,6 +331,18 @@ { Return (0x0F) } + + Name (_PR0, Package () { \_SB.AOAC.I2C3 }) + Name (_PR2, Package () { \_SB.AOAC.I2C3 }) + Name (_PR3, Package () { \_SB.AOAC.I2C3 }) + Method (_PS0, 0, Serialized) { + Printf("I2C3._PS0") + \_SB.AOAC.I2C3.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("I2C3._PS3") + \_SB.AOAC.I2C3.TDS = 3 + } } Device (I2C4) { @@ -317,6 +377,18 @@ { Return (0x0F) } + + Name (_PR0, Package () { \_SB.AOAC.I2C4 }) + Name (_PR2, Package () { \_SB.AOAC.I2C4 }) + Name (_PR3, Package () { \_SB.AOAC.I2C4 }) + Method (_PS0, 0, Serialized) { + Printf("I2C4._PS0") + \_SB.AOAC.I2C4.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("I2C4._PS3") + \_SB.AOAC.I2C4.TDS = 3 + } } Device (MISC) diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b411c20..b3b036e 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -11,6 +11,9 @@ /* Describe PCI INT[A-H] for the Southbridge */ #include "pci_int.asl" +/* Describe the AOAC devices */ +#include "aoac.asl" + /* Describe the devices in the Southbridge */ #include "sb_fch.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/42473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600 Gerrit-Change-Number: 42473 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/ocp/deltalake: add RW_MRC_CACHE flash region
by Jonathan Zhang (Code Review) 22 Jun '20

22 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42025 ) Change subject: mb/ocp/deltalake: add RW_MRC_CACHE flash region ...................................................................... mb/ocp/deltalake: add RW_MRC_CACHE flash region Add RW_MRC_CACHE flash region to hold MRC cache data. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a --- M src/mainboard/ocp/deltalake/board.fmd 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42025/1 diff --git a/src/mainboard/ocp/deltalake/board.fmd b/src/mainboard/ocp/deltalake/board.fmd index 24c7f33..5b8c430 100644 --- a/src/mainboard/ocp/deltalake/board.fmd +++ b/src/mainboard/ocp/deltalake/board.fmd @@ -6,6 +6,7 @@ } SI_BIOS@0x3000000 0x1000000 { FMAP@0x0 0x800 - COREBOOT(CBFS)@0x800 0xfff800 + RW_MRC_CACHE@0x800 0x10000 + COREBOOT(CBFS)@0x10800 0xfef800 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a Gerrit-Change-Number: 42025 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/ocp/deltalake: Add OCP Delta Lake mainboard
by Patrick Georgi (Code Review) 22 Jun '20

22 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40387 ) Change subject: mb/ocp/deltalake: Add OCP Delta Lake mainboard ...................................................................... mb/ocp/deltalake: Add OCP Delta Lake mainboard OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A configs/builder/config.ocp.deltalake A src/mainboard/ocp/deltalake/Kconfig A src/mainboard/ocp/deltalake/Kconfig.name A src/mainboard/ocp/deltalake/Makefile.inc A src/mainboard/ocp/deltalake/acpi/platform.asl A src/mainboard/ocp/deltalake/board.fmd A src/mainboard/ocp/deltalake/board_info.txt A src/mainboard/ocp/deltalake/bootblock.c A src/mainboard/ocp/deltalake/devicetree.cb A src/mainboard/ocp/deltalake/dsdt.asl A src/mainboard/ocp/deltalake/fadt.c A src/mainboard/ocp/deltalake/ramstage.c A src/mainboard/ocp/deltalake/romstage.c 13 files changed, 648 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/configs/builder/config.ocp.deltalake b/configs/builder/config.ocp.deltalake new file mode 100644 index 0000000..4a8cda1 --- /dev/null +++ b/configs/builder/config.ocp.deltalake @@ -0,0 +1,17 @@ +# type this to get working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.deltalake + +CONFIG_VENDOR_OCP=y +CONFIG_BOARD_OCP_DELTALAKE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065a.mcb" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/deltalake/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/deltalake/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/deltalake/Server_S.fd" +CONFIG_ME_BIN_PATH="site-local/deltalake/flashregion_2_intel_me.bin" +CONFIG_IFD_BIN_PATH="site-local/deltalake/flashregion_0_flashdescriptor.bin" diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig new file mode 100644 index 0000000..679115a --- /dev/null +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -0,0 +1,32 @@ +if BOARD_OCP_DELTALAKE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select FSP_CAR + select HAVE_ACPI_TABLES + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_COOPERLAKE_SP + select SUPERIO_ASPEED_AST2400 + +config MAINBOARD_DIR + string + default "ocp/deltalake" + +config MAINBOARD_PART_NUMBER + string + default "DeltaLake" + +config MAINBOARD_FAMILY + string + default "DeltaLake" + +config MAX_SOCKET + int + default 1 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/Kconfig.name b/src/mainboard/ocp/deltalake/Kconfig.name new file mode 100644 index 0000000..c59421f --- /dev/null +++ b/src/mainboard/ocp/deltalake/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_DELTALAKE + bool "DeltaLake" diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc new file mode 100644 index 0000000..bfdd78e --- /dev/null +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/mainboard/ocp/deltalake/acpi/platform.asl b/src/mainboard/ocp/deltalake/acpi/platform.asl new file mode 100644 index 0000000..e04bde5 --- /dev/null +++ b/src/mainboard/ocp/deltalake/acpi/platform.asl @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +Name (_S0, Package () // mandatory system state +{ + 0x00, 0x00, 0x00, 0x00 +}) + +Name (_S5, Package () // mandatory system state +{ + 0x07, 0x00, 0x00, 0x00 +}) + +/* The APM port can be used for generating software SMIs */ +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) +Field (PSYS, ByteAcc, NoLock, Preserve) +{ + PLAT, 32, // Platform ID + + // IOAPIC + APC0, 1, // PCH IOAPIC Enable + AP00, 1, // PC00 IOAPIC Enable + AP01, 1, // PC01 IOAPIC Enable + AP02, 1, // PC02 IOAPIC Enable + AP03, 1, // PC03 IOAPIC Enable + AP04, 1, // PC04 IOAPIC Enable + AP05, 1, // PC05 IOAPIC Enable + AP06, 1, // PC06 IOAPIC Enable + AP07, 1, // PC07 IOAPIC Enable + AP08, 1, // PC08 IOAPIC Enable + AP09, 1, // PC09 IOAPIC Enable + AP10, 1, // PC10 IOAPIC Enable + AP11, 1, // PC11 IOAPIC Enable + AP12, 1, // PC12 IOAPIC Enable + AP13, 1, // PC13 IOAPIC Enable + AP14, 1, // PC14 IOAPIC Enable + AP15, 1, // PC15 IOAPIC Enable + AP16, 1, // PC16 IOAPIC Enable + AP17, 1, // PC17 IOAPIC Enable + AP18, 1, // PC18 IOAPIC Enable + AP19, 1, // PC19 IOAPIC Enable + AP20, 1, // PC20 IOAPIC Enable + AP21, 1, // PC21 IOAPIC Enable + AP22, 1, // PC22 IOAPIC Enable + AP23, 1, // PC23 IOAPIC Enable + RESA, 7, + SKOV, 1, // Override Socket APIC Id + RES0, 7, + + // Power Management + TPME, 1, + CSEN, 1, + C3EN, 1, + C6EN, 1, + C7EN, 1, + MWOS, 1, + PSEN, 1, + EMCA, 1, + HWAL, 2, + KPRS, 1, + MPRS, 1, + TSEN, 1, + FGTS, 1, + OSCX, 1, + RESX, 1, + + // RAS + CPHP, 8, + IIOP, 8, + IIOH, 64, + PRBM, 32, + P0ID, 32, + P1ID, 32, + P2ID, 32, + P3ID, 32, + P4ID, 32, + P5ID, 32, + P6ID, 32, + P7ID, 32, + P0BM, 64, + P1BM, 64, + P2BM, 64, + P3BM, 64, + P4BM, 64, + P5BM, 64, + P6BM, 64, + P7BM, 64, + MEBM, 16, + MEBC, 16, + CFMM, 32, + TSSY, 32, // TODO: This is TSSZ in system booted from production FW + M0BS, 64, + M1BS, 64, + M2BS, 64, + M3BS, 64, + M4BS, 64, + M5BS, 64, + M6BS, 64, + M7BS, 64, + M0RN, 64, + M1RN, 64, + M2RN, 64, + M3RN, 64, + M4RN, 64, + M5RN, 64, + M6RN, 64, + M7RN, 64, + SMI0, 32, + SMI1, 32, + SMI2, 32, + SMI3, 32, + SCI0, 32, + SCI1, 32, + SCI2, 32, + SCI3, 32, + MADD, 64, + CUU0, 128, + CUU1, 128, + CUU2, 128, + CUU3, 128, + CUU4, 128, + CUU5, 128, + CUU6, 128, + CUU7, 128, + CPSP, 8, + ME00, 128, + ME01, 128, + ME10, 128, + ME11, 128, + ME20, 128, + ME21, 128, + ME30, 128, + ME31, 128, + ME40, 128, + ME41, 128, + ME50, 128, + ME51, 128, + ME60, 128, + ME61, 128, + ME70, 128, + ME71, 128, + MESP, 16, + LDIR, 64, + PRID, 32, + AHPE, 8, + + // VTD + DHRD, 192, + ATSR, 192, + RHSA, 192, + + // SR-IOV + WSIC, 8, + WSIS, 16, + WSIB, 8, + WSID, 8, + WSIF, 8, + WSTS, 8, + WHEA, 8, + + // BIOS Guard + BGMA, 64, + BGMS, 8, + BGIO, 16, + BGIL, 8, + CNBS, 8, + + // USB3 + XHMD, 8, + SBV1, 8, + SBV2, 8, + + // HWPM + HWEN, 2, + ACEN, 1, + HWPI, 1, + RES1, 4, + + // IIO + BB00, 8, + BB01, 8, + BB02, 8, + BB03, 8, + BB04, 8, + BB05, 8, + BB06, 8, + BB07, 8, + BB08, 8, + BB09, 8, + BB10, 8, + BB11, 8, + BB12, 8, + BB13, 8, + BB14, 8, + BB15, 8, + BB16, 8, + BB17, 8, + BB18, 8, + BB19, 8, + BB20, 8, + BB21, 8, + BB22, 8, + BB23, 8, + BB24, 8, + BB25, 8, + BB26, 8, + BB27, 8, + BB28, 8, + BB29, 8, + BB30, 8, + BB31, 8, + BB32, 8, + BB33, 8, + BB34, 8, + BB35, 8, + BB36, 8, + BB37, 8, + BB38, 8, + BB39, 8, + BB40, 8, + BB41, 8, + BB42, 8, + BB43, 8, + BB44, 8, + BB45, 8, + BB46, 8, + BB47, 8, + SGEN, 8, + SG00, 8, + SG01, 8, + SG02, 8, + SG03, 8, + SG04, 8, + SG05, 8, + SG06, 8, + SG07, 8, + + // Performance + CLOD, 8, + + // XTU + XTUB, 32, + XTUS, 32, + XMBA, 32, + DDRF, 8, + RT3S, 8, + RTP0, 8, + RTP3, 8, + + // FPGA + FBB0, 8, + FBB1, 8, + FBB2, 8, + FBB3, 8, + FBB4, 8, + FBB5, 8, + FBB6, 8, + FBB7, 8, + FBL0, 8, + FBL1, 8, + FBL2, 8, + FBL3, 8, + FBL4, 8, + FBL5, 8, + FBL6, 8, + FBL7, 8, + P0FB, 8, + P1FB, 8, + P2FB, 8, + P3FB, 8, + P4FB, 8, + P5FB, 8, + P6FB, 8, + P7FB, 8, + FMB0, 32, + FMB1, 32, + FMB2, 32, + FMB3, 32, + FMB4, 32, + FMB5, 32, + FMB6, 32, + FMB7, 32, + FML0, 32, + FML1, 32, + FML2, 32, + FML3, 32, + FML4, 32, + FML5, 32, + FML6, 32, + FML7, 32, + FKPB, 32, + FKB0, 8, + FKB1, 8, + FKB2, 8, + FKB3, 8, + FKB4, 8, + FKB5, 8, + FKB6, 8, + FKB7, 8 +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/ocp/deltalake/board.fmd b/src/mainboard/ocp/deltalake/board.fmd new file mode 100644 index 0000000..24c7f33 --- /dev/null +++ b/src/mainboard/ocp/deltalake/board.fmd @@ -0,0 +1,11 @@ +FLASH 64M { + SI_ALL@0x0 0x3000000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2FE7000 + PLATFORM_DATA@0x2FE8000 0x10000 + } + SI_BIOS@0x3000000 0x1000000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x800 0xfff800 + } +} diff --git a/src/mainboard/ocp/deltalake/board_info.txt b/src/mainboard/ocp/deltalake/board_info.txt new file mode 100644 index 0000000..f5c0700 --- /dev/null +++ b/src/mainboard/ocp/deltalake/board_info.txt @@ -0,0 +1,5 @@ +Board name: DeltaLake +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2020 diff --git a/src/mainboard/ocp/deltalake/bootblock.c b/src/mainboard/ocp/deltalake/bootblock.c new file mode 100644 index 0000000..8004170 --- /dev/null +++ b/src/mainboard/ocp/deltalake/bootblock.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb new file mode 100644 index 0000000..26912d1 --- /dev/null +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/cpx + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # configure device interrupt routing + register "ir00_routing" = "0x3210" # IR00, Dev31 + register "ir01_routing" = "0x3210" # IR01, Dev30 + register "ir02_routing" = "0x3210" # IR02, Dev29 + register "ir03_routing" = "0x3210" # IR03, Dev28 + register "ir04_routing" = "0x3210" # IR04, Dev27 + + # configure interrupt polarity control + register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow + register "ipc1" = "0x00000000" # IPC1 + register "ipc2" = "0x00000000" # IPC2 + register "ipc3" = "0x00000000" # IPC3 + + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + # FB production turbo_ratio_limit is 0x1f1f1f2022222325 + register "turbo_ratio_limit" = "0x1b1b1b1d20222325" + # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 + register "turbo_ratio_limit_cores" = "0x1c1814100c080402" + + # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL + register "pstate_req_ratio" = "0xa" + + register "coherency_support" = "0" + register "ats_support" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 04.0 on end # Intel SkyLake-E CBDMA Registers + device pci 04.1 on end # Intel SkyLake-E CBDMA Registers + device pci 04.2 on end # Intel SkyLake-E CBDMA Registers + device pci 04.3 on end # Intel SkyLake-E CBDMA Registers + device pci 04.4 on end # Intel SkyLake-E CBDMA Registers + device pci 04.5 on end # Intel SkyLake-E CBDMA Registers + device pci 04.6 on end # Intel SkyLake-E CBDMA Registers + device pci 04.7 on end # Intel SkyLake-E CBDMA Registers + device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers + device pci 05.2 on end # Intel SkyLake-E RAS + device pci 05.4 on end # Intel SkyLake-E IOAPIC + device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers + device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers + device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers + device pci 11.0 on end # Intel Device a26c: PCU + + # PCH devices + device pci 11.5 on end # Intel C620 Series Chipset Family SSATA Controller [AHCI mode] + device pci 14.0 on end # Intel C620 Series Chipset Family USB 3.0 xHCI Controller + + device pci 14.2 on end # Signal processing controller: Intel Device a231 + device pci 16.0 on end # Communication controller: Intel Device a23a + device pci 16.1 on end # Communication controller: Intel Device a23b + device pci 16.4 on end # Communication controller: Intel Device a23e + device pci 1c.0 on end # PCI bridge: Intel Device a210 + device pci 1c.4 on end # PCI bridge: Intel Device a214 + device pci 1c.5 on end # PCI bridge: Intel Device a215 + device pci 1d.0 on end # PCI bridge: Intel Device a218 + device pci 1f.0 on end # ISA bridge: Intel Device a245 + device pci 1f.1 on end # p2sb + device pci 1f.2 on end # Memory controller: Intel Device a221 + device pci 1f.3 on end # Audio device: Intel Device a270 + device pci 1f.4 on end # Intel C620 Series Chipset Family SMBus + device pci 1f.5 on end # Intel C620 Series Chipset Family SPI Controller + end +end diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl new file mode 100644 index 0000000..c74b5fe --- /dev/null +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // CPX-SP ACPI tables + #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> +} diff --git a/src/mainboard/ocp/deltalake/fadt.c b/src/mainboard/ocp/deltalake/fadt.c new file mode 100644 index 0000000..b9fcd58 --- /dev/null +++ b/src/mainboard/ocp/deltalake/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <soc/acpi.h> + +void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c new file mode 100644 index 0000000..c4da628 --- /dev/null +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c new file mode 100644 index 0000000..35c7e2d --- /dev/null +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <FspmUpd.h> +#include <soc/romstage.h> + +/* +* Configure GPIO depend on platform +*/ +static void mainboard_config_gpios(FSPM_UPD *mupd) +{ + /* To be implemented */ +} + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + /* To be implemented */ +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mainboard_config_gpios(mupd); + mainboard_config_iio(mupd); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Gerrit-Change-Number: 40387 Gerrit-PatchSet: 31 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/mipi_camera: SSDT add camera power resource
by Paul Menzel (Code Review) 22 Jun '20

22 Jun '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: SSDT add camera power resource ...................................................................... Patch Set 23: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/41624/23//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41624/23//COMMIT_MSG@7 PS23, Line 7: drivers/intel/mipi_camera: SSDT add camera power resource Mayeb: > Add camera power resource to SSDT -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 23 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Jun 2020 12:21:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: consider stack personality
by Jonathan Zhang (Code Review) 22 Jun '20

22 Jun '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42333 to review the following change. Change subject: soc/intel/xeon_sp/cpx: consider stack personality ...................................................................... soc/intel/xeon_sp/cpx: consider stack personality Each IIO stack has a personality. Only when personality of a stack is TYPE_UBOX_IIO, the stack has PCIe devices. For example, for CPX-SP, the stack 3 has personality of TYPE_UBOX, it does not have PCIe devices. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I2f6bfdac4d1110dd95f1b3a72e2e51f70c79212b --- M src/soc/intel/xeon_sp/cpx/soc_util.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42333/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 9b04115..203de87 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -173,11 +173,10 @@ for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { for (int x = 0; x < MAX_IIO_STACK; ++x) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - // TODO: do we have situation with only bux 0 and one stack? - if (ri->BusBase >= ri->BusLimit) - continue; - assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + if (ri->Personality == TYPE_UBOX_IIO) { + assert(info->no_of_stacks < ARRAY_SIZE(info->res)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f6bfdac4d1110dd95f1b3a72e2e51f70c79212b Gerrit-Change-Number: 42333 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: soc/intel/xeon_sp/cpx: ACPI xSDT Table update
by Jonathan Zhang (Code Review) 22 Jun '20

22 Jun '20

Hello Anjaneya "Reddy" Chagam, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40927 to review the following change. Change subject: soc/intel/xeon_sp/cpx: ACPI xSDT Table update ...................................................................... soc/intel/xeon_sp/cpx: ACPI xSDT Table update Add uncore devices, interrupt definition, etc to xSDT table. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I2fa9c26abc6aef2d255535c2abf8b6b67d26359f --- M src/soc/intel/xeon_sp/cpx/acpi.c A src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl A src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl A src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl A src/soc/intel/xeon_sp/cpx/acpi/uncore.asl A src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h 7 files changed, 902 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/40927/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index f72e2ab..3deec01 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -81,9 +81,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { - config_t *config = config_of_soc(); - (void) config; - /* not implemented yet */ + acpi_init_gnvs(gnvs); } static unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl new file mode 100644 index 0000000..c2d5853 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* + * Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + PCNT, 8, // 0x11 - Processor count + TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS + PM1I, 64, // 0x15 - PM1 wake status bit + GPEI, 64, // 0x1D - GPE wake status bit + U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap + U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap + + + /* Device Config */ + Offset (0x30), + S5U0, 8, // 0x30 - Enable USB0 in S5 + S5U1, 8, // 0x31 - Enable USB1 in S5 + S3U0, 8, // 0x32 - Enable USB0 in S3 + S3U1, 8, // 0x33 - Enable USB1 in S3 + TACT, 8, // 0x34 - Thermal Active trip point + TPSV, 8, // 0x35 - Thermal Passive trip point + TCRT, 8, // 0x36 - Thermal Critical trip point + DPTE, 8, // 0x37 - Enable DPTF + + /* Base addresses */ + Offset (0x50), + CMEM, 32, // 0x50 - CBMEM TOC + TOLM, 32, // 0x54 - Top of Low Memory + CBMC, 32, // 0x58 - coreboot mem console pointer + MMOB, 32, // 0x5C - MMIO Base Low Base + MMOL, 32, // 0x60 - MMIO Base Low Limit + MMHB, 64, // 0x64 - MMIO Base High Base + MMHL, 64, // 0x6C - MMIO Base High Limit + TSGB, 32, // 0x74 - TSEG Base + TSSZ, 32, // 0x78 - TSEG Size +} diff --git a/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl new file mode 100644 index 0000000..5db2ee1 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define MAKE_IIO_DEV(id,rt) \ + Device (PC##id) \ + { \ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ + Name (_UID, 0x##id) \ + Method (_PRT, 0, NotSerialized) \ + { \ + If (PICM) \ + { \ + Return (\_SB_.AR##rt) \ + } \ + Return (\_SB_.PR##rt) \ + } \ + External(\_SB.RT##id) \ + Method (_CRS, 0, NotSerialized) \ + { \ + Return (\_SB.RT##id) \ + } \ + Name (SUPP, 0x00) \ + Name (CTRL, 0x00) \ + Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ + Method (_OSC, 4, NotSerialized) \ + { \ + CreateDWordField (Arg3, 0x00, CDW1) \ + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ + { \ + CreateDWordField (Arg3, 0x04, CDW2) \ + If ((Arg2 > 0x02)) \ + { \ + CreateDWordField (Arg3, 0x08, CDW3) \ + } \ + SUPP = CDW2 \ + CTRL = CDW3 \ + If ((AHPE || ((SUPP & 0x16) != 0x16))) \ + { \ + CTRL &= 0x1E \ + Sleep (0x03E8) \ + } \ + /* Never allow SHPC (no SHPC controller in system) */ \ + CTRL &= 0x1D \ + /* Disable Native PCIe AER handling from OS */ \ + CTRL &= 0x17 \ + If ((Arg1 != One)) /* unknown revision */ \ + { \ + CDW1 |= 0x08 \ + } \ + If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ + { \ + CDW1 |= 0x10 \ + } \ + CDW3 = CTRL \ + Return (Arg3) \ + } \ + Else \ + { \ + /* indicate unrecognized UUID */ \ + CDW1 |= 0x04 \ + IO80 = 0xEE \ + Return (Arg3) \ + } \ + } \ + } + +MAKE_IIO_DEV(00, 00) +MAKE_IIO_DEV(01, 10) +MAKE_IIO_DEV(02, 20) +MAKE_IIO_DEV(03, 28) + +#if MAX_SOCKET > 1 +MAKE_IIO_DEV(06, 40) +MAKE_IIO_DEV(07, 50) +MAKE_IIO_DEV(08, 60) +MAKE_IIO_DEV(09, 68) +#endif diff --git a/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl new file mode 100644 index 0000000..cfa4ad5 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 + * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 + * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 + * + * PIRQ routing control is in PCR ITSS region. + */ + +OperationRegion (ITSS, SystemMemory, + Add (PCR_ITSS_PIRQA_ROUT, + Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + +Name (PRSA, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,7,10,11,12,14,15} +}) +Alias (PRSA, PRSB) +Name (PRSC, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,10,11,12,14,15} +}) +Alias (PRSC, PRSD) +Alias (PRSA, PRSE) +Alias (PRSA, PRSF) +Alias (PRSA, PRSG) +Alias (PRSA, PRSH) + +#define MAKE_LINK_DEV(id,uid) \ + Device (LNK##id) \ + { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, ##uid) \ + Method (_PRS, 0, NotSerialized) \ + { \ + Return (PRS##id) \ + } \ + Method (_CRS, 0, Serialized) \ + { \ + Name (RTLA, ResourceTemplate () \ + { \ + IRQ (Level, ActiveLow, Shared) {} \ + }) \ + CreateWordField (RTLA, 1, IRQ0) \ + Store (Zero, IRQ0) \ + \ + /* Set the bit from PIRQ Routing Register */ \ + ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ + Return (RTLA) \ + } \ + Method (_SRS, 1, Serialized) \ + { \ + CreateWordField (Arg0, 1, IRQ0) \ + FindSetRightBit (IRQ0, Local0) \ + Decrement (Local0) \ + Store (Local0, ^^PIR##id) \ + } \ + Method (_STA, 0, Serialized) \ + { \ + If (And (^^PIR##id, ^^IREN)) { \ + Return (0x9) \ + } Else { \ + Return (0xb) \ + } \ + } \ + Method (_DIS, 0, Serialized) \ + { \ + Or (^^PIR##id, ^^IREN, ^^PIR##id) \ + } \ + } + +MAKE_LINK_DEV(A,1) +MAKE_LINK_DEV(B,2) +MAKE_LINK_DEV(C,3) +MAKE_LINK_DEV(D,4) +MAKE_LINK_DEV(E,5) +MAKE_LINK_DEV(F,6) +MAKE_LINK_DEV(G,7) +MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl b/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl new file mode 100644 index 0000000..35fbf98 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Scope(\) +{ + // Private Chipset Register(PCR). Memory Mapped through ILB + OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) + Field(PCRR, DWordAcc, Lock, Preserve) + { + Offset (0xD03100), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Scope (_SB) +{ + #include "pci_irq.asl" + #include "uncore_irq.asl" + #include "iiostack.asl" +} diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl new file mode 100644 index 0000000..f03ded1 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl @@ -0,0 +1,566 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Uncore devices PCI interrupt routing packages. + * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. + * The mapping fields ae Address, Pin, Source, Source Index. + */ + +#define GEN_PCIE_LEGACY_IRQ() \ + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ + Package (0x04) { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ + Package (0x04) { 0x0003FFFF, 0x03, LNKD, 0x00 } + +#define GEN_UNCORE_LEGACY_IRQ(dev) \ + Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ + Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ + Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ + Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + +#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \ + Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \ + Package (0x04) { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, ##irq4 } + +#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ + Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ + Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ + Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ + Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + +// Socket 0, IIOStack 0 device legacy interrupt routing +Name (PR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + // [CB0A]: CBDMA + // [CB0E]: CBDMA + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + // [CB0B]: CBDMA + // [CB0F]: CBDMA + Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + // [CB0C]: CBDMA + // [CB0G]: CBDMA + Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + // [CB0D]: CBDMA + // [CB0H]: CBDMA + Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + // Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + // // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, +}) + +// Socket 0, IIOStack 0 device IOAPIC interrupt routing +Name (AR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + // [CB0A]: CB3DMA + // [CB0E]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + // [CB0B]: CB3DMA + // [CB0F]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + // [CB0C]: CB3DMA + // [CB0G]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // [CB0D]: CB3DMA + // [CB0H]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // [UBX0]: Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, +}) + +// Socket 0, IIOStack 1 device legacy interrupt routing +Name (PR10, Package (0x40) +{ + // PCI Express Port 1A-1D + GEN_PCIE_LEGACY_IRQ(), + + // Uncore CHAUTIL Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore CHASAD Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + + // Uncore CMSCHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + + // Uncore CHASADALL Device + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // Uncore PCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + + // Uncore VCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 0, IIOStack 1 device IOAPIC interrupt routing +Name (AR10, Package (0x40) +{ + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x27,0x21,0x22,0x23), + + // Uncore CHAUTIL Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASAD Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CMSCHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASADALL Device + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore PCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore VCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) +}) + +// Socket 0, IIOStack 2 device legacy interrupt routing +Name (PR20, Package (0x24) +{ + // PCI Express Port A-D on PC02 + GEN_PCIE_LEGACY_IRQ(), + + // Uncore M2MEM Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + + // Uncore MCDECS2 Device + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + + // Uncore MCDECS Device + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 2 device IOAPIC interrupt routing +Name (AR20, Package (0x24) +{ + // PCI Express Port A-D on PC02 + GEN_PCIE_IOAPIC_IRQ(0x2F,0x29,0x2A,0x2B), + + // Uncore M2MEM Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS2 Device + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS Device + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) +}) + +// Socket 0, IIOStack 3 device legacy interrupt routing +Name (PR28, Package (0x20) +{ + // PCI Express Port 3 on PC03 + GEN_PCIE_LEGACY_IRQ(), + + // KTI Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + + // M3K Device + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + + // M2U Device + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + + // M2D Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // M20 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 3 device IOAPIC interrupt routing +Name (AR28, Package (0x20) +{ + // PCI Express Port 3 A-D on PC03 + GEN_PCIE_IOAPIC_IRQ(0x37,0x31,0x32,0x33), + + // KTI Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), + + // M3K Device + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2U Device + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2D Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), + + // M20 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) +}) + +// Socket 1, IIOStack 0 device legacy interrupt routing +Name (PR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + + // CBDMA + GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), + + // Ubox + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) +}) + +// Socket 1, IIOStack 0 device IOAPIC interrupt routing +Name (AR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + + // CBDMA + GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), + + // Ubox + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), +}) + +// Socket 1, IIOStack 1 device legacy interrupt routing +Name (PR50, Package (0x40) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // CHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // PCU Devices + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 1, IIOStack 1 device IOAPIC interrupt routing +Name (AR50, Package (0x40) +{ + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x57,0x51,0x52,0x53), + + // CHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), + + // PCU Devices + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) +}) + +// Socket 1, IIOStack 2 device legacy interrupt routing +Name (PR60, Package (0x24) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Integrated Memory Controller + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 2 device IOAPIC interrupt routing +Name (AR60, Package (0x24) +{ + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x5F,0x59,0x5A,0x5B), + + // Integrated Memory Controller + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (PR68, Package (0x20) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (AR68, Package (0x20) +{ + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x67,0x61,0x62,0x63), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) +}) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h index 93cd474..e43f6cb 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h @@ -26,8 +26,6 @@ } MEM_BLK; void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); void uncore_inject_dsdt(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/40927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fa9c26abc6aef2d255535c2abf8b6b67d26359f Gerrit-Change-Number: 40927 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: nb/intel/sandybridge/gma.c: Remove useless if condition
by Evgeny Zinoviev (Code Review) 22 Jun '20

22 Jun '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42410 ) Change subject: nb/intel/sandybridge/gma.c: Remove useless if condition ...................................................................... nb/intel/sandybridge/gma.c: Remove useless if condition There's a useless check with both branches doing the same: enabling RC6 and disabling RC6p. In past, this condition would enable RC6p in IVB but not on SNB. Then, at some point, RC6p was considered unstable and was disabled, but the condition remained. It's not needed so let's remove it. Change-Id: I926bb682d1b9d21185048224490b966c33204b6a Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/northbridge/intel/sandybridge/gma.c 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42410/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 83a0279..8117c62 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -453,18 +453,14 @@ gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ - /* 11a: Enable Render Standby (RC6) */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* - * IvyBridge should also support DeepRenderStandby. - * - * Unfortunately it does not work reliably on all SKUs so - * disable it here and it can be enabled by the kernel. - */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } else { - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } + /* 11a: Enable Render Standby (RC6) + * + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(0xa090, 0x88040000); /* HW RC Control */ /* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926bb682d1b9d21185048224490b966c33204b6a Gerrit-Change-Number: 42410 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/jasperlake: add processor power limits control support
by Sumeet R Pawnikar (Code Review) 22 Jun '20

22 Jun '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41777 ) Change subject: soc/intel/jasperlake: add processor power limits control support ...................................................................... soc/intel/jasperlake: add processor power limits control support Add processor power limits control support to configure values for jasperlake soc based platforms. BRANCH=None BUG=None TEST=Built for dedede system Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/jasperlake/systemagent.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41777/1 diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index db56cc0..bdf8fee 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <delay.h> #include <device/pci.h> #include <device/pci_ops.h> #include <intelblocks/systemagent.h> +#include <intelblocks/power_limit.h> #include <soc/iomap.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> /* @@ -54,9 +57,17 @@ */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } -- To view, visit https://review.coreboot.org/c/coreboot/+/41777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f Gerrit-Change-Number: 41777 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/kukui: Add Hynix 4GB discrete LPDDR4X DDR support
by Duan huayang (Code Review) 22 Jun '20

22 Jun '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42502 ) Change subject: google/kukui: Add Hynix 4GB discrete LPDDR4X DDR support ...................................................................... google/kukui: Add Hynix 4GB discrete LPDDR4X DDR support Support 4GB H9HCNNNCPMMLXR-NEE discrete DDR bootup. BUG=b:156691665 BRANCH=none TEST=Boots correctly and stress test passes on Kukui. Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42502/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 73bd2f8..ed30d70 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -15,6 +15,7 @@ [6] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", [7] = "sdram-lpddr4x-SDADA4CR-128G-4GB", [8] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [10] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 4d91998..af13aa1 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -7,6 +7,7 @@ sdram-params += sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB sdram-params += sdram-lpddr4x-KMDV6001DA-B620-4GB sdram-params += sdram-lpddr4x-SDADA4CR-128G-4GB +sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c new file mode 100644 index 0000000..6b53bcc --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <soc/emi.h> + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, + [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x0, 0x0}, + [CHANNEL_B] = {0x0, 0x0} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x52, 0x52}, + [CHANNEL_B] = {0x52, 0x52} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/42502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652 Gerrit-Change-Number: 42502 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

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