coreboot-gerrit June 2020

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Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: Check if memory is 'locked'
by Jonathan Zhang (Code Review) 24 Jun '20

24 Jun '20

Hello Andrey Petrov, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42710 to review the following change. Change subject: soc/intel/fsp_broadwell_de: Check if memory is 'locked' ...................................................................... soc/intel/fsp_broadwell_de: Check if memory is 'locked' Under certain conditions TXT can "lock" memory controller for security purpose. This manifests itself in IMC's SMbus controller failing all SPD data read requests. FSP does not detect error condition and fails boot with "No memory found" issue. TEST=tested on OCP monolake in 'locked' state Change-Id: If4637e4293421794a89037ff107e87794c40114a Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/memory.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/romstage/memory.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42710/1 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h index 3bdba2e..494ca34 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/memory.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/memory.h @@ -27,4 +27,8 @@ void save_dimm_info(void); +/* Determine if memory configuration has been locked by TXT */ +bool memory_config_is_locked(void); + + #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index f9fdffb..2bbcf23 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -39,4 +39,9 @@ #define MSR_PRMRR_PHYS_BASE 0x1f4 #define MSR_PRMRR_PHYS_MASK 0x1f5 +/* EDS vol 2 */ +#define MSR_LT_MEMORY_LOCKED 0x2e7 +#define MSR_MEM_LOCK_BIT1 (1 << 1) +#define MSR_MEM_LOCK_BIT2 (1 << 2) + #endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/memory.c b/src/soc/intel/fsp_broadwell_de/romstage/memory.c index b4bc097..571ab09 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/memory.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/memory.c @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <cpu/x86/msr.h> +#include <soc/msr.h> #include <stddef.h> #include <device/pci_ops.h> #include <device/dram/ddr4.h> @@ -85,3 +87,9 @@ } } } + +bool memory_config_is_locked(void) +{ + msr_t msr = rdmsr(MSR_LT_MEMORY_LOCKED); + return (msr.lo & (MSR_MEM_LOCK_BIT1 | MSR_MEM_LOCK_BIT2)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: If4637e4293421794a89037ff107e87794c40114a Gerrit-Change-Number: 42710 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: volteer: Create volteer2 variant
by Nick Vaccaro (Code Review) 24 Jun '20

24 Jun '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42605 ) Change subject: volteer: Create volteer2 variant ...................................................................... volteer: Create volteer2 variant Create the volteer2 variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). Modified to aphabetize and update to duplicate latest volteer changes currently in the review and merge pipeline. Added the following missing files from the variants/volteer2/ folder: - gpio.c - include/variant/acpi/dptf.asl - acpi/mipi_camera.asl - Makefile.inc - memory/dram_id.generated.txt - memory/Makefile.inc - memory/mem_list_variant.txt - overridetree.cb BUG=b:159135047 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLTEER2 Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/volteer2/Makefile.inc A src/mainboard/google/volteer/variants/volteer2/gpio.c A src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl A src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl A src/mainboard/google/volteer/variants/volteer2/include/variant/ec.h A src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h A src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc A src/mainboard/google/volteer/variants/volteer2/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/volteer2/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/volteer2/overridetree.cb 12 files changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/42605/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 44c393f..16527e4 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -72,6 +72,7 @@ default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO default "Volteer" if BOARD_GOOGLE_VOLTEER + default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Voxel" if BOARD_GOOGLE_VOXEL config MAX_CPUS @@ -104,6 +105,7 @@ default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO default "volteer" if BOARD_GOOGLE_VOLTEER + default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "voxel" if BOARD_GOOGLE_VOXEL config VARIANT_HAS_MIPI_CAMERA diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 51ee6cd..8768946 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -27,6 +27,11 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select VARIANT_HAS_MIPI_CAMERA +config BOARD_GOOGLE_VOLTEER2 + bool "-> Volteer2" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA + config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/volteer2/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc new file mode 100644 index 0000000..13269db --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c new file mode 100644 index 0000000..075e6e2 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + /* APIC interrupt conflict, so used GPI_INT; see b/147500717 */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H14, 1, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + + /* F12 : GSXDOUT ==> WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..726e381 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/dptf.asl @@ -0,0 +1,7 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl new file mode 100644 index 0000000..418f2e0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/acpi/mipi_camera.asl> diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer2/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h new file mode 100644 index 0000000..5839395 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h @@ -0,0 +1,26 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc new file mode 100644 index 0000000..c2abb9e --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/memory/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volteer2/memory/dram_id.generated.txt new file mode 100644 index 0000000..637fd23 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) +K4UBE3D4AA-MGCL 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) diff --git a/src/mainboard/google/volteer/variants/volteer2/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/volteer2/memory/mem_list_variant.txt new file mode 100644 index 0000000..c532d0d --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +K4U6E3S4AA-MGCL +K4UBE3D4AA-MGCL +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb new file mode 100644 index 0000000..24b869c --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -0,0 +1,165 @@ +chip soc/intel/tigerlake + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + end + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 1.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 1 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 1.7 on end + end + end + end + end + device pci 1f.2 hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/42605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad Gerrit-Change-Number: 42605 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

7 10

Change in coreboot[master]: soc/intel/tigerlake: Fix unresolved symbol CDW1 error
by John Zhao (Code Review) 24 Jun '20

24 Jun '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42693 ) Change subject: soc/intel/tigerlake: Fix unresolved symbol CDW1 error ...................................................................... soc/intel/tigerlake: Fix unresolved symbol CDW1 error The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after booting to kernel. Fix the error by properly creating the buffer field CDW1 to cover all errors scenarios. BUG=b:140645231 TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42693/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 2fda693..3f51ecc 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -159,13 +159,14 @@ * control of the respectively capabilities or features. */ Name (CTRL, 0) /* Control field value */ + CreateDWordField (Arg3, 0, CDW1) If (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { - CreateDWordField(Arg3, 0, CDW1) - CreateDWordField(Arg3, 2, CDW3) + CreateDWordField (Arg3, 2, CDW3) CTRL = CDW3 If (Arg1 != REVISION_ID) { CDW1 |= UNRECOGNIZED_REVISION + Return (Arg3) } CTRL |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | INTER_DOMAIN_USB4_INTERNET_PROTOCOL -- To view, visit https://review.coreboot.org/c/coreboot/+/42693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012 Gerrit-Change-Number: 42693 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
by HAOUAS Elyes (Code Review) 24 Jun '20

24 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41009 ) Change subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register ...................................................................... soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/adsp.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41009/1 diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 64b7d5e..1f5f814 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -118,7 +118,7 @@ printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); /* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); /* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, -- To view, visit https://review.coreboot.org/c/coreboot/+/41009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Gerrit-Change-Number: 41009 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: src: Report byte-sized access for GPE0
by Angel Pons (Code Review) 24 Jun '20

24 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42671 ) Change subject: src: Report byte-sized access for GPE0 ...................................................................... src: Report byte-sized access for GPE0 According to the ACPI specification, version 6.3: OSPM accesses GPE registers through byte accesses (regardless of their length). So, reporting dword-sized access is wrong and means nothing anyway. Change-Id: I965131a28f1a385d065c95f286549665c3f9693e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/quark/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/42671/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7704c30..c868c34 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -206,7 +206,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..ffead50 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -178,7 +178,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 0d83c01..43ff8eb 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -283,7 +283,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4e4906c..0321962 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -156,7 +156,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 3b3e37a..b5f57f6 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -206,7 +206,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0x00; diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index bf173d9..628ef3a 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -78,7 +78,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6ff836a..b0e5cc7 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -330,7 +330,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 085f9dd..807a3f2 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -332,7 +332,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 3da2025..e35eb96 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -313,7 +313,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0x00; @@ -428,7 +428,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 719eb54..bb86d5f 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -141,7 +141,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index ba277f9..4bca136 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -161,7 +161,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8ed0330..a243252 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -144,7 +144,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 038bb37..595bb7e 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -791,7 +791,7 @@ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 901c97c..90198a2 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -496,7 +496,7 @@ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index edd1430..077f105 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -501,7 +501,7 @@ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4f86e9b..f3dfa14 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -691,7 +691,7 @@ fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 128; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x20; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6cdbc78..756ab56 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -856,7 +856,7 @@ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0x0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965131a28f1a385d065c95f286549665c3f9693e Gerrit-Change-Number: 42671 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: sb/intel/bd82x6x: Align mei_recv_msg() functions
by Angel Pons (Code Review) 24 Jun '20

24 Jun '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42010 ) Change subject: sb/intel/bd82x6x: Align mei_recv_msg() functions ...................................................................... sb/intel/bd82x6x: Align mei_recv_msg() functions They only differ in rather small details, so we can iron them out. Change-Id: I01907f1b8576e82c74b7beeea31ae8ee3e2cc773 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 2 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42010/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index f961bfba..68e6dbf 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -234,8 +234,7 @@ return mei_wait_for_me_ready(); } -static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; @@ -279,7 +278,8 @@ if (mei_rsp.length & 3) ndata++; if (ndata != (expected - 1)) { - printk(BIOS_ERR, "ME: response is missing data\n"); + printk(BIOS_ERR, "ME: response is missing data %d != %d\n", + ndata, (expected - 1)); return -1; } @@ -322,7 +322,7 @@ { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; - if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) return -1; return 0; } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 32c96ad..e1fdd5d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -234,13 +234,12 @@ return mei_wait_for_me_ready(); } -static int mei_recv_msg(struct mkhi_header *mkhi, - void *rsp_data, int rsp_bytes) +static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes) { struct mei_header mei_rsp; struct mkhi_header mkhi_rsp; struct mei_csr me, host; - unsigned int ndata, n/*, me_data_len*/; + unsigned int ndata, n; unsigned int expected; u32 *data; -- To view, visit https://review.coreboot.org/c/coreboot/+/42010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01907f1b8576e82c74b7beeea31ae8ee3e2cc773 Gerrit-Change-Number: 42010 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/amd/stoneyridge: Correct ACPI CPU string prefix
by Matt DeVillier (Code Review) 24 Jun '20

24 Jun '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42627 ) Change subject: soc/amd/stoneyridge: Correct ACPI CPU string prefix ...................................................................... soc/amd/stoneyridge: Correct ACPI CPU string prefix Commit 9550e97 [acpi: correct the processor devices scope] changed the default CPU scope from _PR to _SB, but the default prefix in Stoneyridge's Kconfig was missed, leading to ACPI errors for 'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and eliminate the errors reported in dmesg. Test: boot Linux w/5.3 kernel on google/liara, check for errors Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/42627/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47642a9..d8a3b34e 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -295,7 +295,7 @@ config ACPI_CPU_STRING string - default "\\_PR.P%03d" + default "\\_SB.P%03d" config ACPI_BERT bool "Build ACPI BERT Table" -- To view, visit https://review.coreboot.org/c/coreboot/+/42627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3 Gerrit-Change-Number: 42627 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: ACPI: Replace smm_setup_structures()
by Patrick Georgi (Code Review) 24 Jun '20

24 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42362 ) Change subject: ACPI: Replace smm_setup_structures() ...................................................................... ACPI: Replace smm_setup_structures() Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/acpi/Kconfig M src/arch/x86/acpi_s3.c M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/smi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/smi.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 34 files changed, 58 insertions(+), 178 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 11ef12a3..07008db 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,6 +24,9 @@ Provide common definitions for Intel hardware PM1_CNT register sleep values. +config ACPI_NO_SMI_GNVS + bool + config ACPI_NO_PCAT_8259 bool help diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index d4c697e..4872c07 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -4,7 +4,6 @@ #include <string.h> #include <acpi/acpi.h> #include <arch/cpu.h> -#include <cbmem.h> #include <commonlib/helpers.h> #include <cpu/x86/smm.h> #include <fallback.h> @@ -79,16 +78,8 @@ void acpi_resume(void *wake_vec) { - if (CONFIG(HAVE_SMI_HANDLER)) { - void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); - - /* Restore GNVS pointer in SMM if found */ - if (gnvs_address) { - printk(BIOS_DEBUG, "Restore GNVS pointer to %p\n", - gnvs_address); - smm_setup_structures(gnvs_address, NULL, NULL); - } - } + /* Restore GNVS pointer in SMM if found. */ + apm_control(APM_CNT_GNVS_UPDATE); /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 3cd387d..499cc5b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,6 +17,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 + select ACPI_NO_SMI_GNVS if CPU_AMD_AGESA diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 7bcfa61..533507e 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -17,6 +17,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select SSE2 + select ACPI_NO_SMI_GNVS if CPU_AMD_PI diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c index f1031a0..4b63745 100644 --- a/src/cpu/x86/smm/smi_trigger.c +++ b/src/cpu/x86/smm/smi_trigger.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +static void set_smm_gnvs_ptr(void); + int apm_control(u8 cmd) { if (!CONFIG(HAVE_SMI_HANDLER)) @@ -21,7 +24,8 @@ printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n"); break; case APM_CNT_GNVS_UPDATE: - break; + set_smm_gnvs_ptr(); + return 0; case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "Finalizing SMM.\n"); break; @@ -41,3 +45,32 @@ printk(BIOS_DEBUG, "APMC done.\n"); return 0; } + +static void set_smm_gnvs_ptr(void) +{ + uintptr_t gnvs_address; + + if (CONFIG(ACPI_NO_SMI_GNVS)) { + printk(BIOS_WARNING, "%s() is not implemented\n", __func__); + return; + } + + gnvs_address = (uintptr_t)acpi_get_gnvs(); + if (!gnvs_address) + return; + + /* + * Issue SMI to set the gnvs pointer in SMM. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" (gnvs_address), + "d" (APM_CNT) + ); +} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9db1461..cdc6901 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -48,8 +48,6 @@ void northbridge_smi_handler(void); void southbridge_smi_handler(void); -void smm_setup_structures(void *gnvs, void *tcg, void *smi1); - void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2df0b6a..fd2a205 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -56,6 +56,7 @@ select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select ACPI_NO_SMI_GNVS config MEMLAYOUT_LD_FILE string diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c index ba36e65..125dde6 100644 --- a/src/soc/amd/picasso/smi.c +++ b/src/soc/amd/picasso/smi.c @@ -11,11 +11,6 @@ #include <soc/southbridge.h> #include <soc/smi.h> -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 47642a9..9bb5604 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,6 +46,7 @@ select HAVE_SMI_HANDLER select SSE2 select RTC + select ACPI_NO_SMI_GNVS config AMD_APU_STONEYRIDGE bool diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index a3473aa..fb6d348 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -10,11 +10,6 @@ #include <soc/southbridge.h> #include <soc/smi.h> -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 58238db..c70388a 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -97,22 +97,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index fb63a56..679c04d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -494,7 +494,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 53379a0..1290d62 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -512,7 +512,7 @@ gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index e3ebc32..3f3c53f 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -99,22 +99,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b841291..1e96286 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -584,7 +584,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 9d8d25e..317da0c 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -86,22 +86,3 @@ /* Set EOS bit so other SMIs can occur. */ enable_smi(EOS); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 8d75c9a..c497399 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -240,7 +240,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 0b120a7..2fd97da 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -70,22 +70,3 @@ { smm_southbridge_enable(GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 3b3e37a..014625c 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -292,7 +292,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index b4970ad..e7ed28d 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -56,19 +56,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile("outb %%al, %%dx\n\t" - : /* ignore result */ - : "a"(APM_CNT_GNVS_UPDATE), "b"((uint32_t)gnvs), - "d"(APM_CNT)); -} diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6ff836a..414a14f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -655,7 +655,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 6683301..9542562 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -38,6 +38,7 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP + select ACPI_NO_SMI_GNVS select SMP select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index abaa453..0261857 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -120,7 +120,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index 3da2025..17da9a9 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -968,7 +968,7 @@ if (gnvs) { acpi_create_gnvs(gnvs); /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ - // smm_setup_structures(gnvs, NULL, NULL); + // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 6c76825..f54faeb 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -10,11 +10,6 @@ #include "smi.h" -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 6c76825..f54faeb 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -10,11 +10,6 @@ #include "smi.h" -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); -} - /** Set the EOS bit and enable SMI generation from southbridge */ void global_smi_enable(void) { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 038bb37..fb82246 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -665,7 +665,7 @@ #endif /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 913cce0..06d7c74 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -79,25 +79,6 @@ smm_southbridge_enable(PWRBTN_EN | GBL_EN); } -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uintptr_t)gnvs), - "d" (APM_CNT) - ); -} - void smm_southbridge_clear_state(void) { if (smi_enabled()) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 88c5633..55f3a84 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -622,7 +622,7 @@ acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 27a7c95..db214ee 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -464,7 +464,7 @@ acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index edd1430..0a2440d 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -623,7 +623,7 @@ acpi_create_gnvs(gnvs); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4f86e9b..5a6483f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -566,7 +566,7 @@ gnvs->pcnt = dev_count_cpu(); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6cdbc78..4b12b32 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -721,7 +721,7 @@ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); + apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 48b76e2..6edf5c1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -57,22 +57,3 @@ { smm_southbridge_enable(PWRBTN_EN | GBL_EN); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), - "d" (APM_CNT) - ); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Gerrit-Change-Number: 42362 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
by Patrick Georgi (Code Review) 24 Jun '20

24 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42361 ) Change subject: ACPI: Replace uses of CBMEM_ID_ACPI_GNVS ...................................................................... ACPI: Replace uses of CBMEM_ID_ACPI_GNVS These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/zork/mainboard.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/scc.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/scc.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/common/acpi_wake_source.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/nhlt.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/serialio.c 18 files changed, 47 insertions(+), 62 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 191eedc..239887e 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -5,9 +5,9 @@ #include <device/device.h> #include <device/mmio.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> -#include <cbmem.h> #include <baseboard/variants.h> #include <boardid.h> #include <smbios.h> @@ -165,7 +165,7 @@ { struct global_nvs_t *gnvs; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = acpi_get_gnvs(); if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index f87066a..1ed3e9d 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -6,9 +6,9 @@ #include <device/device.h> #include <device/mmio.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio_banks.h> -#include <cbmem.h> #include <baseboard/variants.h> #include <boardid.h> #include <gpio.h> @@ -196,7 +196,7 @@ { struct global_nvs_t *gnvs; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = acpi_get_gnvs(); reset_backlight_gpio(NULL); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0d908c3..45f66d6 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -10,6 +10,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> @@ -308,7 +309,7 @@ sws = cbmem_find(CBMEM_ID_POWER_STATE); if (sws == NULL) return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; @@ -336,7 +337,7 @@ static void set_sb_final_nvs(void) { - struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + struct global_nvs_t *gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..f217349 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -8,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/reset.h> @@ -542,7 +543,7 @@ sws = cbmem_find(CBMEM_ID_POWER_STATE); if (sws == NULL) return; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; @@ -575,7 +576,7 @@ size_t fwsize; const struct device *sd, *sata; - struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + struct global_nvs_t *gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index cb5c50c..78638de 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -53,11 +53,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 6b87cf0..d5c3e4d 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -31,11 +31,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 71b5f9a..455f243 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -84,11 +84,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 394715e..f3391de 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -56,11 +56,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index c173990..8200248 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -30,11 +30,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index df7dd7d..0b6385f 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -18,11 +18,9 @@ __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); /* Find ACPI NVS to update BARs */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index b8699a2..27368c0 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -85,11 +85,9 @@ printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 20a5d9a..4da3979 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -236,11 +236,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ gnvs->dev.bar0[sio_index] = (u32)bar0->base; diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index 9f30366..1342c80 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <bootstate.h> -#include <cbmem.h> #include <console/console.h> #include <soc/nvs.h> #include <stdint.h> @@ -16,7 +16,7 @@ /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + global_nvs_t *gnvs = acpi_get_gnvs(); uint32_t pm1, *gpe0; int gpe_reg, gpe_reg_count; int reg_size = sizeof(uint32_t) * 8; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4e4906c..8d75c9a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -6,6 +6,7 @@ #include <bootstate.h> #include <cbmem.h> #include <cf9_reset.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> @@ -456,7 +457,7 @@ /* Save wake source data for ACPI _SWS methods in NVS */ static void acpi_save_wake_source(void *unused) { - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + global_nvs_t *gnvs = acpi_get_gnvs(); uint32_t pm1, *gpe0; int gpe_reg, gpe_reg_count; int reg_size = sizeof(uint32_t) * 8; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index cc5e485..0c641f3 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/uart.h> #include <device/device.h> #include <device/pci.h> @@ -167,7 +167,7 @@ */ static bool pch_uart_init_debug_controller_on_resume(void) { - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + global_nvs_t *gnvs = acpi_get_gnvs(); if (gnvs) return !!gnvs->uior; diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index 5d916ab..099be5d 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <nhlt.h> #include <soc/nvs.h> @@ -15,7 +15,7 @@ { global_nvs_t *gnvs; - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = acpi_get_gnvs(); if (gnvs == NULL) return acpi_addr; diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d63af6c..c4ea418 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> -#include <cbmem.h> #include <types.h> #include <string.h> #include <version.h> @@ -51,7 +51,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + global_nvs_t *gnvs = acpi_get_gnvs(); int id; if (!gnvs) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index cdb1f35..3973a8d 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <cbmem.h> +#include <acpi/acpi_gnvs.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -208,11 +208,9 @@ global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); + gnvs = acpi_get_gnvs(); + if (!gnvs) return; - } /* Save BAR0 and BAR1 to ACPI NVS */ gnvs->s0b[sio_index] = (u32)bar0->base; -- To view, visit https://review.coreboot.org/c/coreboot/+/42361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Gerrit-Change-Number: 42361 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ACPI: Add framework for GNVS initialisation
by Patrick Georgi (Code Review) 24 Jun '20

24 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42423 ) Change subject: ACPI: Add framework for GNVS initialisation ...................................................................... ACPI: Add framework for GNVS initialisation Provide common initialisation point for setting up GNVS structure before first SMI is triggered. Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/Makefile.inc A src/acpi/chromeos-gnvs.c A src/acpi/gnvs.c A src/include/acpi/acpi_gnvs.h 4 files changed, 108 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 7e37e1a..29ddc08 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -8,6 +8,8 @@ ramstage-y += acpigen_ps2_keybd.c ramstage-y += acpigen_usb.c ramstage-y += device.c +ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c +ramstage-y += gnvs.c ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c new file mode 100644 index 0000000..d30e204 --- /dev/null +++ b/src/acpi/chromeos-gnvs.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <types.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> + +void gnvs_assign_chromeos(void) +{ + chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(); + chromeos_init_chromeos_acpi(gnvs_chromeos); + + /* EC can override to ECFW_RW. */ + gnvs_chromeos->vbt2 = ACTIVE_ECFW_RO; + + if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) + gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW; +} diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c new file mode 100644 index 0000000..fbc84b3 --- /dev/null +++ b/src/acpi/gnvs.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <acpi/acpigen.h> +#include <cbmem.h> +#include <console/console.h> +#include <string.h> +#include <types.h> + +static void *gnvs; + +void *acpi_get_gnvs(void) +{ + if (gnvs) + return gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs) + return gnvs; + + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return NULL; +} + +static void gnvs_assign_cbmc(void) +{ + uint32_t *gnvs_cbmc = gnvs_cbmc_ptr(); + if (gnvs_cbmc) + *gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); +} + +void *gnvs_get_or_create(void) +{ + size_t gnvs_size; + + if (gnvs) + return gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (gnvs) + return gnvs; + + gnvs_size = gnvs_size_of_array(); + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size); + if (!gnvs) + return gnvs; + + memset(gnvs, 0, gnvs_size); + + if (CONFIG(CONSOLE_CBMEM)) + gnvs_assign_cbmc(); + + if (CONFIG(CHROMEOS)) + gnvs_assign_chromeos(); + + return gnvs; +} + +void acpi_inject_nvsa(void) +{ + uintptr_t gnvs_address = (uintptr_t)acpi_get_gnvs(); + if (!gnvs_address) + return; + + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", gnvs_address); + acpigen_pop_len(); +} diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h new file mode 100644 index 0000000..cc0c471 --- /dev/null +++ b/src/include/acpi/acpi_gnvs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ACPI_GNVS_H__ +#define __ACPI_GNVS_H__ + +#include <types.h> + +void *acpi_get_gnvs(void); +void *gnvs_get_or_create(void); +void acpi_inject_nvsa(void); + +void gnvs_assign_chromeos(void); + +/* Platform code must implement these. */ +size_t gnvs_size_of_array(void); +uint32_t *gnvs_cbmc_ptr(void); +void *gnvs_chromeos_ptr(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Gerrit-Change-Number: 42423 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit June 2020