Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 )
Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
PS13, Line 397: device pci 05.0 on end # RP4
> @Tim, I tried the following and the acpi_fill_ssdt callback is not getting called for IPU0. […]
Typo in my previous comment, following is what I tried and it did not work.
device pci 05.0 on
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "chip_name" = ""Camera and Imaging Subsystem""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{2,2}"
register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1""
register "cio2_prt[0]" = "0"
register "cio2_prt[1]" = "2"
end
end
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Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 )
Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
PS13, Line 397: device pci 05.0 on end # RP4
> Why is this still here?
@Tim, I tried the following and the acpi_fill_ssdt callback is not getting called for IPU0.
chip drivers/intel/mipi_camera
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "chip_name" = ""Camera and Imaging Subsystem""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{2,2}"
register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1""
register "cio2_prt[0]" = "0"
register "cio2_prt[1]" = "2"
end
end
So I moved pci device 05.0 from line 158 to here and it works fine. This is the only combination I found working.
All the devices for which SSDT is generated in this file, I see one device at the end of scope.
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Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 )
Change subject: drivers/intel/mipi_camera: Handle acpi_name and common code
......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41607/25/src/drivers/intel/mipi_ca…
File src/drivers/intel/mipi_camera/camera.c:
https://review.coreboot.org/c/coreboot/+/41607/25/src/drivers/intel/mipi_ca…
PS25, Line 101: const char *scope = acpi_device_scope(dev);
> You don't need the parent scope anymore?
Now I have moved the IPU device outside camera device scope and due to this now the device that is passed here is parent device of camera.
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 )
Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
......................................................................
Patch Set 44:
(3 comments)
https://review.coreboot.org/c/coreboot/+/40308/44//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/40308/44//COMMIT_MSG@12
PS44, Line 12: Need to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.
"Mainboard needs to configure"
https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d…
File src/drivers/ocp/dmi/ocp_dmi.h:
https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d…
PS44, Line 6: #include <cpu/x86/msr.h>
Do we need to include this header file?
https://review.coreboot.org/c/coreboot/+/40308/44/src/drivers/ocp/dmi/ocp_d…
PS44, Line 15: extern msr_t xeon_sp_ppin[];
All the PPIN related code are x86 specific. It should be guarded with CONFIG_ARCH_X86; while hardware access code should part of soc code, instead of here.
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Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 )
Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe…
PS13, Line 374: ^
> > Using ^ in pr0 might cause Windows to BSOD during boot, e.g.: […]
The lack of proper ^ handling in Windows seems to be specific to 'prX' / PowerResource (vs. a complete inability to handle them). I'm not sure why this part of Windows seems particularly limited in handling and prone to throwing BSODs (e.g., early boot of the kernel is more limited in capability?):
https://docs.microsoft.com/en-us/windows-hardware/drivers/debugger/bug-chec…
When I hit the issue on Nocturne the root cause wasn't that painful to ID since the system was previously bootable. Offhand I don't recall whether I used kernel debugging and/or reviewed the coreboot change list to identify the code change that introduced the issue. Otherwise, IDing the issue would be tough since the OS just BSODs during boot and I suspect the OS installer would also just BSOD during boot.
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