coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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2826 discussions

Change in coreboot[master]: mb/google/waddledee: Enable Audio
by Yong Zhi (Code Review) 24 Jun '20

24 Jun '20

Yong Zhi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41765 ) Change subject: mb/google/waddledee: Enable Audio ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… PS2, Line 67: register "uid" = "0" > Can you please check if EN_SPK gpio needs to be configured. […] According to kenny_chen(a)realtek.com, the codec driver uses internal control to shutdown the amp, so EN_SPK is not useful for the codec driver, that said, we can turn EN_SPK to off in the cb. -- To view, visit https://review.coreboot.org/c/coreboot/+/41765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Gerrit-Change-Number: 41765 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirtika Ruchandani <kirtika(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: Yong Zhi <yong.zhi(a)intel.com> Gerrit-Comment-Date: Wed, 24 Jun 2020 15:54:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/waddledee: Enable Audio
by Karthik Ramasubramanian (Code Review) 24 Jun '20

24 Jun '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41765 ) Change subject: mb/google/waddledee: Enable Audio ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… PS2, Line 61: 1 How is this 1 translate to HP_INT_ODL i.e. GPP_D16? https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… PS2, Line 67: register "uid" = "0" Can you please check if EN_SPK gpio needs to be configured. That GPIO is routed to SDB pin in the AMP. Same comment for right side AMP. -- To view, visit https://review.coreboot.org/c/coreboot/+/41765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Gerrit-Change-Number: 41765 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirtika Ruchandani <kirtika(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: Yong Zhi <yong.zhi(a)intel.com> Gerrit-Comment-Date: Wed, 24 Jun 2020 15:41:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ipmi: Add IPMI read FRU chassis info area
by Patrick Rudolph (Code Review) 24 Jun '20

24 Jun '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40306 ) Change subject: drivers/ipmi: Add IPMI read FRU chassis info area ...................................................................... Patch Set 26: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247 Gerrit-Change-Number: 40306 Gerrit-PatchSet: 26 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 24 Jun 2020 15:35:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Sugnan Prabhu S (Code Review) 24 Jun '20

24 Jun '20

Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Wonkyu Kim, Rizwan Qureshi, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41758 to look at the new patch set (#15). Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT This change updates devicetree to enable camera SSDT generation and removes changes related to camera DSDT. Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/dsdt.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl D src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb D src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl 8 files changed, 110 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41758/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 15 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/mipi_camera: Add camera power resource to SSDT
by Sugnan Prabhu S (Code Review) 24 Jun '20

24 Jun '20

Hello Varshit B Pandya, build bot (Jenkins), Daniel Kang, Furquan Shaikh, Wonkyu Kim, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41624 to look at the new patch set (#27). Change subject: drivers/intel/mipi_camera: Add camera power resource to SSDT ...................................................................... drivers/intel/mipi_camera: Add camera power resource to SSDT This change adds support function to parse entries in the devicetree to generate PowerResource entries for the MIPI camera. Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 159 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41624/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 27 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: fix host bridge bus numbers
by Aaron Durbin (Code Review) 24 Jun '20

24 Jun '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42734 ) Change subject: soc/amd/picasso: fix host bridge bus numbers ...................................................................... soc/amd/picasso: fix host bridge bus numbers The host bridge's resources covering bus numbers assumed 256 buses were being decoded. However, MMCONFIG was only covering 64 buses. This results in Linux complaining: acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge When retrieving the host bridge's resources fix up the bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't keep IASL from complaining when trying to do this statically. BUG=b:158874061 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64 --- M src/soc/amd/picasso/acpi/sb_pci0_fch.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42734/1 diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 27c4661..7488b55 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -101,6 +101,11 @@ Subtract(Local0, TOM1, Local0) Store(Local0, MM1L) + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) + Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) + Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64 Gerrit-Change-Number: 42734 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 24 Jun '20

24 Jun '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 8: (13 comments) https://review.coreboot.org/c/coreboot/+/41816/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41816/7//COMMIT_MSG@11 PS7, Line 11: increase > *to* increase? Done https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/memlay… File src/soc/amd/picasso/memlayout.ld: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/memlay… PS7, Line 3: #if ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) > Sounds good. I definitely like that option better. Done https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/memlay… PS7, Line 174: : /* SPDX-License-Identifier: GPL-2.0-only */ > remove Done https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 5: CPPFLAGS_verstage += -I$(src)/soc/amd/picasso/psp_verstage/include > I'll see what I can do. I haven't gotten to test this yet. Hopefully today. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/fch.c: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 79: printk(BIOS_DEBUG, "Mapping %s\n", bar_map[i].name); > is this debug really necessary any more? removed. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 80: err = svc_map_fch_dev(bar_map[i].args.device, bar_map[i].args.arg0, 0, &bar); > I'm assuming the individual calls are fast, but is there a reason why we didn't make this a single c […] Because AMD's interface lets us map one bar at a time. We can bring it up to them. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 86: printk(BIOS_DEBUG, "%s mapped to 0x%p\n", bar_map[i].name, bar); > debug still necessary? removed. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 121: svc_debug_print("Mapping devices\n"); > why svc_debug_print vs. […] This happens earlier in the sequence before the IO is set up, so we can't use printk yet. I removed this one as unnecessary as well though. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 32: printk Can't use printk here because it can be called early if there's a failure. Switch to svc_debug_print() https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 140: /* Do not use printk() before verstage_mainboard_init() is called */ > why not? Because IO isn't initialized until that point, and the system will hang. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 156: svc_write_postcode(0x01); > you use defines elsewhere but literals here. And we switch from scv_write_postcode to post_code. Thanks, I meant to go back and add #defines for these. We need to use svc_write_postcode before verstage_mainboard_init so that the IO addresses get set up, then we can switch over to post_code(). https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 186: svc_write_postcode(0xF1); > and switch back. […] Yes. These were the first ones implemented and they never got updated. https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… File src/soc/amd/picasso/psp_verstage/vboot_crypto.c: https://review.coreboot.org/c/coreboot/+/41816/7/src/soc/amd/picasso/psp_ve… PS7, Line 62: sha_op.DataLen = MIN(size, 1024); > why 1024 here? Any benefit to larger or smaller? That's a VERY good question. I was hoping that the answer would be in the updated documentation, but it's not there. I'll address it with AMD in our next meeting. In the meantime I'll turn it into a #define with a note that it should be tuned. -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 8 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 24 Jun 2020 13:52:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and Ezkinil
by chris wang (Code Review) 24 Jun '20

24 Jun '20

Hello Lucas Chen, Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42217 to review the following change. Change subject: mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and Ezkinil ...................................................................... mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and Ezkinil Add UPD xhci0_force_gen1 for Trembyle and Ezkinil. The default setting is set to disable. and set enabled for Ezkinil. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle. Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/devicetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/42217/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 664e379..650418f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -48,6 +48,8 @@ register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + register "xhci0_force_gen1" = "0" + # SPI Configuration register "common_config.spi_config" = "{ .normal_speed = SPI_SPEED_66M, /* MHz */ diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index c208dae..f7366ac 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -22,6 +22,8 @@ # End : OPN Performance Configuration + register "xhci0_force_gen1" = "1" + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/42217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052 Gerrit-Change-Number: 42217 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add UPD xhci0_force_gen1
by chris wang (Code Review) 24 Jun '20

24 Jun '20

Hello Raul Rangel, Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42216 to review the following change. Change subject: soc/amd/picasso: Add UPD xhci0_force_gen1 ...................................................................... soc/amd/picasso: Add UPD xhci0_force_gen1 Add xhci0_force_gen1 UPD for force USB3 port to gen1 BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42216/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e52751a..f5fbe0f 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -103,6 +103,8 @@ SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } sd_emmc_config; + + uint8_t xhci0_force_gen1; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 2d83220..e0620e5 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -95,6 +95,12 @@ fill_ddi_descriptors(scfg, fsp_ddi, num_ddi); } +static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, + const struct soc_amd_picasso_config *cfg) +{ + scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; +} + void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { const struct soc_amd_picasso_config *cfg; @@ -103,4 +109,5 @@ cfg = config_of_soc(); fsps_update_emmc_config(scfg, cfg); fsp_fill_pcie_ddi_descriptors(scfg); + fsp_usb_oem_customization(scfg, cfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Gerrit-Change-Number: 42216 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/malefor: Update overridetree.cb
by William Wei (Code Review) 24 Jun '20

24 Jun '20

William Wei has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42246 ) Change subject: mb/google/volteer/malefor: Update overridetree.cb ...................................................................... mb/google/volteer/malefor: Update overridetree.cb 1) Based on malefor schematics, disable unused I2C port, USB port, TBT PCIe 2) Add audio device to the tree, should update fw_config at the same time BUG=b:150653745 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the devices' function worked properly. Signed-off-by: William Wei <wenxu.wei(a)bitland.corp-partner.google.com> Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb --- M src/mainboard/google/volteer/variants/malefor/overridetree.cb 1 file changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42246/1 diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index 8d4c6ea..5e0f320 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -1,6 +1,76 @@ chip soc/intel/tigerlake + # USB Port Config + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S + end + end + end + device pci 15.1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" @@ -19,6 +89,17 @@ device i2c 5d on end end end # I2C1 + + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb Gerrit-Change-Number: 42246 Gerrit-PatchSet: 1 Gerrit-Owner: William Wei <wenxu.wei(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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