coreboot-gerrit June 2020

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Change in coreboot[master]: soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define
by Edward O'Callaghan (Code Review) 25 Jun '20

25 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42716 ) Change subject: soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define ...................................................................... soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. BUG=b:159187889 BRANCH=none TEST=none Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/soc/intel/cannonlake/include/soc/usb.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42716/1 diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 247b0ba..ac5776c 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -136,4 +136,11 @@ .tx_downscale_amp = 0x00, \ } +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6 Gerrit-Change-Number: 42716 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add a function to print hex dump with prefix
by Harshit Sharma (Code Review) 25 Jun '20

25 Jun '20

Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42793 to look at the new patch set (#2). Change subject: lib: Add a function to print hex dump with prefix ...................................................................... lib: Add a function to print hex dump with prefix Add a function hexdump_prefix() which allows to print hex dump with a prefix string. This function will be used by kasan library to print the shadow region state of the addresses around the location where a memory bug is found. Change-Id: I94869b10cd2d388a39cd5d86b1db936eff5473fa Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M src/include/lib.h M src/lib/hexdump.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42793/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94869b10cd2d388a39cd5d86b1db936eff5473fa Gerrit-Change-Number: 42793 Gerrit-PatchSet: 2 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add a function to print hex dump with prefix
by Harshit Sharma (Code Review) 25 Jun '20

25 Jun '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42793 ) Change subject: lib: Add a function to print hex dump with prefix ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94869b10cd2d388a39cd5d86b1db936eff5473fa Gerrit-Change-Number: 42793 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 25 Jun 2020 03:57:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add KASAN stub
by Harshit Sharma (Code Review) 25 Jun '20

25 Jun '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42271 ) Change subject: lib: Add KASAN stub ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Gerrit-Change-Number: 42271 Gerrit-PatchSet: 6 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 25 Jun 2020 01:21:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Tim Wawrzynczak (Code Review) 24 Jun '20

24 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe… PS15, Line 374: CAM1 This is not the correct name for the power resource, it was "PRIC". However, if we're trying to make this compatible with windows, then you'll need to emit a path that doesn't start with "^", so the full path will be required, "\_SB.PCI0.I2C5.CAM1.PRIC" I believe it would be. This is unfortunate, though 😞 If/When we get "alias" support in the devicetree, we can instead provide a reference to the other device and append "PRIC" to its ACPI path, instead of using hardcoded paths. https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe… PS15, Line 397: pci 05.0 on end # RP4 Sorry, I should have been more clear before. It looks like the IPU0 device should be described in the following way: device pci 05.0 on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" register "acpi_name" = ""IPU0"" .... register "cio2_prt[1]" = "2" device generic 0 on end end end # IPU If it isn't producing any output, then we'll need a minimal IPU PCI driver for JSL. -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 15 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Jun 2020 21:32:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Matt Delco (Code Review) 24 Jun '20

24 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/15/src/mainboard/intel/jaspe… PS15, Line 387: register "chip_name" = ""Camera and Imaging Subsystem" Nit: this line probably isn't needed. Specifying device_type=INTEL_ACPI_CAMERA_CIO2 causes write_pci_camera_device() to be called, which uses: acpigen_write_name_string("_DDN", config->device_type == INTEL_ACPI_CAMERA_CIO2 ? "Camera and Imaging Subsystem" : "Imaging Unit"); (vs. write_i2c_camera_device() which uses: acpigen_write_name_string("_DDN", config->chip_name); ) -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 15 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Jun 2020 19:20:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/mandolin: maximize CBFS size
by Felix Held (Code Review) 24 Jun '20

24 Jun '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42706 ) Change subject: mb/amd/mandolin: maximize CBFS size ...................................................................... mb/amd/mandolin: maximize CBFS size Change-Id: Ib829da0972bb7ec98f66fe8fe683289d91ad58dc Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42706/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 6ec77bf..eefa0df 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -27,9 +27,9 @@ Note that Kconfig does not currently enforce this restriction. config CBFS_SIZE - default 0x780000 + default 0x7cf000 help - TODO: Adjust this to maximize CBFS size + Maximum CBFS size for the Mandolin FMAP. config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/42706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib829da0972bb7ec98f66fe8fe683289d91ad58dc Gerrit-Change-Number: 42706 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Matt Delco (Code Review) 24 Jun '20

24 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… PS13, Line 397: device pci 05.0 on end # RP4 > Typo in my previous comment, following is what I tried and it did not work. […] I think what's mostly needed is to move the block of: chip drivers/intel/mipi_camera // ... device pci 05.0 on end # RP4 end to an earlier place in the file where "device pci 05.0 on end #IPU" is being removed. If I understand the comment & update what was attempted basically placed the chip block within the device line (when it should be the other way around). -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 15 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 24 Jun 2020 18:57:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] jasperlake: enable DPTF functionality for dedede
by Sumeet R Pawnikar (Code Review) 24 Jun '20

24 Jun '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41668 ) Change subject: [WIP] jasperlake: enable DPTF functionality for dedede ...................................................................... [WIP] jasperlake: enable DPTF functionality for dedede Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/dedede/variants/baseboard/devicetree.cb A src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl A src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl A src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl 7 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/41668/1 diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 6137f3b..3e99651 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -51,4 +51,15 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/common/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c891e6e..b7aee82 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -133,6 +133,16 @@ register "DdiPortBDdc" = "1" register "DdiPortCDdc" = "1" + # Enable DPTF + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "Device4Enable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000..f9eebe8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Below values might change after Thermal Tuning. */ +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Memory" +#define DPTF_TSR0_PASSIVE 80 +#define DPTF_TSR0_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/dedede/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledoo/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..189cafe --- /dev/null +++ b/src/mainboard/google/dedede/variants/wheelie/include/variant/acpi/dptf.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptf.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Gerrit-Change-Number: 41668 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Karthik Ramasubramanian (Code Review) 24 Jun '20

24 Jun '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/42462/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42462/4//COMMIT_MSG@17 PS4, Line 17: Nit: Please remove the extra line. Also I believe Cq-Depend: should be marked as TBD. -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 24 Jun 2020 16:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2020