coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ACPI: Replace smm_setup_structures()
by Kyösti Mälkki (Code Review) 24 Jun '20

24 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42362 ) Change subject: ACPI: Replace smm_setup_structures() ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/42362/9/src/cpu/x86/smm/smi_trigge… File src/cpu/x86/smm/smi_trigger.c: https://review.coreboot.org/c/coreboot/+/42362/9/src/cpu/x86/smm/smi_trigge… PS9, Line 47: void set_smm_gnvs_ptr(void) > Why is this exposed as a global if there's only one caller? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Gerrit-Change-Number: 42362 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:29:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Add framework for GNVS initialisation
by Kyösti Mälkki (Code Review) 24 Jun '20

24 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42423 ) Change subject: ACPI: Add framework for GNVS initialisation ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/42423/4/src/acpi/chromeos-gnvs.c File src/acpi/chromeos-gnvs.c: https://review.coreboot.org/c/coreboot/+/42423/4/src/acpi/chromeos-gnvs.c@18 PS4, Line 18: ACTIVE_ECFW_RO > Let's have Aaron or Furquan resolve this comment. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Gerrit-Change-Number: 42423 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Add framework for GNVS initialisation
by Kyösti Mälkki (Code Review) 24 Jun '20

24 Jun '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42423 ) Change subject: ACPI: Add framework for GNVS initialisation ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c File src/acpi/chromeos-gnvs.c: https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c@14 PS5, Line 14: gnvs_chromeos->vbt2 = ACTIVE_ECFW_RO; > OK. But we can move all that code from vendorcode. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Gerrit-Change-Number: 42423 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Replace smm_setup_structures()
by Kyösti Mälkki (Code Review) 24 Jun '20

24 Jun '20

Hello build bot (Jenkins), Raul Rangel, David Guckian, Vanessa Eusebio, Angel Pons, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42362 to look at the new patch set (#10). Change subject: ACPI: Replace smm_setup_structures() ...................................................................... ACPI: Replace smm_setup_structures() Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/arch/x86/acpi_s3.c M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig M src/cpu/x86/smm/smi_trigger.c M src/include/cpu/x86/smm.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/smi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/smi.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 34 files changed, 58 insertions(+), 178 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42362/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/42362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Gerrit-Change-Number: 42362 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Tim Wawrzynczak (Code Review) 24 Jun '20

24 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… PS13, Line 374: ^ > Using ^ in pr0 might cause Windows to BSOD during boot, e.g.: That's unfortunate, ^ is a perfectly legal part of a namestring, and that would violate the spec. from the spec: "A name proceeded with ‘^’ causes the name to refer to the parent of the current namespace (‘^’ is not part of the 32-bit fixed-length name)" You could use the absolute path as well. > I'm not sure if this problem still exists -- at some point coreboot may have changed the > ASL(?) compiler flag so name references are 'absolute' rather than 'relative'. The acpigen interface emits raw AML bytecode into the SSDT, so this code is not compiled by IASL. And IASL's behavior hasn't changed either, it still emits '^' all over the place, so if that's the case, there may be other entities in an SSDT that could cause the same problem with Windows. -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 13 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:16:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ACPI: Add framework for GNVS initialisation
by Aaron Durbin (Code Review) 24 Jun '20

24 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42423 ) Change subject: ACPI: Add framework for GNVS initialisation ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c File src/acpi/chromeos-gnvs.c: https://review.coreboot.org/c/coreboot/+/42423/5/src/acpi/chromeos-gnvs.c@14 PS5, Line 14: gnvs_chromeos->vbt2 = ACTIVE_ECFW_RO; > I do not want to span under vendorcode/ with my change. OK. But we can move all that code from vendorcode. That's the current location, but it doesn't have to be there. -- To view, visit https://review.coreboot.org/c/coreboot/+/42423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Gerrit-Change-Number: 42423 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:13:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT
by Matt Delco (Code Review) 24 Jun '20

24 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41758 ) Change subject: mb/intel/jasperlake_rvp: Camera remove DSDT and enable SSDT ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/41758/13/src/mainboard/intel/jaspe… PS13, Line 374: ^ Using ^ in pr0 might cause Windows to BSOD during boot, e.g.: https://review.coreboot.org/c/coreboot/+/27605 I'm not sure if this problem still exists -- at some point coreboot may have changed the ASL(?) compiler flag so name references are 'absolute' rather than 'relative'. -- To view, visit https://review.coreboot.org/c/coreboot/+/41758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97 Gerrit-Change-Number: 41758 Gerrit-PatchSet: 13 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Jun 2020 22:03:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add camera power resource to SSDT
by Tim Wawrzynczak (Code Review) 23 Jun '20

23 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: Add camera power resource to SSDT ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/c/coreboot/+/41624/25/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41624/25/src/drivers/intel/mipi_ca… PS25, Line 20: RCPR > I wonder if this should be called something more generic (e.g. […] Any 4-uppercase letter name (can include some _) is allowed, as long as it's unique in its scope. Obviously this doesn't always make for very intuitive names for ACPI devices, so I try not to be too picky about those. If you want to be like the rest of coreboot, the acpi_device_add_power_res() function uses the name "PRIC". -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 25 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Jun 2020 21:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add camera power resource to SSDT
by Matt Delco (Code Review) 23 Jun '20

23 Jun '20

Matt Delco has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41624 ) Change subject: drivers/intel/mipi_camera: Add camera power resource to SSDT ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/c/coreboot/+/41624/25/src/drivers/intel/mipi_ca… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/41624/25/src/drivers/intel/mipi_ca… PS25, Line 20: RCPR I wonder if this should be called something more generic (e.g., "CPR" or "POWR", if permitted by the spec). I assumed FCPR and RCPR was about front vs. rear camera power resource, so using RCPR for a non-rear camera might be misleading/confusing. -- To view, visit https://review.coreboot.org/c/coreboot/+/41624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Gerrit-Change-Number: 41624 Gerrit-PatchSet: 25 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-CC: Matt Delco <delco(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Jun 2020 21:50:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/*: Update makefiles to exclude x86 code from non-x86 verstage
by Martin Roth (Code Review) 23 Jun '20

23 Jun '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42062 ) Change subject: src/*: Update makefiles to exclude x86 code from non-x86 verstage ...................................................................... src/*: Update makefiles to exclude x86 code from non-x86 verstage The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b --- M src/arch/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/drivers/pc80/pc/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc 9 files changed, 58 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42062/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0dd8d2b..6446043 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -83,32 +83,24 @@ endef ############################################################################### -# all (bootblock,verstage,romstage,postcar,ramstage) -############################################################################### - -ifeq ($(CONFIG_ARCH_X86),y) - -all-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c -all-y += boot.c -all-y += memcpy.c -all-y += memset.c -all-y += cpu_common.c -all-y += post.c - -endif - -############################################################################### # bootblock ############################################################################### ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) +bootblock-y += boot.c +bootblock-y += post.c +bootblock-y += cpu_common.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +bootblock-y += memcpy.c +bootblock-y += memset.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += id.S +bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c + $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y += bootblock_crt0.S @@ -129,10 +121,16 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += boot.c +verstage-y += post.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +verstage-y += cpu_common.c +verstage-y += memset.c +verstage-y += memcpy.c verstage-y += memmove.c verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c # If verstage is a separate stage it means there's no need @@ -161,16 +159,22 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +romstage-y += boot.c +romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. romstage-y += gdt_init.S romstage-y += cbmem.c +romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +romstage-y += memcpy.c romstage-y += memmove.c +romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= @@ -196,15 +200,21 @@ postcar-generic-ccopts += -D__POSTCAR__ postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +postcar-y += boot.c +postcar-y += post.c postcar-y += gdt_init.S +postcar-y += cpu_common.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += memcpy.c postcar-y += memmove.c +postcar-y += memset.c postcar-y += memlayout.ld postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c LDFLAGS_postcar += -Map $(objcbfs)/postcar.map @@ -229,15 +239,20 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c +ramstage-y += boot.c +ramstage-y += post.c ramstage-y += c_start.S ramstage-y += cpu.c +ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c ramstage-y += memlayout.ld ramstage-y += memmove.c +ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c @@ -248,6 +263,7 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memcpy.c diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 0d11478..a35433e 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -6,7 +6,9 @@ ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += boot_cpu.c +endif romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..3a5ba88 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -2,7 +2,10 @@ romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += earlymtrr.c +verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c +endif bootblock-y += debug.c romstage-y += debug.c @@ -10,4 +13,3 @@ ramstage-y += debug.c bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c -verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 62176d2..7825db8 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += pgtbl.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += pgtbl.c +endif romstage-y += pgtbl.c postcar-y += pgtbl.c ramstage-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index b3925b5..d8f44d9 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,8 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +endif postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 67c40a1..e591dd1 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -7,7 +7,9 @@ romstage-$(CONFIG_SPKMODEM) += spkmodem.c bootblock-y += i8254.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-y += i8254.c +endif romstage-y += i8254.c ramstage-y += i8254.c postcar-y += i8254.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 708631a..27876aa 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index 720a7cb..e9d8612 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,5 +1,7 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +endif romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 558a7ac..c5568d4 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,14 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +ramstage-y += amd_pci_util.c -all-y += amd_pci_mmconf.c +bootblock-y += amd_pci_mmconf.c +ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y) +verstage-y += amd_pci_mmconf.c +endif +romstage-y += amd_pci_mmconf.c +postcar-y += amd_pci_mmconf.c +ramstage-y += amd_pci_mmconf.c +smm-y += amd_pci_mmconf.c + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Gerrit-Change-Number: 42062 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020