May 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: payloads/external/GRUB2: prevent rebuild without actual changes
by Michael Niewöhner (Code Review) May 5, 2020

May 5, 2020

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40955 ) Change subject: payloads/external/GRUB2: prevent rebuild without actual changes ...................................................................... Uploaded patch set 5. -- To view, visit https://review.coreboot.org/c/coreboot/+/40955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5a316d0c9761426ec2ee306d78cd56d4bf19b5 Gerrit-Change-Number: 40955 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Denis Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 22:15:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files again
by Patrick Georgi (Code Review) May 4, 2020

May 4, 2020

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41036 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files again ...................................................................... Patch Set 3: Code-Review+2 The third CR+2 for expedited merging is a bit late, but here it is. -- To view, visit https://review.coreboot.org/c/coreboot/+/41036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Gerrit-Change-Number: 41036 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 04 May 2020 21:25:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_skl: disable serial console by default
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40873 ) Change subject: mb/purism/librem_skl: disable serial console by default ...................................................................... mb/purism/librem_skl: disable serial console by default Librem SKL/KBL boards do not have an exposed serial port interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot librem 13v4 with board defaults + Tianocore Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I4c3f8a3c1726f804957b06b437b399291854a3f5 --- M src/mainboard/purism/librem_skl/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/40873/1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a..4f51d9e 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -73,4 +73,8 @@ config NO_POST default y +config CONSOLE_SERIAL + bool + default n + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3f8a3c1726f804957b06b437b399291854a3f5 Gerrit-Change-Number: 40873 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files again
by 9elements QA (Code Review) May 4, 2020

May 4, 2020

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41036 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files again ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3195 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3194 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3193 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3192 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/41036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Gerrit-Change-Number: 41036 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 04 May 2020 21:00:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_skl: Clean up Kconfig
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40913 ) Change subject: mb/purism/librem_skl: Clean up Kconfig ...................................................................... mb/purism/librem_skl: Clean up Kconfig Reorder Kconfig selects alphabetically, and select the correct SoC based on board selection (even though no actual difference currently). Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I46f651a530ef0ed617dd1f3eee077e84279a40f2 --- M src/mainboard/purism/librem_skl/Kconfig 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/40913/1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 08fa4c7..11bb08d 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,16 +1,17 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n - select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_SKYLAKE - select SPD_READ_BY_WORD select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 + select SOC_INTEL_SKYLAKE if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP if BOARD_PURISM_BASEBOARD_LIBREM_SKL -- To view, visit https://review.coreboot.org/c/coreboot/+/40913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f651a530ef0ed617dd1f3eee077e84279a40f2 Gerrit-Change-Number: 40913 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_skl: rename variant directories
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40912 ) Change subject: mb/purism/librem_skl: rename variant directories ...................................................................... mb/purism/librem_skl: rename variant directories Since the same variant dirs are used by multiple versions of the same board, drop the v2/v3 labels Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856 --- M src/mainboard/purism/librem_skl/Kconfig R src/mainboard/purism/librem_skl/variants/librem13/board_info.txt R src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb R src/mainboard/purism/librem_skl/variants/librem15/board_info.txt R src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb 5 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40912/1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index be4c391..08fa4c7 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -20,8 +20,8 @@ config VARIANT_DIR string - default "librem13v2" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 - default "librem15v3" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 + default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_FAMILY string diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem13/board_info.txt similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem13v2/board_info.txt rename to src/mainboard/purism/librem_skl/variants/librem13/board_info.txt diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb rename to src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem15/board_info.txt similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem15v3/board_info.txt rename to src/mainboard/purism/librem_skl/variants/librem15/board_info.txt diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb similarity index 100% rename from src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb rename to src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/40912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856 Gerrit-Change-Number: 40912 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_skl: Convert to use override devicetree
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40911 ) Change subject: mb/purism/librem_skl: Convert to use override devicetree ...................................................................... mb/purism/librem_skl: Convert to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b --- M src/mainboard/purism/librem_skl/Kconfig R src/mainboard/purism/librem_skl/devicetree.cb A src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb D src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb A src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb 5 files changed, 47 insertions(+), 255 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/40911/1 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a..be4c391 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -39,9 +39,9 @@ string default "purism/librem_skl" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAX_CPUS int diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb similarity index 90% rename from src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb rename to src/mainboard/purism/librem_skl/devicetree.cb index 89e3841..0d511f0 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -164,19 +164,6 @@ register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD - - # OC1 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb new file mode 100644 index 0000000..18ce220 --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/overridetree.cb @@ -0,0 +1,17 @@ +chip soc/intel/skylake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD + + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + + device domain 0 on end +end diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb deleted file mode 100644 index 308688a..0000000 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ /dev/null @@ -1,240 +0,0 @@ -chip soc/intel/skylake - - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" - - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - register "eist_enable" = "1" - - # Set the Thermal Control Circuit (TCC) activaction value to 95C - # even though FSP integration guide says to set it to 100C for SKL-U - # (offset at 0), because when the TCC activates at 100C, the CPU - # will have already shut itself down from overheating protection. - register "tcc_offset" = "5" # TCC of 95C - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_C" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Disable DPTF - register "dptf_enable" = "0" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "0" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" - register "DspEnable" = "0" - register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "PttSwitch" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "0" - - # EC/KBC requires continuous mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # VR Settings Configuration for 4 Domains - #+----------------+-----------+-----------+-------------+----------+ - #| Domain/Setting | SA | IA | GT Unsliced | GT | - #+----------------+-----------+-----------+-------------+----------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | - #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | - #+----------------+-----------+-----------+-------------+----------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), - .voltage_limit = 1520, - .ac_loadline = 1500, - .dc_loadline = 1430, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), - .voltage_limit = 1520, - .ac_loadline = 570, - .dc_loadline = 483, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - .ac_loadline = 520, - .dc_loadline = 420, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), - .voltage_limit = 1520, - .ac_loadline = 520, - .dc_loadline = 420, - }" - - # Enable Root Ports 5 and 9 - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "0" - # ClkReq for NVMe - Bruteforced (no other value works) - register "PcieRpClkReqNumber[8]" = "2" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - - # OC0 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - - # PL2 override 25W - register "tdp_pl2_override" = "25" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 on end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb new file mode 100644 index 0000000..b48ab5b --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/overridetree.cb @@ -0,0 +1,28 @@ +chip soc/intel/skylake + + # Enable CLKREQ# for RP9 + register "PcieRpClkReqSupport[8]" = "0" + # ClkReq for NVMe - Bruteforced (no other value works) + register "PcieRpClkReqNumber[8]" = "2" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + + + device domain 0 on + device pci 1c.4 on end # PCI Express Port 5 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/40911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b Gerrit-Change-Number: 40911 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files again
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41036 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files again ...................................................................... payloads/external/GRUB2: Makefile: fix check for changed files again This fixes the missing closing brace introduced in CB:40953. Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41036 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index bb7b5f8..31b0f53 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -18,7 +18,7 @@ test -d $(project_dir) || git clone $(project_git_repo) $(project_dir) git -C $(project_dir) fetch ifeq ($(shell test -d $(project_dir) && \ - (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain),) + (git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)),) git -C $(project_dir) checkout -f $(TAG-y) else echo "WARNING: index/tree not clean, skipping update / force checkout." -- To view, visit https://review.coreboot.org/c/coreboot/+/41036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Gerrit-Change-Number: 41036 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files again
by Matt DeVillier (Code Review) May 4, 2020

May 4, 2020

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41036 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files again ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Gerrit-Change-Number: 41036 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 May 2020 20:45:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/external/GRUB2: Makefile: fix check for changed files again
by Angel Pons (Code Review) May 4, 2020

May 4, 2020

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41036 ) Change subject: payloads/external/GRUB2: Makefile: fix check for changed files again ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/41036/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41036/1//COMMIT_MSG@9 PS1, Line 9: cb > Mind making this 'cb' uppercase please? You can edit the commit msg from the gerrit UI Done https://review.coreboot.org/c/coreboot/+/41036/1//COMMIT_MSG@9 PS1, Line 9: closig > closing Done -- To view, visit https://review.coreboot.org/c/coreboot/+/41036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Gerrit-Change-Number: 41036 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 04 May 2020 20:36:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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