coreboot-gerrit April 2020

coreboot-gerrit@coreboot.org

1 participants
2501 discussions

Change in coreboot[master]: mb/google/glados: clean up variant devicetrees
by Matt DeVillier (Code Review) 03 Apr '20

03 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39981 ) Change subject: mb/google/glados: clean up variant devicetrees ...................................................................... mb/google/glados: clean up variant devicetrees In preparation for conversion to overridetree format, clean up the variant devicetrees in order to minimize the differences across glados variants. This entails: - minor reformatting and reordering of devicetree entries - addition of setting default values on boards which skipped them - disabling unused I2C2 on boards which left it enabled - setting the TCC offset for all SKL-Y boards - setting VR mailbox command 1 for all SKL-Y boards - skipping init for Uart2 on cave and glados - dropping unused PCIe RP5 for sentry Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb 7 files changed, 92 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/39981/1 diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index 772584d..e1e68ca 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -34,13 +34,23 @@ register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -146,8 +156,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -163,6 +171,9 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 6314af8..00b29b7 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -61,8 +61,14 @@ register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - # TCC offset - register "tcc_offset" = "10" + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" # VR Slew rate setting for improving audible noise register "AcousticNoiseMitigation" = "1" @@ -137,7 +143,7 @@ .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -160,7 +166,7 @@ register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, @@ -177,9 +183,15 @@ # PL2 override 15W register "tdp_pl2_override" = "15" + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" device cpu_cluster 0 on @@ -208,7 +220,7 @@ device i2c 4a on end end end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 1d04a8e..41bb82e 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -167,7 +167,7 @@ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # I2C4 is 1.8V @@ -176,11 +176,12 @@ # PL2 override 15W register "tdp_pl2_override" = "15" - register "tcc_offset" = "10" # TCC of 90C - # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 89f1c08..c0fb07c 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -136,7 +136,7 @@ .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -155,7 +155,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ @@ -172,17 +171,21 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 15W register "tdp_pl2_override" = "15" - register "tcc_offset" = "10" # TCC of 90C - # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" device cpu_cluster 0 on diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 2016625..d63d9c1 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -136,7 +136,7 @@ .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -155,8 +155,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -169,15 +167,21 @@ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 15W register "tdp_pl2_override" = "15" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # TCC of 90C + register "tcc_offset" = "10" + # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 76e614d..419d140 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -9,6 +9,8 @@ register "gpu_pch_backlight_pwm_hz" = "1000" # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" @@ -32,13 +34,23 @@ register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -124,7 +136,7 @@ .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" @@ -143,8 +155,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -160,6 +170,9 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 3e2137b..57586fb 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -34,13 +34,23 @@ register "dptf_enable" = "1" # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" + register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" + register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -126,14 +136,18 @@ .voltage_limit = 1520, }" - # Enable Root port 1 and 5. + # Enable Root port 1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + + # Enable Root port 5 + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # RP 5 uses SRCCLKREQ2# register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 @@ -148,9 +162,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # I2C0 is 3.3V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -166,6 +177,12 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # I2C0 is 3.3V + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + + # I2C4 is 1.8V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + # PL2 override 25W register "tdp_pl2_override" = "25" @@ -263,7 +280,7 @@ device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/39981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I628b20a69fab187e67901c9eb98c0e2ddcb76b0d Gerrit-Change-Number: 39981 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Matt DeVillier (Code Review) 03 Apr '20

03 Apr '20

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default There are boards that do not need a specific domain_vr_config because the defaults provided by the soc code are sufficient. Currently, this means that these boards can't benefit from lower power states (PSI 3 and 4) because the settings default to being disabled since at the time the defaults have been defined (2015) there were bugs in FSP in this regard. Set the default values of psiXenable to 1 for boards that do not have a domain_vr_config setting in their devicetree, just like Cannon Lake does. Boards that have a domain_vr_config and set their specific settings are not affected at all. Currently, there are only three boards that have no domain_vr_config: - supermicro/x11-lga1151-series These boards have a MPS MP2955 which we can assume support for PS3 (the MP2965 and MP2935 support it, too). S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and since only C10 makes use of PS4, those CPUs won't ever request PS4. That means we do not need to disable it explicitly for these boards. - 51nb/x210: Needs testing and/or VR datasheet check for PS3/PS4 support Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Angel Pons: Looks good to me, approved Benjamin Doron: Looks good to me, but someone else must approve diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 98d2513..57c55ec 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -21,15 +21,15 @@ #include <console/console.h> #include <intelblocks/cpulib.h> -/* Default values for domain configuration. PSI3 and PSI4 are disabled. */ +/* Default values for domain configuration. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { [VR_SYSTEM_AGENT] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(4), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -40,8 +40,8 @@ .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -52,8 +52,8 @@ .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, @@ -64,8 +64,8 @@ .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(5), .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 0, - .psi4enable = 0, + .psi3enable = 1, + .psi4enable = 1, .imon_slope = 0, .imon_offset = 0, .icc_max = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/auron: Convert variants to use override devicetree
by Matt DeVillier (Code Review) 03 Apr '20

03 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39940 ) Change subject: mb/google/auron: Convert variants to use override devicetree ...................................................................... mb/google/auron: Convert variants to use override devicetree Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Test: build all auron variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig R src/mainboard/google/auron/devicetree.cb D src/mainboard/google/auron/variants/auron_paine/devicetree.cb A src/mainboard/google/auron/variants/auron_paine/overridetree.cb A src/mainboard/google/auron/variants/auron_yuna/overridetree.cb D src/mainboard/google/auron/variants/buddy/devicetree.cb A src/mainboard/google/auron/variants/buddy/overridetree.cb D src/mainboard/google/auron/variants/gandof/devicetree.cb A src/mainboard/google/auron/variants/gandof/overridetree.cb D src/mainboard/google/auron/variants/lulu/devicetree.cb A src/mainboard/google/auron/variants/lulu/overridetree.cb D src/mainboard/google/auron/variants/samus/devicetree.cb A src/mainboard/google/auron/variants/samus/overridetree.cb 13 files changed, 167 insertions(+), 555 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39940/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 644104a..20d2e44 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -48,9 +48,9 @@ default "Lulu" if BOARD_GOOGLE_LULU default "Samus" if BOARD_GOOGLE_SAMUS -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config EC_GOOGLE_CHROMEEC_BOARDNAME string diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/devicetree.cb similarity index 66% rename from src/mainboard/google/auron/variants/auron_yuna/devicetree.cb rename to src/mainboard/google/auron/devicetree.cb index db02565..35074b4 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -12,14 +12,6 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200" - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b" @@ -44,10 +36,6 @@ register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - # Force enable ASPM for PCIe Port1 register "pcie_port_force_aspm" = "0x01" @@ -61,32 +49,31 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 device pci 15.3 off end # GSPI0 device pci 15.4 off end # GSPI1 device pci 15.5 off end # UART0 device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 17.0 off end # SDIO device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI + device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm @@ -96,8 +83,8 @@ device pnp 0c09.0 on end end end # LPC bridge - device pci 1f.2 on end # SATA Controller + device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + device pci 1f.6 on end # Thermal end end diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb deleted file mode 100644 index f6ec15a..0000000 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ /dev/null @@ -1,103 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb new file mode 100644 index 0000000..6592d9f --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on + device pci 13.0 off end # Smart Sound Audio DSP + end +end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb new file mode 100644 index 0000000..6315e26 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on + device pci 13.0 off end # Smart Sound Audio DSP + end +end diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb deleted file mode 100644 index e12882f..0000000 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ /dev/null @@ -1,110 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - - register "s0ix_enable" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb new file mode 100644 index 0000000..4c47543 --- /dev/null +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -0,0 +1,37 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device domain 0 on + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb deleted file mode 100644 index 230f5bd..0000000 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ /dev/null @@ -1,103 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "500" # 50ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb new file mode 100644 index 0000000..4be90ba1 --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "500" # 50ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on + device pci 13.0 off end # Smart Sound Audio DSP + end +end diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb deleted file mode 100644 index 1983045..0000000 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ /dev/null @@ -1,104 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "70" # 7ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - - register "sio_acpi_mode" = "1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - register "s0ix_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb new file mode 100644 index 0000000..6592d9f --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/broadwell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "70" # 7ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + device domain 0 on + device pci 13.0 off end # Smart Sound Audio DSP + end +end diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb deleted file mode 100644 index 434ecc8..0000000 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ /dev/null @@ -1,107 +0,0 @@ -chip soc/intel/broadwell - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Enable DDI2 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_port0_gen3_tx" = "0x72" - register "sio_acpi_mode" = "1" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" - - # Disable S0ix for now - register "s0ix_enable" = "0" - - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 on end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal - end -end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb new file mode 100644 index 0000000..99b5e693 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -0,0 +1,43 @@ +chip soc/intel/broadwell + + # Enable DDI1 Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Enable DDI2 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + # Disable S0ix + register "s0ix_enable" = "0" + + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" + + device domain 0 on + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c Gerrit-Change-Number: 39940 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 15

Change in coreboot[master]: soc/intel/tigerlake: Add function to dump ME firmware status information
by Philipp Deppenwiese (Code Review) 03 Apr '20

03 Apr '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39127 ) Change subject: soc/intel/tigerlake: Add function to dump ME firmware status information ...................................................................... Patch Set 10: Hey guys. Can we implement this in src/soc/intel/common/block/cse/cse.c instead so we have a common code base. Other we would duplicate the code base -- To view, visit https://review.coreboot.org/c/coreboot/+/39127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Gerrit-Change-Number: 39127 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Apr 2020 15:33:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/pch/lockdown: Lock at end of BS_POST_DEVICE
by Patrick Rudolph (Code Review) 03 Apr '20

03 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39967 ) Change subject: soc/intel/common/pch/lockdown: Lock at end of BS_POST_DEVICE ...................................................................... soc/intel/common/pch/lockdown: Lock at end of BS_POST_DEVICE There's no need to lock it early. Lock it after device initialization was finished. Change-Id: I76cca20bc8dc2a7bdc5f16525919f7ef081df798 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39967/1 diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index de45643..684dcee 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -100,5 +100,4 @@ soc_lockdown_config(chipset_lockdown); } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, - NULL); +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, platform_lockdown_config, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/39967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cca20bc8dc2a7bdc5f16525919f7ef081df798 Gerrit-Change-Number: 39967 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Doc/mb/index.md: Fix mainboard vendor order
by Angel Pons (Code Review) 03 Apr '20

03 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40118 ) Change subject: Doc/mb/index.md: Fix mainboard vendor order ...................................................................... Doc/mb/index.md: Fix mainboard vendor order Oops, Libretrend "stole" all the Thinkpads from Lenovo. Correct that. Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/index.md 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/40118/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 99e5dd0..7637f7b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -75,10 +75,6 @@ - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) -## Libretrend - -- [LT1000](libretrend/lt1000.md) - ### Arrandale series - [T410](lenovo/t410.md) @@ -107,6 +103,10 @@ - [T440p](lenovo/t440p.md) +## Libretrend + +- [LT1000](libretrend/lt1000.md) + ## MSI - [MS-7707](msi/ms7707/ms7707.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/40118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b Gerrit-Change-Number: 40118 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

6 6

Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
by Michał Żygowski (Code Review) 03 Apr '20

03 Apr '20

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/c/coreboot/+/30360/19/Documentation/mainboard/i… File Documentation/mainboard/index.md: https://review.coreboot.org/c/coreboot/+/30360/19/Documentation/mainboard/i… PS19, Line 77: > CB:40118 Sorry, I maintained order by the headers: ## Lenovo > ## Libretrend > ### Nehalem series -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 19 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 13:42:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Michael Niewöhner (Code Review) 03 Apr '20

03 Apr '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 7: > Patch Set 7: > > > Patch Set 7: > > > > > Patch Set 7: Code-Review+2 > > > > > > > Patch Set 7: > > > > > > > > > Patch Set 6: > > > > > > > > > > whoops, looks like I pushed an older patch when I rebased another change, I'll fix that > > > > > > > > Ah, alright. Not a problem (maybe -1 was unnecessary) > > > > > > A -1 is not a blocker. In fact, it's a good way to indicate mild dissatisfaction with a change, as it stands out in a field of green scores. > > > > but -1 is not a thing that should be used just because of a wrong comment IMHO > > There are no real guidelines, what -1 means. So do not interpret too much into it, besides another iteration is needed. -1 scores will get removed with the next iteration, so in my opinion it’s a good way to prevent accidental submission of the change-set. Though, as comments need to be explicitly marked as resolved nowadays, -1 are not needed for that anymore. > Though, as comments need to be explicitly marked as resolved nowadays, Yeah, that's what I actually meant but didn't say :) -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Apr 2020 12:25:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Paul Menzel (Code Review) 03 Apr '20

03 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 7: > Patch Set 7: > > > Patch Set 7: Code-Review+2 > > > > > Patch Set 7: > > > > > > > Patch Set 6: > > > > > > > > whoops, looks like I pushed an older patch when I rebased another change, I'll fix that > > > > > > Ah, alright. Not a problem (maybe -1 was unnecessary) > > > > A -1 is not a blocker. In fact, it's a good way to indicate mild dissatisfaction with a change, as it stands out in a field of green scores. > > but -1 is not a thing that should be used just because of a wrong comment IMHO There are no real guidelines, what -1 means. So do not interpret too much into it, besides another iteration is needed. -1 scores will get removed with the next iteration, so in my opinion it’s a good way to prevent accidental submission of the change-set. Though, as comments need to be explicitly marked as resolved nowadays, -1 are not needed for that anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Apr 2020 11:36:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
by Angel Pons (Code Review) 03 Apr '20

03 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: mb/libretrend/lt1000: Add Libretrend LT1000 mainboard ...................................................................... Patch Set 19: (1 comment) https://review.coreboot.org/c/coreboot/+/30360/19/Documentation/mainboard/i… File Documentation/mainboard/index.md: https://review.coreboot.org/c/coreboot/+/30360/19/Documentation/mainboard/i… PS19, Line 77: > Please maintain order, you stole all the ThinkPads below from Lenovo. CB:40118 -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 19 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 11:27:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2020