coreboot-gerrit April 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload: malloc: Change memcpy() to memmove() in realloc
by Julius Werner (Code Review) 03 Apr '20

03 Apr '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40028 to review the following change. Change subject: libpayload: malloc: Change memcpy() to memmove() in realloc ...................................................................... libpayload: malloc: Change memcpy() to memmove() in realloc Our realloc() works (somewhat suboptimally) by free()ing the existing allocation and then reallocating it wherever it fits. If there was free space before the old location, this means the new allocation may be before the old one, and if the free space block is smaller than the old allocation it may overlap. Thus, we should be moving memmove() instead of memcpy() to move the block over. This is not a problem in practice since all our existing memcpy()s are simple iterate and copy front to back implementations which are safe for overlaps when the destination is in front of the source. but it's still the more correct thing to do (in case we ever change our memcpy()s to do something more advanced or whatever). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 --- M payloads/libpayload/libc/malloc.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/40028/1 diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 1fdb59e..f2a54a7 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -310,8 +310,9 @@ if (ret == NULL || ret == ptr) return ret; - /* Copy the memory to the new location. */ - memcpy(ret, ptr, osize > size ? size : osize); + /* Move the memory to the new location. Might be before the old location + and overlap since the free() above includes a _consolidate(). */ + memmove(ret, ptr, osize > size ? size : osize); return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/40028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 Gerrit-Change-Number: 40028 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/tiogapass: use common GPIO config
by Maxim Polyakov (Code Review) 03 Apr '20

03 Apr '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39427 to look at the new patch set (#25). Change subject: mb/ocp/tiogapass: use common GPIO config ...................................................................... mb/ocp/tiogapass: use common GPIO config According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the common pad configuration from soc/intel/ common, using macros PAD_CFG_ instead of the FSP-style GPIO definitions. This patch adds the GPIO configuration, which has the format required by the driver from common/gpio. The data for this was taken from the inteltool register dump with AMI firmware and converted to macros using intelp2m (pch-pads-parser) [3,4]. [1] https://review.coreboot.org/c/coreboot/+/39425 [2] https://review.coreboot.org/c/coreboot/+/39428 [3] https://review.coreboot.org/c/coreboot/+/35643 [4] https://github.com/maxpoliak/pch-pads-parser Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/Makefile.inc M src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/gpio.h M src/mainboard/ocp/tiogapass/ramstage.c M src/mainboard/ocp/tiogapass/romstage.c 5 files changed, 619 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39427/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/39427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Gerrit-Change-Number: 39427 Gerrit-PatchSet: 25 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Maxim Polyakov (Code Review) 03 Apr '20

03 Apr '20

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39425 to look at the new patch set (#19). Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver Adds definitions that allow to use the common GPIO driver to configure the Lewisburg PCH pads. Using the GPIO configuration from common/gpio, unlike the FSP-style definitions from Intel RefCode [1] definitions, is more understandable and makes the motherboards code much cleaner. In addition, we can use utilities, such as intetool, to analyze the configuration of proprietary firmware to add support for new server motherboards with Skylake-SP processors. The pin layout in this patch corresponds to the driver in the Linux kernel for Lewisburg PCH GPIO hardware [2] [1] https://designintools.intel.com/product_p/stlgrn45.htm [2] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/gpio.c A src/soc/intel/xeon_sp/include/soc/gpio.h A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h M src/soc/intel/xeon_sp/include/soc/pcr_ids.h 5 files changed, 884 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/gma: hook up GMA for Skylake+
by Matt DeVillier (Code Review) 03 Apr '20

03 Apr '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39638 ) Change subject: drivers/intel/gma: hook up GMA for Skylake+ ...................................................................... Patch Set 21: now that CB:39983 has been merged, and CB:40121/40122 pushed, this patchset is really just adding ACPI backlight controls for 3 boards (kunimitsu, librem_skl, and blade_stealth), and can be easily rebased/refactored into 3 tidy patches modeled on 40121/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/39638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2f0e8fe1ef91334d494c8a8605dd46cda80e3d Gerrit-Change-Number: 39638 Gerrit-PatchSet: 21 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 18:44:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Matt DeVillier (Code Review) 03 Apr '20

03 Apr '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 8: > Patch Set 7: > > > A -1 is not a blocker. In fact, it's a good way to indicate mild dissatisfaction with a change, as it stands out in a field of green scores. > > but -1 is not a thing that should be used just because of a wrong comment IMHO I think in this case, a -1 is actually the perfect way to signify that a new patchset had inadvertently reverted a previous change and should not be merged as is, regardless of the triviality of that change. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Apr 2020 18:25:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
by Nico Huber (Code Review) 03 Apr '20

03 Apr '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 ) Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default ...................................................................... Patch Set 8: > > > > > whoops, looks like I pushed an older patch when I rebased another change, I'll fix that > > > > > > > > Ah, alright. Not a problem (maybe -1 was unnecessary) > > > > > > A -1 is not a blocker. In fact, it's a good way to indicate mild dissatisfaction with a change, as it stands out in a field of green scores. > > > > but -1 is not a thing that should be used just because of a wrong comment IMHO > > There are no real guidelines, what -1 means. So do not interpret too much into it, besides another iteration is needed. -1 scores will get removed with the next iteration, so in my opinion it’s a good way to prevent accidental submission of the change-set. Agreed, and also, the -1 has a description: "I would prefer that you didn't submit this". Beside some very rare 1 out of some 100 changes, "this" refers to a patch set, not the change itself. > Though, as comments need to be explicitly marked as resolved nowadays, -1 are not needed for that anymore. ACR has very different mechanics, though. Anyone can mark a comment as resolved, even the change author. But not everyone can remove a -1 (with- out also losing all +2s). Many people mark comments as resolved that really aren't (and comment authors are not notified, unless it's a blunt Done or Ack). Unless we can prevent that, I think -1 is still a very valid choice. -- To view, visit https://review.coreboot.org/c/coreboot/+/39980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748 Gerrit-Change-Number: 39980 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matthew Garrett <mjg59(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Apr 2020 18:18:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Maxim Polyakov (Code Review) 03 Apr '20

03 Apr '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 18: > Patch Set 18: > > we got some preliminary results and they look promising. However we haven't yet have luck with running it under inteltool to see if inteltool picks up all the pads correctly. stay tuned. Ok, thx. Please use inteltool with the latest changes for testing from https://review.coreboot.org/c/coreboot/+/40044 -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 17:51:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Add new Skylake COMe module
by Nico Huber (Code Review) 03 Apr '20

03 Apr '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29480 ) Change subject: mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... Patch Set 30: (1 comment) https://review.coreboot.org/c/coreboot/+/29480/29/src/mainboard/kontron/bsl… File src/mainboard/kontron/bsl6/Kconfig: https://review.coreboot.org/c/coreboot/+/29480/29/src/mainboard/kontron/bsl… PS29, Line 46: config CBFS_SIZE : hex : default 0x600000 > It makes it more tedious to switch between vendor and coreboot, though... In the best case, it shifts convenience from one use case to another. In the worst case, somebody bricks their machine. There is no guarantee that everybody has the same flash layout. It's likely for a laptop, yes, but less likely for some off-the-shelf board and much less likely in the embedded world. And for a COMe module, we don't even know the chip size, one could use a different one on the carrier board. If you want, you can add this default for the Boxer26 variant, but not for the generic one. It's not hardware specific and we are not the board vendor, so we can't say that we know this. -- To view, visit https://review.coreboot.org/c/coreboot/+/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 30 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 17:40:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Andrey Petrov (Code Review) 03 Apr '20

03 Apr '20

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 18: we got some preliminary results and they look promising. However we haven't yet have luck with running it under inteltool to see if inteltool picks up all the pads correctly. stay tuned. -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 17:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/volteer: enable Early Command Training
by Srinidhi N Kaushik (Code Review) 03 Apr '20

03 Apr '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40023 ) Change subject: mb/volteer: enable Early Command Training ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/40023/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40023/5//COMMIT_MSG@11 PS5, Line 11: ECT enabled. > Why is that still an option then, if it’s required? […] This is enabled on all platforms, we had temporarily disabled it until MRC matures. From FSP 2527 we can run with ECT enabled hence this change. I have mentioned ECT = Early Command Training. -- To view, visit https://review.coreboot.org/c/coreboot/+/40023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3 Gerrit-Change-Number: 40023 Gerrit-PatchSet: 5 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Apr 2020 17:17:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit April 2020