coreboot-gerrit April 2020

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Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.
by Srinidhi N Kaushik (Code Review) 04 Apr '20

04 Apr '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40026 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/40026/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40026/5//COMMIT_MSG@9 PS5, Line 9: Update FSP headers for Tiger Lake platform version 2527. > Please summarize the changes. There are no manual changes, these were generated from FSP v 2527 integration. -- To view, visit https://review.coreboot.org/c/coreboot/+/40026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Gerrit-Change-Number: 40026 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 04 Apr 2020 02:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527.
by Srinidhi N Kaushik (Code Review) 04 Apr '20

04 Apr '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40026 to look at the new patch set (#7). Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527. Update FSP headers for Tiger Lake platform generated based FSP version 2527. BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 3 files changed, 110 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40026/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/40026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Gerrit-Change-Number: 40026 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: vendorcode/intel/fsp: Update FSP header for Tiger Lake
by Srinidhi N Kaushik (Code Review) 04 Apr '20

04 Apr '20

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40026 to look at the new patch set (#6). Change subject: vendorcode/intel/fsp: Update FSP header for Tiger Lake ...................................................................... vendorcode/intel/fsp: Update FSP header for Tiger Lake Update FSP headers for Tiger Lake platform version 2527. BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 3 files changed, 110 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40026/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Gerrit-Change-Number: 40026 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/commonlib: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 04 Apr '20

04 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40047 ) Change subject: src/commonlib: Use SPDX for GPL-2.0-only files ...................................................................... src/commonlib: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I29e746115e3b0630238176a0f913a3b5340962eb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/commonlib/cbfs.c M src/commonlib/fsp_relocate.c M src/commonlib/include/commonlib/cbfs.h M src/commonlib/include/commonlib/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/commonlib/include/commonlib/endian.h M src/commonlib/include/commonlib/fsp.h M src/commonlib/include/commonlib/helpers.h M src/commonlib/include/commonlib/iobuf.h M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/include/commonlib/region.h M src/commonlib/include/commonlib/rmodule-defs.h M src/commonlib/include/commonlib/sort.h M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/commonlib/iobuf.c M src/commonlib/mem_pool.c M src/commonlib/region.c M src/commonlib/sort.c 19 files changed, 38 insertions(+), 228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/40047/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index b03a3dc..caa81ea 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <commonlib/cbfs.h> diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index a8b45fa..d9040efa 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <commonlib/endian.h> diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index f5842d9..eb74c4c 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 93d1464..1b4b227 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _CBMEM_ID_H_ #define _CBMEM_ID_H_ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 213d821..3cba43e 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_COREBOOT_TABLES_H #define COMMONLIB_COREBOOT_TABLES_H diff --git a/src/commonlib/include/commonlib/endian.h b/src/commonlib/include/commonlib/endian.h index 3d7ccb1..78c4613 100644 --- a/src/commonlib/include/commonlib/endian.h +++ b/src/commonlib/include/commonlib/endian.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_ENDIAN_H_ #define _COMMONLIB_ENDIAN_H_ diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h index 2ae7949..c36f64b 100644 --- a/src/commonlib/include/commonlib/fsp.h +++ b/src/commonlib/include/commonlib/fsp.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_FSP_H_ #define _COMMONLIB_FSP_H_ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index a5fe87d..eba021a 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_HELPERS_H #define COMMONLIB_HELPERS_H diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index f114ef8..202226a 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef COMMONLIB_IOBUF_H #define COMMONLIB_IOBUF_H diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index ed473eb..4775eaf 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _MEM_POOL_H_ #define _MEM_POOL_H_ diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 47df9b6..86b9ee3 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _REGION_H_ #define _REGION_H_ diff --git a/src/commonlib/include/commonlib/rmodule-defs.h b/src/commonlib/include/commonlib/rmodule-defs.h index de06941..ca04936 100644 --- a/src/commonlib/include/commonlib/rmodule-defs.h +++ b/src/commonlib/include/commonlib/rmodule-defs.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef RMODULE_DEFS_H #define RMODULE_DEFS_H diff --git a/src/commonlib/include/commonlib/sort.h b/src/commonlib/include/commonlib/sort.h index 3d91cd8..3ba00e7 100644 --- a/src/commonlib/include/commonlib/sort.h +++ b/src/commonlib/include/commonlib/sort.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _COMMONLIB_SORT_H_ #define _COMMONLIB_SORT_H_ diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h index 020eb04..84132fa 100644 --- a/src/commonlib/include/commonlib/tcpa_log_serialized.h +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TCPA_LOG_SERIALIZED_H__ #define __TCPA_LOG_SERIALIZED_H__ diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index ca72734..80a8d0b 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __TIMESTAMP_SERIALIZED_H__ #define __TIMESTAMP_SERIALIZED_H__ diff --git a/src/commonlib/iobuf.c b/src/commonlib/iobuf.c index fc0b2ed..a05db01 100644 --- a/src/commonlib/iobuf.c +++ b/src/commonlib/iobuf.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/endian.h> #include <commonlib/iobuf.h> diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index 0aa821b..39bfe71 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <commonlib/mem_pool.h> diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 4a7e285..b1203bc 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <commonlib/region.h> diff --git a/src/commonlib/sort.c b/src/commonlib/sort.c index 98d2db2..cdb94d3 100644 --- a/src/commonlib/sort.c +++ b/src/commonlib/sort.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <commonlib/sort.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/40047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29e746115e3b0630238176a0f913a3b5340962eb Gerrit-Change-Number: 40047 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src/console: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 04 Apr '20

04 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40048 ) Change subject: src/console: Use SPDX for GPL-2.0-only files ...................................................................... src/console: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/console/console.c M src/console/die.c M src/console/init.c M src/console/post.c M src/console/printk.c M src/console/vsprintf.c M src/console/vtxprintf.c 7 files changed, 16 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40048/1 diff --git a/src/console/console.c b/src/console/console.c index a36cb96..e7d74b6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/cbmem_console.h> #include <console/ne2k.h> diff --git a/src/console/die.c b/src/console/die.c index e57c4e4..0d26dfe 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <halt.h> diff --git a/src/console/init.c b/src/console/init.c index 911dbd0..80bdb24 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <console/console.h> diff --git a/src/console/post.c b/src/console/post.c index 6265770..7d6a8ff 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <stdint.h> #include <console/console.h> diff --git a/src/console/printk.c b/src/console/printk.c index 3ef28f3..bbe028b 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * blatantly copied from linux/kernel/printk.c */ diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 78bc09f..bdc7244 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/vtxprintf.h> #include <string.h> diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4045543..6801a97 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + /* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * * vtxprintf.c, originally from linux/lib/vsprintf.c */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9 Gerrit-Change-Number: 40048 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso: Convert TSEG and BERT info to cbmem
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36114 ) Change subject: soc/amd/picasso: Convert TSEG and BERT info to cbmem ...................................................................... soc/amd/picasso: Convert TSEG and BERT info to cbmem Remove the convoluted memory map calculation for cbmem_top() and put the two reserved regions into cbmem. There is no compellng reason to keep these regions above cbmem. AMD can lock any region with Tvalid and the appropriate mask. The memory pointed to by the BERT table simply needs to be reserved from the OS. Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/romstage.c 3 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36114/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index b54a8ef..cf1d2d4 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -41,6 +41,6 @@ #define EARLY_DRAM_MTRR_TOP \ (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) -#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB) +#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB + CONFIG_SMM_TSEG_SIZE) #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4..7b21bb8 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,6 +28,8 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h> +#define BERT_REGION_MAX_SIZE 0x100000 + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); @@ -38,24 +40,19 @@ return biosram_read32(BIOSRAM_CBMEM_TOP); } -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - void bert_reserved_region(void **start, size_t *size) { - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; + const struct cbmem_entry *bert; + + *start = 0; + *size = 0; + + bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); + if (!bert) + return; + + *start = cbmem_entry_start(bert); + *size = cbmem_entry_size(bert); } void *cbmem_top(void) @@ -66,19 +63,7 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); -} - -static uintptr_t smm_region_start(void) -{ - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; + return (void *)ALIGN_DOWN(restore_top_of_low_cacheable(), 8 * MiB); } /* @@ -106,12 +91,39 @@ void smm_region(uintptr_t *start, size_t *size) { static int once; + const struct cbmem_entry *smm; - *start = smm_region_start(); - *size = smm_region_size(); + *start = 0; + *size = 0; + + smm = cbmem_entry_find(CBMEM_ID_SMM_TSEG_SPACE); + if (!smm) + return; + + *start = ALIGN_UP((uintptr_t)cbmem_entry_start(smm), CONFIG_SMM_TSEG_SIZE); + *size = CONFIG_SMM_TSEG_SIZE; if (!once) { clear_tvalid(); once = 1; } } + +/* Add or find TSEG and BERT storage prior to ramstage. ramstage may need + * to be recovered from cached space in TSEG. BERT storage is consumed at + * ROMSTAGE_CBMEM_INIT_HOOK and ordering can't be enforced for a hook. + */ +static void alloc_reserved_in_cbmem(int unused) +{ + void *p; + + /* Make large enough so TSEG can have alignment = size, allowing a + * good mask. + */ + p = cbmem_add(CBMEM_ID_SMM_TSEG_SPACE, 2 * CONFIG_SMM_TSEG_SIZE); + + if (CONFIG(ACPI_BERT)) + p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, BERT_REGION_MAX_SIZE); +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_reserved_in_cbmem) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index eb39cc4..f4ae24b 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -78,27 +78,24 @@ static void set_mtrrs_for_ramstage(void) { - uintptr_t smm_base; - size_t smm_size; - uintptr_t smm_top; uintptr_t mem_top; uintptr_t ramstage_wb_base; size_t ramstage_wb_size; int mtrr; - smm_region(&smm_base, &smm_size); - smm_top = smm_base + smm_size; - mem_top = (uintptr_t)cbmem_top(); - /* Cache anticipated ramstage location through the top of TSEG */ - ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; - ramstage_wb_size = smm_top - ramstage_wb_base; + /* Cache anticipated ramstage location through the top of cbmem. + * Unlike some other implementations, TSEG is in cbmem so it will + * be cached as well. + */ + ramstage_wb_size = EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_base = mem_top - ramstage_wb_size; - /* Make sure MTRR base and size are usable */ + /* Ensure base and size are usable in a single MTRR pair */ if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); - ramstage_wb_base = smm_top - ramstage_wb_size; + ramstage_wb_base = mem_top - ramstage_wb_size; } if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Gerrit-Change-Number: 36114 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd/picasso: Add basic MTRR settings to hybrid romstage
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35297 ) Change subject: soc/amd/picasso: Add basic MTRR settings to hybrid romstage ...................................................................... soc/amd/picasso: Add basic MTRR settings to hybrid romstage Program the system flash as WP to allow it to be cacheable. This was done during bootblock on previous systems. Since this code and its data are in DRAM, set them to WP. Prior to running ramstage, set its anticipated target location as WP also. Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35297/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 66e6650..15f319f 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -25,8 +25,18 @@ #define ROMSTAGE_SIZE (64 * KiB) /* Enforced by Makefile.inc for PSP info */ #define ROMSTAGE_TOP (CONFIG_ROMSTAGE_ADDR + ROMSTAGE_SIZE) +#define EARLYRAM_TOP (ROMSTAGE_TOP + CONFIG_EARLYRAM_SIZE) #if ROMSTAGE_TOP & 0xffff # error Top of the BIOS binary image must be 64KB aligned #endif +#define EARLY_DRAM_MTRR_BASE \ + ALIGN_DOWN(CONFIG_ROMSTAGE_ADDR, 32 * MiB) +#define EARLY_DRAM_MTRR_SIZE \ + ALIGN_UP(ROMSTAGE_SIZE + CONFIG_EARLYRAM_SIZE, 32 * MiB) +#define EARLY_DRAM_MTRR_TOP \ + (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) + +#define EARLY_RAMSTAGE_MTRR_SZ (16 * MiB) + #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 92361f9..b4c8013 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,8 +21,10 @@ #include <delay.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/x86/bist.h> +#include <cpu/amd/mtrr.h> #include <cpu/amd/msr.h> #include <cbmem.h> #include <console/console.h> @@ -56,10 +58,68 @@ fch_early_init(); } +static int set_early_mtrrs(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, EARLY_DRAM_MTRR_BASE, EARLY_DRAM_MTRR_SIZE, + MTRR_TYPE_WRBACK); + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + return 0; +} + +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t smm_base; + size_t smm_size; + uintptr_t smm_top; + uintptr_t mem_top; + uintptr_t ramstage_wb_base; + size_t ramstage_wb_size; + int mtrr; + + smm_region(&smm_base, &smm_size); + smm_top = smm_base + smm_size; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of TSEG */ + ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_size = smm_top - ramstage_wb_base; + + /* Make sure MTRR base and size are usable */ + if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { + ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); + ramstage_wb_base = smm_top - ramstage_wb_size; + } + if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { + printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); + return; + } + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, ramstage_wb_base, ramstage_wb_size, + MTRR_TYPE_WRBACK); + else + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); +} + asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc) { uintptr_t top_of_mem; int s3_resume; + int early_mtrr_err; post_code(0x40); if (CONFIG(COLLECT_TIMESTAMPS)) { @@ -70,6 +130,7 @@ /* Many of these tasks typically happen in bootblock, but execution * begins in romstage for this device. */ post_code(0x41); + early_mtrr_err = set_early_mtrrs(); post_code(0x42); romstage_soc_early_init(); @@ -96,6 +157,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + if (early_mtrr_err) + printk(BIOS_WARNING, "Early MTRRs were not set properly\n"); + post_code(0x48); if (!s3_resume && CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); @@ -111,6 +175,7 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x4b); + set_mtrrs_for_ramstage(); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Gerrit-Change-Number: 35297 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Support reset vector in romstage
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Support reset vector in romstage ...................................................................... Abandoned We're no longer planning to begin in romstage. Solution will only begin with bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 20 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37491 ) Change subject: x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM ...................................................................... x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM In continuing the flexibility of RESET_VECTOR_IN_RAM, add Kconfig options for declaring whether the first stage of execution is bootblock or romstage. For the romstage version, rely on the existing x86 reset vector handling and initialization, as well as assembly_entry.S (previously intended only to reinitialize the x86's basic settings in early stages). Add a new function to be called earlyram_stage_entry() that transmits the BIST information to be checked. Adjust linker scripts accordingly. Note that flipping the default build to a hybrid romstage arrangement is intentional. Implementations intending to use a traditional bootblock should select RESET_VECTOR_IN_RAM_BOOTBLOCK. Sample build using amd/mandolin (currently WIP): Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/ramstage 0x80 stage 76100 none config 0x12a00 raw 364 none revision 0x12bc0 raw 674 none payload_config 0x12ec0 raw 1593 none payload_revision 0x13540 raw 262 none (empty) 0x136c0 null 1752 none fspm.bin 0x13dc0 fsp 786432 none (empty) 0xd3e00 null 3992 none fsps.bin 0xd4dc0 fsp 262144 none pci1002,15d8.rom 0x114e00 optionrom 54272 none fallback/dsdt.aml 0x122280 raw 8365 none fallback/payload 0x124380 simple elf 68099 none (empty) 0x134dc0 null 2928536 none bootblock 0x3ffd80 bootblock 64 none readelf of build/cbfs/fallback/romstage.elf: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 08000000 001000 007c20 00 AX 0 0 32 [ 2] .rel.text REL 00000000 0838f4 001ac0 08 I 9 1 4 [ 3] .earlyram.data NOBITS 0802d000 008c20 045ed8 00 WA 0 0 32 [ 4] .near_reset_vecto PROGBITS 0807f000 080000 0000c8 00 AX 0 0 4096 [ 5] .rel.near_reset_v REL 00000000 0853b4 000058 08 I 9 4 4 [ 6] .reset PROGBITS 0807fff0 080ff0 000010 00 AX 0 0 1 [ 7] .rel.reset REL 00000000 08540c 000008 08 I 9 6 4 [ 8] .gnu_debuglink PROGBITS 00000000 081000 000014 00 0 0 4 [ 9] .symtab SYMTAB 00000000 081014 001590 10 10 122 4 [10] .strtab STRTAB 00000000 0825a4 001350 00 0 0 1 [11] .shstrtab STRTAB 00000000 085414 000065 00 0 0 1 167: 0802d000 0 NOTYPE GLOBAL DEFAULT 3 _earlyram_stack 134: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _eearlyram_stack 274: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _preram_cbmem_console 310: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _epreram_cbmem_console 202: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _timestamp 335: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _etimestamp 244: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _bss 216: 08072ed8 0 NOTYPE GLOBAL DEFAULT 3 _ebss Change-Id: Ida2bc90fdd3e953445065929124adaa168164250 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/memlayout.ld M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/cpu/x86/32bit/entry32.inc 9 files changed, 57 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37491/1 diff --git a/Makefile.inc b/Makefile.inc index e4defc1..6a11ae8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1153,6 +1153,8 @@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE),y) + cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -1192,6 +1194,7 @@ ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) $(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB) endif +endif # !CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0547193..467dbf2 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -106,6 +106,23 @@ The first stage executed may be a bootblock, or a hybrid romstage, combining certain elements of bootblock and romstage. +config RESET_VECTOR_IN_RAM_BOOTBLOCK + bool + depends on RESET_VECTOR_IN_RAM + select HAVE_BOOTBLOCK + help + Build a traditional bootblock that begins execution in RAM. This + implementation uses a C environment, and romcc is not supported. + +config RESET_VECTOR_IN_RAM_ROMSTAGE + bool + depends on RESET_VECTOR_IN_RAM + default !RESET_VECTOR_IN_RAM_BOOTBLOCK + help + Build a hybrid romstage, combining the bootblock operations of + bringing the x86 online and setting flat protected mode, with the + romstage operations of determining memory setup and bring up cbmem. + # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c351..973ef65 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -224,8 +224,10 @@ # gdt_init.S is included by entry32.inc when romstage is the first C # environment. ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +ifneq ($(CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE),y) romstage-y += gdt_init.S endif +endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 273045a..56f18f8 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -28,12 +28,19 @@ #define _STACK_TOP _ecar_stack #endif -.section ".text._start", "ax", @progbits -.global _start -_start: +#if CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) + #include <arch/x86/prologue.inc> + #include <cpu/x86/16bit/entry16.inc> + #include <cpu/x86/16bit/reset16.inc> /* includes _start symbol */ + #include <cpu/x86/32bit/entry32.inc> /* includes gdt_init */ +#else + .section ".text._start", "ax", @progbits + .global _start + _start: /* Migrate GDT to this text segment */ call gdt_init +#endif /* reset stack pointer to CAR stack */ mov $_STACK_TOP, %esp @@ -62,7 +69,14 @@ #if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif + +#if CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) + subl $12, %esp + pushl %ebp /* BIST value */ + call earlyram_stage_entry +#else call car_stage_entry +#endif /* Expect to never return. */ 1: diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..22fcce8 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -293,6 +293,13 @@ */ asmlinkage void car_stage_entry(void); +/* + * A system using RESET_VECTOR_IN_RAM_ROMSTAGE eliminates bootblock and calls + * earlyram_stage_entry() as the platform's entry point. + * entry point. + */ +asmlinkage void earlyram_stage_entry(uint32_t bist); + #endif /* diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 978925f..b7a1891 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -60,12 +60,14 @@ #endif } -#if ENV_BOOTBLOCK +#if (ENV_BOOTBLOCK || (CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) && ENV_ROMSTAGE)) /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> +#if ENV_BOOTBLOCK #include <arch/x86/id.ld> +#endif #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif -#endif /* ENV_BOOTBLOCK */ +#endif /* ENV_BOOTBLOCK || (CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) && ENV_ROMSTAGE) */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2aa8240..0dca67e 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,7 +29,8 @@ #include <arch/rom_segs.h> -#if (!CONFIG(ROMCC_BOOTBLOCK) && CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000) +#if ((!CONFIG(ROMCC_BOOTBLOCK) && (CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000)) \ + || CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE)) .section ".near_reset_vector", "ax", @progbits #endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index 28893c6..4c4bdcb 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -14,7 +14,8 @@ /* _RESET_VECTOR: typically the top of the ROM */ SECTIONS { -#if (!CONFIG(ROMCC_BOOTBLOCK) && CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000) +#if ((!CONFIG(ROMCC_BOOTBLOCK) && (CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000)) \ + || CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE)) /* Trigger an error if I have an unuseable start address */ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 52c0768..7f60ca5 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -13,6 +13,8 @@ /* For starting coreboot in protected mode */ +#define _START_IN_ENTRY32 (!ENV_BOOTBLOCK && !CONFIG(RESET_VECTOR_IN_RAM)) + #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> #include <arch/x86/gdt_init.S> @@ -35,7 +37,7 @@ * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK +#if _START_IN_ENTRY32 .globl _start _start: #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida2bc90fdd3e953445065929124adaa168164250 Gerrit-Change-Number: 37491 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: Add Intel SkyLake Scalable Processor support
by Jonathan Zhang (Code Review) 03 Apr '20

03 Apr '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38548 ) Change subject: Add Intel SkyLake Scalable Processor support ...................................................................... Add Intel SkyLake Scalable Processor support This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family. The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,799 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Gerrit-Change-Number: 38548 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2020