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Change in coreboot[master]: mb/google/eve: Use ACPI backlight controls
by Matt DeVillier (Code Review) 05 Apr '20

05 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40122 ) Change subject: mb/google/eve: Use ACPI backlight controls ...................................................................... mb/google/eve: Use ACPI backlight controls Enables backlight control under Windows. Test: build/boot eve, verify screen backlight controls available and functional under Windows 10. Change-Id: Id4477d2ec71aefb4c9d2ead31cd5fd3bfad51981 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/eve/dsdt.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40122/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 50f9114..564b45d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "100" register "gpu_pp_down_delay_ms" = "500" register "gpu_pp_cycle_delay_ms" = "500" diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index ea0424a..8b07dab 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -39,6 +39,7 @@ { #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4477d2ec71aefb4c9d2ead31cd5fd3bfad51981 Gerrit-Change-Number: 40122 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism: Remove unused ACPI generic sleep button device SLPB
by Paul Menzel (Code Review) 05 Apr '20

05 Apr '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40221 ) Change subject: mb/purism: Remove unused ACPI generic sleep button device SLPB ...................................................................... mb/purism: Remove unused ACPI generic sleep button device SLPB The Puri.sm devices use the dual-button model, where the power button generates a soft-off transition request and a sleep button (function key for ESC key) generates a sleep transition request. But the fixed hardware sleep button with its event programming model in the PM1x_EVT_BLK is used. For this to work the flag SLEEP_BUTTON in the FADT has to be cleared. Change-Id: I533818d106703b1dda745ceb633129661ac61cdf Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/purism/librem_bdw/acpi/mainboard.asl M src/mainboard/purism/librem_skl/acpi/mainboard.asl 2 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40221/1 diff --git a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl index 8aaf285..b160e28 100644 --- a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl @@ -17,14 +17,4 @@ Return (\_SB.PCI0.LPCB.EC.LIDS) } } - - Device (SLPB) - { - Name (_HID, EisaId ("PNP0C0E")) - - Method (_STA) - { - Return (0xF) - } - } } diff --git a/src/mainboard/purism/librem_skl/acpi/mainboard.asl b/src/mainboard/purism/librem_skl/acpi/mainboard.asl index 8aaf285..b160e28 100644 --- a/src/mainboard/purism/librem_skl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_skl/acpi/mainboard.asl @@ -17,14 +17,4 @@ Return (\_SB.PCI0.LPCB.EC.LIDS) } } - - Device (SLPB) - { - Name (_HID, EisaId ("PNP0C0E")) - - Method (_STA) - { - Return (0xF) - } - } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533818d106703b1dda745ceb633129661ac61cdf Gerrit-Change-Number: 40221 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/glados: Use ACPI brightness controls
by Matt DeVillier (Code Review) 05 Apr '20

05 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40121 ) Change subject: mb/google/glados: Use ACPI brightness controls ...................................................................... mb/google/glados: Use ACPI brightness controls Enables ACPI backlight controls under Windows. Test: build/boot chell variant, verify screen backlight controls available and functional under Windows 10. Change-Id: Ida0102ac828254ae195528a8f1de078abed4a491 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/glados/dsdt.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40121/1 diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index e9c1cac..4e85e21 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/skylake + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_pp_up_delay_ms" = "200" register "gpu_pp_down_delay_ms" = " 50" register "gpu_pp_cycle_delay_ms" = "500" diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 879e888..7e3a1a2 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -35,6 +35,7 @@ { #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } // Dynamic Platform Thermal Framework -- To view, visit https://review.coreboot.org/c/coreboot/+/40121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0102ac828254ae195528a8f1de078abed4a491 Gerrit-Change-Number: 40121 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cyan: Use ACPI backlight contrls
by Matt DeVillier (Code Review) 05 Apr '20

05 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40120 ) Change subject: mb/google/cyan: Use ACPI backlight contrls ...................................................................... mb/google/cyan: Use ACPI backlight contrls Enables ACPI backlight controls under Windows. Test: boot Win 10 on cyan and edgar variants, verify screen backlight controls available and functional. Change-Id: I8976291b5bafaec934d0bfd91fcdab50b381beec Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/devicetree.cb M src/mainboard/google/cyan/dsdt.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40120/1 diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index b13f3f9..91e9795 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/braswell + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + ############################################################ # Set the parameters for MemoryInit ############################################################ diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index 90dfa37..f9f4940 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -33,6 +33,7 @@ Device (PCI0) { #include <acpi/southcluster.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #if CONFIG(BOARD_GOOGLE_TERRA) #include <variant/acpi/cpu.asl> #else -- To view, visit https://review.coreboot.org/c/coreboot/+/40120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8976291b5bafaec934d0bfd91fcdab50b381beec Gerrit-Change-Number: 40120 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/rambi: use ACPI backlight controls
by Matt DeVillier (Code Review) 05 Apr '20

05 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40119 ) Change subject: mb/google/rambi: use ACPI backlight controls ...................................................................... mb/google/rambi: use ACPI backlight controls All variants except NINJA have a built-in display. Enables ACPI brightness controls under Windows. Change-Id: I8dd026608de606fa33f28ccb2967f3beb83b3470 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/rambi/devicetree.cb M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/rambi/variants/ninja/overridetree.cb 3 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/40119/1 diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index dc11ec8..c7bc0b6 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/baytrail + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # SATA port enable mask (2 ports) register "sata_port_map" = "0x1" register "sata_ahci" = "0x1" diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 3a8d1a1..347269f 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -36,6 +36,7 @@ { //#include <soc/intel/baytrail/acpi/northcluster.asl> #include <soc/intel/baytrail/acpi/southcluster.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } /* Dynamic Platform Thermal Framework */ diff --git a/src/mainboard/google/rambi/variants/ninja/overridetree.cb b/src/mainboard/google/rambi/variants/ninja/overridetree.cb index 3f67644..47527da 100644 --- a/src/mainboard/google/rambi/variants/ninja/overridetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/overridetree.cb @@ -1,5 +1,8 @@ chip soc/intel/baytrail + # No Built-in IGD Display + register "gfx.ndid" = "0" + register "usb2_comp_bg" = "0x4700" # Allow PCIe devices to wake system from suspend -- To view, visit https://review.coreboot.org/c/coreboot/+/40119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd026608de606fa33f28ccb2967f3beb83b3470 Gerrit-Change-Number: 40119 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Improve code formatting
by HAOUAS Elyes (Code Review) 05 Apr '20

05 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40127 ) Change subject: sb/intel/i82801gx: Improve code formatting ...................................................................... sb/intel/i82801gx: Improve code formatting Change-Id: Ia75c3ca7136b0291b3ae82e6a281cc76b75965ca Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c 10 files changed, 38 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/40127/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 9e34912..4b698dc 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -41,9 +41,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -111,9 +109,7 @@ static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -127,9 +123,8 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) @@ -141,14 +136,12 @@ reg32 |= (1 << 0) | (1 << 1); write32(base + 0x68, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 45844c4..a58e02d 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -33,8 +33,7 @@ return -1; /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -60,8 +59,7 @@ return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 0be9e28..d96082c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -73,8 +73,7 @@ /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ce5d82f..7f49c4b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -64,8 +64,7 @@ static void i82801gx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); } /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control @@ -141,9 +140,7 @@ config_t *config = dev->chip_info; u32 reg32 = 0; - /* An array would be much nicer here, or some - * other method of doing this. - */ + /* An array would be much nicer here, or some other method of doing this. */ reg32 |= (config->gpi0_routing & 0x03) << 0; reg32 |= (config->gpi1_routing & 0x03) << 2; reg32 |= (config->gpi2_routing & 0x03) << 4; @@ -423,8 +420,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) @@ -687,14 +683,13 @@ .final = lpc_final, }; -/* 27b0: 82801GH (ICH7 DH) */ -/* 27b8: 82801GB/GR (ICH7/ICH7R) */ -/* 27b9: 82801GBM/GU (ICH7-M/ICH7-U) */ -/* 27bc: 82NM10 (NM10) */ -/* 27bd: 82801GHM (ICH7-M DH) */ - static const unsigned short pci_device_ids[] = { - 0x27b0, 0x27b8, 0x27b9, 0x27bc, 0x27bd, 0 + 0x27b0, /* 82801GH (ICH7 DH) */ + 0x27b8, /* 82801GB/GR (ICH7/ICH7R) */ + 0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */ + 0x27bc, /* 82NM10 (NM10) */ + 0x27bd, /* 82801GHM (ICH7-M DH) */ + 0 }; static const struct pci_driver ich7_lpc __pci_driver = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 8ebbd81..6f9242c 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -141,8 +141,7 @@ rp = root_port_number(dev); if (rp > rpc.num_ports) { - printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", - rp, rpc.num_ports); + printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports); return; } @@ -182,8 +181,7 @@ int coalesce = 0; if (dev->chip_info != NULL) { - struct southbridge_intel_i82801gx_config *config - = dev->chip_info; + struct southbridge_intel_i82801gx_config *config = dev->chip_info; coalesce = config->pcie_port_coalesce; } @@ -196,16 +194,14 @@ pcie_dev = rpc.ports[i]; if (pcie_dev == NULL) { - printk(BIOS_ERR, "Root Port %d device is NULL?\n", - i + 1); + printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1); continue; } if (pcie_dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", - dev_path(pcie_dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev)); /* Disable this device if possible */ i82801gx_enable(pcie_dev); @@ -234,8 +230,7 @@ } } - printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; } diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index df8acf5..526c1de 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -40,8 +40,7 @@ case 0x27bc: return 0x3; default: - printk(BIOS_ERR, - "i82801gx_sata: error: cannot determine port config\n"); + printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n"); return 0; } } @@ -66,11 +65,9 @@ & AHCI_UNSUPPORTED); if (!ahci_supported) { - /* Fallback to IDE PLAIN for sata for the rest of the - initialization */ + /* Fallback to IDE PLAIN for sata for the rest of the initialization */ config->sata_mode = SATA_MODE_IDE_PLAIN; - printk(BIOS_DEBUG, - "AHCI not supported, falling back to plain mode.\n"); + printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n"); } } @@ -78,12 +75,10 @@ if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) - & ~0xc3) | 0x40); + (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); } else { /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, - pci_read_config8(dev, SATA_MAP) & ~0xc3); + pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -155,8 +150,7 @@ struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); break; default: case SATA_MODE_IDE_PLAIN: @@ -231,7 +225,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index fb15ba5..d2371d6 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -46,8 +46,7 @@ return do_smbus_write_byte(res->base, device, address, data); } -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, - const u8 *buf) +static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) { u16 device; struct resource *res; @@ -74,9 +73,9 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, }; static struct pci_operations smbus_pci_ops = { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f8c8bec..fa6c534 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -30,15 +30,11 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ +/* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ +/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */ global_nvs_t *gnvs = (global_nvs_t *)0x0; void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index ea83579..13a8737 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -43,7 +43,7 @@ } static struct pci_operations usb_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f8eba8e..5278c16 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -58,8 +58,7 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; -- To view, visit https://review.coreboot.org/c/coreboot/+/40127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia75c3ca7136b0291b3ae82e6a281cc76b75965ca Gerrit-Change-Number: 40127 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: src: Use 'scan_bus = NULL' instead of 'scan_bus = 0'
by HAOUAS Elyes (Code Review) 05 Apr '20

05 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40126 ) Change subject: src: Use 'scan_bus = NULL' instead of 'scan_bus = 0' ...................................................................... src: Use 'scan_bus = NULL' instead of 'scan_bus = 0' Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/device/device.c M src/device/pci_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/dec/21143/21143.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/intel/i210/i210.c M src/drivers/net/atl1e.c M src/drivers/net/ne2k.c M src/drivers/net/r8168.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie.c M src/drivers/xgi/z9s/z9s.c M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/pi/00630F01/iommu.c M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/sandybridge/northbridge.c M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/xhci.c M src/soc/nvidia/tegra124/soc.c M src/soc/rockchip/rk3288/soc.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/usb.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/ide.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/nic.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/ti/pci1x2x/pci1x2x.c 82 files changed, 91 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40126/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 519d461..e2722ef 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -261,6 +261,6 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_audio_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_audio_pci_ops, }; diff --git a/src/device/device.c b/src/device/device.c index 236b768..dffcc18 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -918,7 +918,7 @@ while (do_scan_bus) { struct bus *link; busdev->ops->scan_bus(busdev); - do_scan_bus = 0; + do_scan_bus = NULL; for (link = busdev->link_list; link; link = link->next) { if (link->reset_needed) { if (reset_bus(link)) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 0cbb02d..ec6502a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -771,7 +771,7 @@ .acpi_fill_ssdt = pci_rom_ssdt, #endif .init = pci_dev_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 8bc7307..aec27dc 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -67,7 +67,7 @@ .set_resources = aspeed_ast2050_set_resources, .enable_resources = pci_dev_enable_resources, .init = aspeed_ast2050_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver aspeed_ast2050_driver __pci_driver = { diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 0230935..76169bb 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -43,7 +43,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = dec_21143_enable, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver dec_21143_driver __pci_driver = { diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d9e4ce1..7b9c58c 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -140,7 +140,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = bochs_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver qemu_stdvga_driver __pci_driver = { diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 6b1968c..252f0b5 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -340,7 +340,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = cirrus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver qemu_cirrus_driver __pci_driver = { diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 232a826..77eed4b 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -228,7 +228,7 @@ .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = 0, }; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 51470b0..339955e 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -162,7 +162,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = atl1e_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver atl1e_driver __pci_driver = { diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index b1d72de..f3cbfdd 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -318,7 +318,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver ne2k_driver __pci_driver = { diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index c764b43..6d73eb7 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -372,7 +372,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = r8168_init, - .scan_bus = 0, + .scan_bus = NULL, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = r8168_net_acpi_name, .acpi_fill_ssdt = r8168_net_fill_ssdt, diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index fd42582..fca766f 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -58,7 +58,7 @@ .enable_resources = pci_dev_enable_resources, .init = rce822_init, .enable = rce822_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 355e0f9..c6e9f22 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -158,7 +158,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nc_fpga_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = 0, }; diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index c38e642..a119683 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -38,7 +38,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = si_sata_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver si_sata_driver __pci_driver = { diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 999c6ba..b29b72a 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -52,7 +52,7 @@ .set_resources = oxford_oxpcie_set_resources, .enable_resources = pci_dev_enable_resources, .init = oxford_oxpcie_enable, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver oxford_oxpcie_driver __pci_driver = { diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 62c80aa..afbbd11 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -50,7 +50,7 @@ .set_resources = xgi_z9s_set_resources, .enable_resources = pci_dev_enable_resources, .init = xgi_z9s_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver xgi_z9s_driver __pci_driver = { diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index a7bf958..cf796df 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -57,7 +57,7 @@ .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c index 77eea90..d23ef55 100644 --- a/src/northbridge/amd/pi/00630F01/iommu.c +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -57,7 +57,7 @@ .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index a9f6f97..729b8d2 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -47,7 +47,7 @@ .set_resources = iommu_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 074f63a..1eb613d 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -96,7 +96,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 0bbd3d5..c26ee27 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -267,7 +267,7 @@ .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 9484cd9..1d07805 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -242,7 +242,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index d23a843..eefd03f 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -97,7 +97,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index f5a964a..9b2df13 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -816,7 +816,7 @@ .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, @@ -830,7 +830,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func1_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = &gma_pci_ops, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 16cf5e6..b003423 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -196,7 +196,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = generate_cpu_entries, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &intel_pci_ops, }; @@ -216,7 +216,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 6dbc156..a05a0a0 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -257,7 +257,7 @@ .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = &gma_pci_ops, .write_acpi_tables = gma_write_acpi_tables, diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4637175..39558ab 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -256,7 +256,7 @@ .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &intel_pci_ops, }; @@ -271,7 +271,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ff5d7f2..4bd0a7a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -466,7 +466,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 73a680e..0492ae9 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -69,7 +69,7 @@ .read_resources = pci_csme_ie_kt_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, + .scan_bus = NULL, .init = 0, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/npk.c b/src/soc/intel/denverton_ns/npk.c index ce57686..98ea556 100644 --- a/src/soc/intel/denverton_ns/npk.c +++ b/src/soc/intel/denverton_ns/npk.c @@ -37,7 +37,7 @@ .read_resources = pci_npk_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, + .scan_bus = NULL, .init = npk_init, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 7027e1e..983d382 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -104,7 +104,7 @@ .read_resources = pci_pmc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, + .scan_bus = NULL, .init = pmc_init, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 9097526..ad4dcfa 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -65,7 +65,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 7c6e889..f51203f 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -39,7 +39,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, .enable = pci_dev_enable_resources, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index f2e2c0a..fbe1318 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -57,7 +57,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = soc_enable, .init = soc_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_tegra124_dev(struct device *dev) diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 09cd7bc..aa58a44 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -38,7 +38,7 @@ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .init = soc_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_rk3288_dev(struct device *dev) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 4523964..62300ba 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -127,7 +127,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = cpu_enable, .init = cpu_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_exynos5250_dev(struct device *dev) diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index bcc6878..a9b1fee 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -157,7 +157,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = cpu_enable, .init = cpu_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_exynos5420_dev(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 3acbdf0..5568966 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -31,7 +31,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 69d9591..292e80d 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -30,7 +30,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index 2ca8591..ace1dc7 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -60,7 +60,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index 0da7631..ffc3692 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -54,7 +54,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver sd_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index c634830..6107c75 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -31,7 +31,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index f8773fc..21bc5da 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -181,7 +181,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ahci_raid_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; @@ -207,7 +207,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; @@ -238,7 +238,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; @@ -254,7 +254,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 49d1ddf..e8cc360 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -37,7 +37,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = hda_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 69d9591..292e80d 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -30,7 +30,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 58e0c57..9693cff 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -60,7 +60,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index 01a2343..95f2f52 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -55,7 +55,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .scan_bus = 0, + .scan_bus = NULL, }; static const struct pci_driver sd_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index e465c14..766f479 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -31,7 +31,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15178cb..633fc9e 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -344,7 +344,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, .acpi_name = azalia_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 4d2ac1c..35a2555 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -258,7 +258,7 @@ .acpi_fill_ssdt = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, .acpi_name = sata_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 26d2bd1..3508f7b 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -109,7 +109,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, .acpi_name = usb_ehci_acpi_name, }; diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 7af3b08f..634bd8a 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -65,7 +65,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_xhci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &xhci_pci_ops, .acpi_name = xhci_acpi_name, }; diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index b21887f..74f07b1 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -146,7 +146,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init_i82371fb_sb, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; @@ -157,7 +157,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init_i82371ab_eb_mb, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; diff --git a/src/southbridge/intel/i82371eb/usb.c b/src/southbridge/intel/i82371eb/usb.c index d4fffa4..b57004a 100644 --- a/src/southbridge/intel/i82371eb/usb.c +++ b/src/southbridge/intel/i82371eb/usb.c @@ -37,7 +37,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index ba17b7e..adb3688 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -253,7 +253,7 @@ .enable_resources = pci_dev_enable_resources, .enable = i82801dx_enable, .init = ac97_audio_init, - .scan_bus = 0, + .scan_bus = NULL, }; static struct device_operations ac97_modem_ops = { @@ -262,7 +262,7 @@ .enable_resources = pci_dev_enable_resources, .enable = i82801dx_enable, .init = ac97_modem_init, - .scan_bus = 0, + .scan_bus = NULL, }; /* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index c94779b..19d1344 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -59,7 +59,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index f6cb6e4..72543fe 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -36,7 +36,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index 9d48b89..e5cab63 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -37,7 +37,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb2_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 606faa4..097cc6a 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -255,7 +255,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ac97_audio_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &ac97_pci_ops, }; @@ -265,7 +265,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ac97_modem_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &ac97_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index c18eb4b..9e34912 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -311,7 +311,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 2bb6be4..e291aa4 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -101,7 +101,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &ide_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/nic.c b/src/southbridge/intel/i82801gx/nic.c index b7b061f..5fd369e 100644 --- a/src/southbridge/intel/i82801gx/nic.c +++ b/src/southbridge/intel/i82801gx/nic.c @@ -29,7 +29,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nic_init, - .scan_bus = 0, + .scan_bus = NULL, }; /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index a658057..df8acf5 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -239,7 +239,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sata_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 21d1a6b..ea83579 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -51,7 +51,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &usb_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 368eebf..f8eba8e 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -83,7 +83,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = i82801gx_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 65492d6..e2974ee 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -294,7 +294,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 49d60f2..e197493 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -270,7 +270,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 4d49af4..2be5633 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -58,7 +58,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &thermal_pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 7eb7243..5816810 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -64,7 +64,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0a964be..c98c6a3 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -294,7 +294,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 69df88c..d330ec1 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -264,7 +264,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index d2744c8..8978b0e 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -58,7 +58,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &thermal_pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 8290112..352fb90 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -66,7 +66,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 1f4aa501a..ad98be8 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -97,7 +97,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = p64h2_ioapic_init, - .scan_bus = 0, + .scan_bus = NULL, .enable = p64h2_ioapic_enable, }; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index fe5cc2e..2716cf8 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -319,7 +319,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 555b5ca..7294382 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -241,7 +241,7 @@ .init = sata_init, .enable = sata_enable, .acpi_fill_ssdt = sata_fill_ssdt, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 2664c65..2918b66 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -52,7 +52,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = thermal_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index f4b975a..d179e17 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -92,7 +92,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index eb505ed..7c62b89 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -160,7 +160,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = azalia_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &azalia_pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 8570dab..6a2ea9b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -333,7 +333,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &sata_pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 574b6d1..64b366e 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -189,7 +189,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index c07e764..38d1fe32 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -58,7 +58,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, .init = ti_pci1x2y_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &ti_pci1x2y_pci_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/40126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Gerrit-Change-Number: 40126 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 20

Change in coreboot[master]: soc/intel: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 05 Apr '20

05 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40131 ) Change subject: soc/intel: Use SPDX for GPL-2.0-only files ...................................................................... soc/intel: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I75cda26f254c6d1beffbdef95a878d3eafc5c0b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi/dptf.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/platform.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl M src/soc/intel/apollolake/acpi/xhci.asl M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/elog.c M src/soc/intel/apollolake/i2c.c M src/soc/intel/apollolake/include/soc/gpe.h M src/soc/intel/apollolake/include/soc/itss.h M src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/include/soc/p2sb.h M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/apollolake/include/soc/pnpconfig.h M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/apollolake/include/soc/soc_chip.h M src/soc/intel/apollolake/meminit.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/reset.c M src/soc/intel/apollolake/sd.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/apollolake/xhci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/device_nvs.asl M src/soc/intel/baytrail/acpi/dptf/charger.asl M src/soc/intel/baytrail/acpi/dptf/cpu.asl M src/soc/intel/baytrail/acpi/dptf/dptf.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/gpio.asl M src/soc/intel/baytrail/acpi/irq_helper.h M src/soc/intel/baytrail/acpi/irqlinks.asl M src/soc/intel/baytrail/acpi/irqroute.asl M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/baytrail/acpi/lpe.asl M src/soc/intel/baytrail/acpi/lpss.asl M src/soc/intel/baytrail/acpi/pcie.asl M src/soc/intel/baytrail/acpi/platform.asl M src/soc/intel/baytrail/acpi/scc.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/acpi/xhci.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/chip.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/ehci.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/baytrail/include/soc/device_nvs.h M src/soc/intel/baytrail/include/soc/ehci.h M src/soc/intel/baytrail/include/soc/gfx.h M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/include/soc/iomap.h M src/soc/intel/baytrail/include/soc/iosf.h M src/soc/intel/baytrail/include/soc/irq.h M src/soc/intel/baytrail/include/soc/lpc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/baytrail/include/soc/pattrs.h M src/soc/intel/baytrail/include/soc/pci_devs.h M src/soc/intel/baytrail/include/soc/pcie.h M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/include/soc/sata.h M src/soc/intel/baytrail/include/soc/smm.h M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/include/soc/xhci.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/placeholders.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/refcode.c M src/soc/intel/baytrail/romstage/gfx.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/scc.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/baytrail/xhci.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/device_nvs.asl M src/soc/intel/braswell/acpi/dptf/charger.asl M src/soc/intel/braswell/acpi/dptf/cpu.asl M src/soc/intel/braswell/acpi/dptf/dptf.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/wifi.asl M src/soc/intel/braswell/acpi/dptf/wwan.asl M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/gpio.asl M src/soc/intel/braswell/acpi/irq_helper.h M src/soc/intel/braswell/acpi/irqlinks.asl M src/soc/intel/braswell/acpi/irqroute.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/acpi/lpss.asl M src/soc/intel/braswell/acpi/platform.asl M src/soc/intel/braswell/acpi/scc.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/acpi/xhci.asl M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/gpio_support.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/include/soc/device_nvs.h M src/soc/intel/braswell/include/soc/ehci.h M src/soc/intel/braswell/include/soc/gfx.h M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/include/soc/gpio_defs.h M src/soc/intel/braswell/include/soc/hda.h M src/soc/intel/braswell/include/soc/iomap.h M src/soc/intel/braswell/include/soc/iosf.h M src/soc/intel/braswell/include/soc/irq.h M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/braswell/include/soc/pattrs.h M src/soc/intel/braswell/include/soc/pci_devs.h M src/soc/intel/braswell/include/soc/pcie.h M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/include/soc/ramstage.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/include/soc/sata.h M src/soc/intel/braswell/include/soc/smbus.h M src/soc/intel/braswell/include/soc/smm.h M src/soc/intel/braswell/include/soc/spi.h M src/soc/intel/braswell/include/soc/xhci.h M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/placeholders.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/smbus.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/braswell/xhci.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/device_nvs.asl M src/soc/intel/broadwell/acpi/ehci.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/hda.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/pci_irqs.asl M src/soc/intel/broadwell/acpi/pcie.asl M src/soc/intel/broadwell/acpi/pcie_port.asl M src/soc/intel/broadwell/acpi/platform.asl M src/soc/intel/broadwell/acpi/sata.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/smbus.asl M src/soc/intel/broadwell/acpi/systemagent.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/elog.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/broadwell/include/soc/adsp.h M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/device_nvs.h M src/soc/intel/broadwell/include/soc/ehci.h M src/soc/intel/broadwell/include/soc/gpio.h M src/soc/intel/broadwell/include/soc/igd.h M src/soc/intel/broadwell/include/soc/iobp.h M src/soc/intel/broadwell/include/soc/iomap.h M src/soc/intel/broadwell/include/soc/lpc.h M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/include/soc/pei_wrapper.h M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/include/soc/rcba.h M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/include/soc/sata.h M src/soc/intel/broadwell/include/soc/serialio.h M src/soc/intel/broadwell/include/soc/smbus.h M src/soc/intel/broadwell/include/soc/spi.h M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/romstage/cpu.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/tsc_freq.c M src/soc/intel/broadwell/usb_debug.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/dptf.asl M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/cannonlake/acpi/ish.asl M src/soc/intel/cannonlake/acpi/pch_glan.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/acpi/platform.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/acpi/serialio.asl M src/soc/intel/cannonlake/acpi/smbus.asl M src/soc/intel/cannonlake/acpi/xhci.asl M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/cpu.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/i2c.c M src/soc/intel/cannonlake/include/soc/bootblock.h M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/gpe.h M src/soc/intel/cannonlake/include/soc/gpio.h M src/soc/intel/cannonlake/include/soc/gpio_common.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/irq.h M src/soc/intel/cannonlake/include/soc/itss.h M src/soc/intel/cannonlake/include/soc/lpc.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/cannonlake/include/soc/nvs.h M src/soc/intel/cannonlake/include/soc/p2sb.h M src/soc/intel/cannonlake/include/soc/pch.h M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/include/soc/ramstage.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/include/soc/sata.h M src/soc/intel/cannonlake/include/soc/serialio.h M src/soc/intel/cannonlake/include/soc/smbus.h M src/soc/intel/cannonlake/include/soc/soc_chip.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/include/soc/usb.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/me.c M src/soc/intel/cannonlake/p2sb.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/pch.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/cannonlake/romstage/systemagent.c M src/soc/intel/cannonlake/sd.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/acpi/acpi_debug.asl M src/soc/intel/common/acpi/acpi_wake_source.asl M src/soc/intel/common/acpi/dptf/charger.asl M src/soc/intel/common/acpi/dptf/cpu.asl M src/soc/intel/common/acpi/dptf/dptf.asl M src/soc/intel/common/acpi/dptf/fan.asl M src/soc/intel/common/acpi/dptf/thermal.asl M src/soc/intel/common/acpi/pci_osc.asl M src/soc/intel/common/acpi/pcr.asl M src/soc/intel/common/acpi/platform.asl M src/soc/intel/common/acpi/sgx.asl M src/soc/intel/common/acpi/wifi.asl M src/soc/intel/common/acpi_wake_source.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/ipu.asl M src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/common/block/chip/chip.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car_fsp.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/imc/imc.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/common/block/include/intelblocks/gspi.h M src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/include/intelblocks/pcr.h M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/include/intelblocks/rtc.h M src/soc/intel/common/block/include/intelblocks/sd.h M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/include/intelblocks/smbus.h M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/include/intelblocks/sram.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/include/intelblocks/xdci.h M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/itss/itss.c M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pcie/pcie_rp.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/rtc/rtc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smbus/smbuslib.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/block/thermal/thermal.c M src/soc/intel/common/block/timer/timer.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/elog.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/hda_verb.h M src/soc/intel/common/mma.c M src/soc/intel/common/mma.h M src/soc/intel/common/nhlt.c M src/soc/intel/common/pch/include/intelpch/lockdown.h M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/common/reset.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/common/tpm_tis.c M src/soc/intel/common/vbt.c M src/soc/intel/common/vbt.h M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/irqlinks.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/npk.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/denverton_ns/acpi/pcie_port.asl M src/soc/intel/denverton_ns/acpi/pmc.asl M src/soc/intel/denverton_ns/acpi/sata.asl M src/soc/intel/denverton_ns/acpi/sata2.asl M src/soc/intel/denverton_ns/acpi/smbus.asl M src/soc/intel/denverton_ns/acpi/smbus2.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl M src/soc/intel/denverton_ns/acpi/xhci.asl M src/soc/intel/denverton_ns/chip.h M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/fiamux.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/hob_mem.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/bootblock.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/denverton_ns/include/soc/fiamux.h M src/soc/intel/denverton_ns/include/soc/gpio.h M src/soc/intel/denverton_ns/include/soc/gpio_defs.h M src/soc/intel/denverton_ns/include/soc/gpio_dnv.h M src/soc/intel/denverton_ns/include/soc/hob_mem.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/lpc.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/denverton_ns/include/soc/p2sb.h M src/soc/intel/denverton_ns/include/soc/pattrs.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pcr.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/include/soc/ramstage.h M src/soc/intel/denverton_ns/include/soc/sata.h M src/soc/intel/denverton_ns/include/soc/smbus.h M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/include/soc/uart.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/reset.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/icelake/acpi/pch_glan.asl M src/soc/intel/icelake/acpi/pch_hda.asl M src/soc/intel/icelake/acpi/pcie.asl M src/soc/intel/icelake/acpi/platform.asl M src/soc/intel/icelake/acpi/scs.asl M src/soc/intel/icelake/acpi/serialio.asl M src/soc/intel/icelake/acpi/smbus.asl M src/soc/intel/icelake/acpi/xhci.asl M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/cpu.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/elog.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/i2c.c M src/soc/intel/icelake/include/soc/bootblock.h M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/gpe.h M src/soc/intel/icelake/include/soc/gpio.h M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/icelake/include/soc/gpio_soc_defs.h M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/icelake/include/soc/irq.h M src/soc/intel/icelake/include/soc/itss.h M src/soc/intel/icelake/include/soc/me.h M src/soc/intel/icelake/include/soc/msr.h M src/soc/intel/icelake/include/soc/nvs.h M src/soc/intel/icelake/include/soc/p2sb.h M src/soc/intel/icelake/include/soc/pch.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/include/soc/pmc.h M src/soc/intel/icelake/include/soc/ramstage.h M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/icelake/include/soc/serialio.h M src/soc/intel/icelake/include/soc/smbus.h M src/soc/intel/icelake/include/soc/soc_chip.h M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/include/soc/usb.h M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/p2sb.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/reset.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/romstage/pch.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/icelake/romstage/systemagent.c M src/soc/intel/icelake/sd.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/systemagent.c M src/soc/intel/icelake/uart.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio_op.asl M src/soc/intel/jasperlake/acpi/ipu.asl M src/soc/intel/jasperlake/acpi/ish.asl M src/soc/intel/jasperlake/acpi/pch_glan.asl M src/soc/intel/jasperlake/acpi/pch_hda.asl M src/soc/intel/jasperlake/acpi/pcie.asl M src/soc/intel/jasperlake/acpi/platform.asl M src/soc/intel/jasperlake/acpi/pmc.asl M src/soc/intel/jasperlake/acpi/scs.asl M src/soc/intel/jasperlake/acpi/serialio.asl M src/soc/intel/jasperlake/acpi/smbus.asl M src/soc/intel/jasperlake/acpi/xhci.asl M src/soc/intel/jasperlake/bootblock/bootblock.c M src/soc/intel/jasperlake/bootblock/cpu.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/report_platform.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/i2c.c M src/soc/intel/jasperlake/include/soc/bootblock.h M src/soc/intel/jasperlake/include/soc/cpu.h M src/soc/intel/jasperlake/include/soc/espi.h M src/soc/intel/jasperlake/include/soc/gpe.h M src/soc/intel/jasperlake/include/soc/gpio.h M src/soc/intel/jasperlake/include/soc/gpio_defs.h M src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h M src/soc/intel/jasperlake/include/soc/iomap.h M src/soc/intel/jasperlake/include/soc/irq.h M src/soc/intel/jasperlake/include/soc/itss.h M src/soc/intel/jasperlake/include/soc/me.h M src/soc/intel/jasperlake/include/soc/meminit.h M src/soc/intel/jasperlake/include/soc/msr.h M src/soc/intel/jasperlake/include/soc/nvs.h M src/soc/intel/jasperlake/include/soc/p2sb.h M src/soc/intel/jasperlake/include/soc/pch.h M src/soc/intel/jasperlake/include/soc/pci_devs.h M src/soc/intel/jasperlake/include/soc/pcr_ids.h M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/include/soc/pmc.h M src/soc/intel/jasperlake/include/soc/ramstage.h M src/soc/intel/jasperlake/include/soc/romstage.h M src/soc/intel/jasperlake/include/soc/serialio.h M src/soc/intel/jasperlake/include/soc/smbus.h M src/soc/intel/jasperlake/include/soc/soc_chip.h M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/include/soc/usb.h M src/soc/intel/jasperlake/lockdown.c M src/soc/intel/jasperlake/meminit.c M src/soc/intel/jasperlake/p2sb.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/jasperlake/reset.c M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/jasperlake/romstage/pch.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/systemagent.c M src/soc/intel/jasperlake/sd.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/jasperlake/uart.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/chip.c M src/soc/intel/quark/chip.h M src/soc/intel/quark/ehci.c M src/soc/intel/quark/fsp_params.c M src/soc/intel/quark/gpio_i2c.c M src/soc/intel/quark/i2c.c M src/soc/intel/quark/include/soc/acpi.h M src/soc/intel/quark/include/soc/car.h M src/soc/intel/quark/include/soc/cpu.h M src/soc/intel/quark/include/soc/i2c.h M src/soc/intel/quark/include/soc/iomap.h M src/soc/intel/quark/include/soc/pci_devs.h M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/include/soc/romstage.h M src/soc/intel/quark/include/soc/sd.h M src/soc/intel/quark/include/soc/spi.h M src/soc/intel/quark/include/soc/storage_test.h M src/soc/intel/quark/lpc.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/quark/reg_access.c M src/soc/intel/quark/reset.c M src/soc/intel/quark/romstage/car.c M src/soc/intel/quark/romstage/debug.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/quark/romstage/mtrr.c M src/soc/intel/quark/romstage/pcie.c M src/soc/intel/quark/romstage/report_platform.c M src/soc/intel/quark/romstage/romstage.c M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/quark/tsc_freq.c M src/soc/intel/quark/uart.c M src/soc/intel/quark/uart_common.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_op.asl M src/soc/intel/tigerlake/acpi/ipu.asl M src/soc/intel/tigerlake/acpi/ish.asl M src/soc/intel/tigerlake/acpi/pch_glan.asl M src/soc/intel/tigerlake/acpi/pch_hda.asl M src/soc/intel/tigerlake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/platform.asl M src/soc/intel/tigerlake/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/scs.asl M src/soc/intel/tigerlake/acpi/serialio.asl M src/soc/intel/tigerlake/acpi/smbus.asl M src/soc/intel/tigerlake/acpi/xhci.asl M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/cpu.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/i2c.c M src/soc/intel/tigerlake/include/soc/bootblock.h M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/include/soc/espi.h M src/soc/intel/tigerlake/include/soc/gpe.h M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/include/soc/itss.h M src/soc/intel/tigerlake/include/soc/me.h M src/soc/intel/tigerlake/include/soc/msr.h M src/soc/intel/tigerlake/include/soc/nvs.h M src/soc/intel/tigerlake/include/soc/p2sb.h M src/soc/intel/tigerlake/include/soc/pch.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/pcr_ids.h M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/include/soc/pmc.h M src/soc/intel/tigerlake/include/soc/ramstage.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/include/soc/serialio.h M src/soc/intel/tigerlake/include/soc/smbus.h M src/soc/intel/tigerlake/include/soc/soc_chip.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/include/soc/usb.h M src/soc/intel/tigerlake/lockdown.c M src/soc/intel/tigerlake/p2sb.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/reset.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/systemagent.c M src/soc/intel/tigerlake/sd.c M src/soc/intel/tigerlake/smihandler.c M src/soc/intel/tigerlake/smmrelocate.c M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/tigerlake/uart.c M src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl M src/soc/intel/xeon_sp/skx/include/soc/nvs.h 839 files changed, 1,621 insertions(+), 10,825 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/40131/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75cda26f254c6d1beffbdef95a878d3eafc5c0b6 Gerrit-Change-Number: 40131 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mainboard/google: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 05 Apr '20

05 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40079 ) Change subject: mainboard/google: Use SPDX for GPL-2.0-only files ...................................................................... mainboard/google: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I661dbb585bd5198206b998f0a1a0e4cf2d05d4be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/acpi/ec.asl M src/mainboard/google/auron/acpi/mainboard.asl M src/mainboard/google/auron/acpi/superio.asl M src/mainboard/google/auron/acpi/thermal.asl M src/mainboard/google/auron/acpi/video.asl M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/auron/ec.c M src/mainboard/google/auron/ec.h M src/mainboard/google/auron/fadt.c M src/mainboard/google/auron/hda_verb.c M src/mainboard/google/auron/mainboard.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/auron/variant.h M src/mainboard/google/auron/variants/auron_paine/gpio.c M src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl M src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h M src/mainboard/google/auron/variants/auron_paine/include/variant/onboard.h M src/mainboard/google/auron/variants/auron_paine/include/variant/spd.h M src/mainboard/google/auron/variants/auron_paine/include/variant/thermal.h M src/mainboard/google/auron/variants/auron_paine/pei_data.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_paine/variant.c M src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl M src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h M src/mainboard/google/auron/variants/auron_yuna/include/variant/onboard.h M src/mainboard/google/auron/variants/auron_yuna/include/variant/spd.h M src/mainboard/google/auron/variants/auron_yuna/include/variant/thermal.h M src/mainboard/google/auron/variants/auron_yuna/pei_data.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/variant.c M src/mainboard/google/auron/variants/buddy/gpio.c M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/buddy/include/variant/hda_verb.h M src/mainboard/google/auron/variants/buddy/include/variant/onboard.h M src/mainboard/google/auron/variants/buddy/include/variant/spd.h M src/mainboard/google/auron/variants/buddy/include/variant/thermal.h M src/mainboard/google/auron/variants/buddy/pei_data.c M src/mainboard/google/auron/variants/buddy/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/include/variant/acpi/ec.asl M src/mainboard/google/auron/variants/gandof/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl M src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h M src/mainboard/google/auron/variants/gandof/include/variant/onboard.h M src/mainboard/google/auron/variants/gandof/include/variant/spd.h M src/mainboard/google/auron/variants/gandof/include/variant/thermal.h M src/mainboard/google/auron/variants/gandof/pei_data.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/include/variant/acpi/ec.asl M src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl M src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h M src/mainboard/google/auron/variants/lulu/include/variant/onboard.h M src/mainboard/google/auron/variants/lulu/include/variant/spd.h M src/mainboard/google/auron/variants/lulu/include/variant/thermal.h M src/mainboard/google/auron/variants/lulu/pei_data.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/lulu/variant.c M src/mainboard/google/auron/variants/samus/board_version.c M src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/include/variant/acpi/ec.asl M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl M src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl M src/mainboard/google/auron/variants/samus/include/variant/board_version.h M src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h M src/mainboard/google/auron/variants/samus/include/variant/onboard.h M src/mainboard/google/auron/variants/samus/include/variant/spd.h M src/mainboard/google/auron/variants/samus/include/variant/thermal.h M src/mainboard/google/auron/variants/samus/pei_data.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/auron/variants/samus/variant.c M src/mainboard/google/beltino/acpi/mainboard.asl M src/mainboard/google/beltino/acpi/platform.asl M src/mainboard/google/beltino/acpi/superio.asl M src/mainboard/google/beltino/acpi/thermal.asl M src/mainboard/google/beltino/acpi/usb.asl M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/beltino/lan.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/beltino/onboard.h M src/mainboard/google/beltino/romstage.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h M src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h M src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h M src/mainboard/google/beltino/variants/monroe/led.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/panther/include/variant/gpio.h M src/mainboard/google/beltino/variants/panther/include/variant/thermal.h M src/mainboard/google/beltino/variants/panther/led.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h M src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/beltino/variants/zako/hda_verb.c M src/mainboard/google/beltino/variants/zako/include/variant/gpio.h M src/mainboard/google/beltino/variants/zako/include/variant/thermal.h M src/mainboard/google/beltino/variants/zako/led.c M src/mainboard/google/butterfly/acpi/ec.asl M src/mainboard/google/butterfly/acpi/mainboard.asl M src/mainboard/google/butterfly/acpi/platform.asl M src/mainboard/google/butterfly/acpi/superio.asl M src/mainboard/google/butterfly/acpi/thermal.asl M src/mainboard/google/butterfly/acpi_tables.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/butterfly/ec.c M src/mainboard/google/butterfly/ec.h M src/mainboard/google/butterfly/gpio.c M src/mainboard/google/butterfly/hda_verb.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/onboard.h M src/mainboard/google/butterfly/thermal.h M src/mainboard/google/cheza/boardid.c M src/mainboard/google/cheza/reset.c M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl M src/mainboard/google/cyan/acpi/dptf.asl M src/mainboard/google/cyan/acpi/ec.asl M src/mainboard/google/cyan/acpi/mainboard.asl M src/mainboard/google/cyan/acpi/superio.asl M src/mainboard/google/cyan/acpi/touchscreen_elan.asl M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/acpi/trackpad_elan.asl M src/mainboard/google/cyan/acpi_tables.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/com_init.c M src/mainboard/google/cyan/dsdt.asl M src/mainboard/google/cyan/ec.c M src/mainboard/google/cyan/ec.h M src/mainboard/google/cyan/fadt.c M src/mainboard/google/cyan/irqroute.c M src/mainboard/google/cyan/irqroute.h M src/mainboard/google/cyan/mainboard.c M src/mainboard/google/cyan/romstage.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/cyan/spd/spd_util.h M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/banon/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/banon/include/variant/onboard.h M src/mainboard/google/cyan/variants/banon/romstage.c M src/mainboard/google/cyan/variants/banon/spd_util.c M src/mainboard/google/cyan/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/celes/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/celes/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/celes/include/variant/onboard.h M src/mainboard/google/cyan/variants/celes/ramstage.c M src/mainboard/google/cyan/variants/celes/spd_util.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h M src/mainboard/google/cyan/variants/cyan/spd_util.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h M src/mainboard/google/cyan/variants/edgar/romstage.c M src/mainboard/google/cyan/variants/edgar/spd_util.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/kefka/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h M src/mainboard/google/cyan/variants/kefka/ramstage.c M src/mainboard/google/cyan/variants/kefka/romstage.c M src/mainboard/google/cyan/variants/kefka/spd_util.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/reks/include/variant/onboard.h M src/mainboard/google/cyan/variants/reks/ramstage.c M src/mainboard/google/cyan/variants/reks/romstage.c M src/mainboard/google/cyan/variants/reks/spd_util.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/relm/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/relm/include/variant/onboard.h M src/mainboard/google/cyan/variants/relm/ramstage.c M src/mainboard/google/cyan/variants/relm/romstage.c M src/mainboard/google/cyan/variants/relm/spd_util.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/setzer/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h M src/mainboard/google/cyan/variants/setzer/ramstage.c M src/mainboard/google/cyan/variants/setzer/romstage.c M src/mainboard/google/cyan/variants/setzer/spd_util.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl M src/mainboard/google/cyan/variants/terra/include/variant/onboard.h M src/mainboard/google/cyan/variants/terra/ramstage.c M src/mainboard/google/cyan/variants/terra/romstage.c M src/mainboard/google/cyan/variants/terra/spd_util.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/ultima/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h M src/mainboard/google/cyan/variants/ultima/ramstage.c M src/mainboard/google/cyan/variants/ultima/spd_util.c M src/mainboard/google/cyan/variants/wizpig/gpio.c M src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl M src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/mainboard.asl M src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h M src/mainboard/google/cyan/variants/wizpig/spd_util.c M src/mainboard/google/cyan/w25q64.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/daisy/exynos5250.h M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/daisy/memlayout.ld M src/mainboard/google/daisy/memory.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/daisy/wakeup.c M src/mainboard/google/dragonegg/bootblock.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/dragonegg/ec.c M src/mainboard/google/dragonegg/mainboard.c M src/mainboard/google/dragonegg/romstage_fsp_params.c M src/mainboard/google/dragonegg/smihandler.c M src/mainboard/google/dragonegg/variants/baseboard/gpio.c M src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/dragonegg/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/dragonegg/variants/baseboard/memory.c M src/mainboard/google/dragonegg/variants/dragonegg/include/variant/ec.h M src/mainboard/google/dragonegg/variants/dragonegg/include/variant/gpio.h M src/mainboard/google/drallion/bootblock.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/drallion/ec.c M src/mainboard/google/drallion/hda_verb.c M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/smihandler.c M src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/dptf.asl M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl M src/mainboard/google/drallion/variants/drallion/include/variant/ec.h M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c M src/mainboard/google/drallion/variants/drallion/sku.c M src/mainboard/google/drallion/variants/drallion/smbios.c M src/mainboard/google/eve/acpi/dptf.asl M src/mainboard/google/eve/bootblock.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/eve/ec.c M src/mainboard/google/eve/ec.h M src/mainboard/google/eve/gpio.h M src/mainboard/google/eve/mainboard.c M src/mainboard/google/eve/romstage.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/eve/spd/spd.h M src/mainboard/google/fizz/acpi/usb.asl M src/mainboard/google/fizz/bootblock.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/fizz/ec.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/fizz/romstage.c M src/mainboard/google/fizz/smihandler.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl M src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fizz/variants/baseboard/nhlt.c M src/mainboard/google/fizz/variants/endeavour/gpio.c M src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl M src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h M src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h M src/mainboard/google/fizz/variants/endeavour/nhlt.c M src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl M src/mainboard/google/fizz/variants/fizz/include/variant/ec.h M src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/fizz/variants/karma/include/variant/acpi/dptf.asl M src/mainboard/google/fizz/variants/karma/include/variant/ec.h M src/mainboard/google/fizz/variants/karma/include/variant/gpio.h M src/mainboard/google/fizz/variants/karma/nhlt.c M src/mainboard/google/fizz/variants/karma/smihandler.c M src/mainboard/google/foster/boardid.c M src/mainboard/google/foster/bootblock.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/foster/ec_dummy.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/memlayout.ld M src/mainboard/google/foster/pmic.c M src/mainboard/google/foster/pmic.h M src/mainboard/google/foster/reset.c M src/mainboard/google/foster/romstage.c M src/mainboard/google/foster/sdram_configs.c M src/mainboard/google/gale/boardid.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/gale/memlayout.ld M src/mainboard/google/gale/reset.c M src/mainboard/google/gale/romstage.c M src/mainboard/google/gale/verstage.c M src/mainboard/google/glados/acpi/dptf.asl M src/mainboard/google/glados/acpi/ec.asl M src/mainboard/google/glados/acpi/mainboard.asl M src/mainboard/google/glados/acpi/superio.asl M src/mainboard/google/glados/bootblock_mainboard.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/glados/ec.c M src/mainboard/google/glados/ec.h M src/mainboard/google/glados/mainboard.c M src/mainboard/google/glados/romstage.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/glados/spd/spd.h M src/mainboard/google/glados/spd/spd_util.h M src/mainboard/google/glados/variants/asuka/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h M src/mainboard/google/glados/variants/caroline/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl M src/mainboard/google/glados/variants/caroline/include/variant/ec.h M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/cave/include/variant/ec.h M src/mainboard/google/glados/variants/cave/include/variant/gpio.h M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl M src/mainboard/google/glados/variants/chell/include/variant/ec.h M src/mainboard/google/glados/variants/chell/include/variant/gpio.h M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/glados/include/variant/ec.h M src/mainboard/google/glados/variants/glados/include/variant/gpio.h M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/lars/include/variant/ec.h M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl M src/mainboard/google/glados/variants/sentry/include/variant/ec.h M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h M src/mainboard/google/glados/variants/sentry/variant.c M src/mainboard/google/gru/board.h M src/mainboard/google/gru/boardid.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/gru/mainboard.c M src/mainboard/google/gru/memlayout.ld M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/gru/pwm_regulator.h M src/mainboard/google/gru/reset.c M src/mainboard/google/gru/romstage.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-800.c M src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-2GB-928.c M src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-800.c M src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c M src/mainboard/google/hatch/bootblock.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/ec.c M src/mainboard/google/hatch/mainboard.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/romstage_spd_cbfs.c M src/mainboard/google/hatch/romstage_spd_smbus.c M src/mainboard/google/hatch/smihandler.c M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/akemi/include/variant/ec.h M src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl M src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/baseboard/memory.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/dratini/include/variant/ec.h M src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h M src/mainboard/google/hatch/variants/dratini/include/variant/sku.h M src/mainboard/google/hatch/variants/dratini/ramstage.c M src/mainboard/google/hatch/variants/dratini/variant.c M src/mainboard/google/hatch/variants/hatch/gpio.c M src/mainboard/google/hatch/variants/hatch/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/hatch/include/variant/ec.h M src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/helios/include/variant/ec.h M src/mainboard/google/hatch/variants/helios/include/variant/gpio.h M src/mainboard/google/hatch/variants/helios/memory.c M src/mainboard/google/hatch/variants/helios/ramstage.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h M src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h M src/mainboard/google/hatch/variants/jinlon/ramstage.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kindred/include/variant/ec.h M src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h M src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/memory.c M src/mainboard/google/hatch/variants/kohaku/ramstage.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/mushu/include/variant/ec.h M src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h M src/mainboard/google/hatch/variants/nightfury/gpio.c M src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h M src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h M src/mainboard/google/hatch/variants/nightfury/memory.c M src/mainboard/google/hatch/variants/nightfury/ramstage.c M src/mainboard/google/hatch/variants/puff/gpio.c M src/mainboard/google/hatch/variants/puff/include/variant/ec.h M src/mainboard/google/hatch/variants/puff/include/variant/gpio.h M src/mainboard/google/hatch/variants/puff/mainboard.c M src/mainboard/google/hatch/variants/stryke/gpio.c M src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/stryke/include/variant/ec.h M src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h M src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/sushi/include/variant/ec.h M src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h M src/mainboard/google/jecht/acpi/mainboard.asl M src/mainboard/google/jecht/acpi/platform.asl M src/mainboard/google/jecht/acpi/superio.asl M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/jecht/fadt.c M src/mainboard/google/jecht/hda_verb.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/jecht/led.c M src/mainboard/google/jecht/mainboard.c M src/mainboard/google/jecht/onboard.h M src/mainboard/google/jecht/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/jecht/spd/spd.c M src/mainboard/google/jecht/spd/spd.h M src/mainboard/google/jecht/variants/guado/gpio.c M src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/guado/include/variant/thermal.h M src/mainboard/google/jecht/variants/guado/pei_data.c M src/mainboard/google/jecht/variants/jecht/gpio.c M src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h M src/mainboard/google/jecht/variants/jecht/pei_data.c M src/mainboard/google/jecht/variants/rikku/gpio.c M src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl M src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h M src/mainboard/google/jecht/variants/rikku/pei_data.c M src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl M src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h M src/mainboard/google/jecht/variants/tidus/pei_data.c M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/kahlee/ec.c M src/mainboard/google/kahlee/irq_tables.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/kahlee/smihandler.c M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/aleena/include/variant/ec.h M src/mainboard/google/kahlee/variants/aleena/include/variant/gpio.h M src/mainboard/google/kahlee/variants/aleena/include/variant/thermal.h M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/google/kahlee/variants/baseboard/romstage.c M src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/careena/include/variant/ec.h M src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h M src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h M src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/liara/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/liara/include/variant/ec.h M src/mainboard/google/kahlee/variants/liara/include/variant/gpio.h M src/mainboard/google/kahlee/variants/liara/include/variant/thermal.h M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/nuwani/include/variant/ec.h M src/mainboard/google/kahlee/variants/nuwani/include/variant/gpio.h M src/mainboard/google/kahlee/variants/nuwani/include/variant/thermal.h M src/mainboard/google/kahlee/variants/nuwani/mainboard.c M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl M src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h M src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h M src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h M src/mainboard/google/kahlee/variants/treeya/mainboard.c M src/mainboard/google/kukui/boardid.c M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/kukui/early_init.h M src/mainboard/google/kukui/gpio.h M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/kukui/memlayout.ld M src/mainboard/google/kukui/panel.h M src/mainboard/google/kukui/panel_anx7625.c M src/mainboard/google/kukui/panel_flapjack.c M src/mainboard/google/kukui/panel_kakadu.c M src/mainboard/google/kukui/panel_kodama.c M src/mainboard/google/kukui/panel_krane.c M src/mainboard/google/kukui/panel_kukui.c M src/mainboard/google/kukui/panel_params/panel-AUO_B101UAN08_3.c M src/mainboard/google/kukui/panel_params/panel-AUO_KD101N80_45NA.c M src/mainboard/google/kukui/panel_params/panel-AUO_NT51021D8P.c M src/mainboard/google/kukui/panel_params/panel-BOE_TV080WUM_NG0.c M src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c M src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NG0.c M src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_NL6.c M src/mainboard/google/kukui/panel_params/panel-BOE_TV105WUM_NW0.c M src/mainboard/google/kukui/panel_params/panel-CMN_P097PFG_SSD2858.c M src/mainboard/google/kukui/panel_params/panel-INX_OTA7290D10P.c M src/mainboard/google/kukui/panel_ps8640.c M src/mainboard/google/kukui/reset.c M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c M src/mainboard/google/kukui/verstage.c M src/mainboard/google/link/acpi/ec.asl M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/acpi/platform.asl M src/mainboard/google/link/acpi/superio.asl M src/mainboard/google/link/acpi/thermal.asl M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/early_init.c M src/mainboard/google/link/ec.c M src/mainboard/google/link/ec.h M src/mainboard/google/link/gpio.c M src/mainboard/google/link/hda_verb.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/onboard.h M src/mainboard/google/link/thermal.h M src/mainboard/google/mistral/reset.c M src/mainboard/google/mistral/verstage.c M src/mainboard/google/nyan/boardid.c M src/mainboard/google/nyan/bootblock.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan/early_configs.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan/memlayout.ld M src/mainboard/google/nyan/pmic.c M src/mainboard/google/nyan/pmic.h M src/mainboard/google/nyan/reset.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan/sdram_configs.c M src/mainboard/google/nyan/sdram_configs.h M src/mainboard/google/nyan_big/boardid.c M src/mainboard/google/nyan_big/bootblock.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_big/early_configs.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_big/memlayout.ld M src/mainboard/google/nyan_big/pmic.c M src/mainboard/google/nyan_big/pmic.h M src/mainboard/google/nyan_big/reset.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_big/sdram_configs.c M src/mainboard/google/nyan_big/sdram_configs.h M src/mainboard/google/nyan_blaze/boardid.c M src/mainboard/google/nyan_blaze/bootblock.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/nyan_blaze/early_configs.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/nyan_blaze/memlayout.ld M src/mainboard/google/nyan_blaze/pmic.c M src/mainboard/google/nyan_blaze/pmic.h M src/mainboard/google/nyan_blaze/reset.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/nyan_blaze/sdram_configs.c M src/mainboard/google/nyan_blaze/sdram_configs.h M src/mainboard/google/oak/boardid.c M src/mainboard/google/oak/bootblock.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/oak/gpio.h M src/mainboard/google/oak/mainboard.c M src/mainboard/google/oak/memlayout.ld M src/mainboard/google/oak/romstage.c M src/mainboard/google/oak/sdram_configs.c M src/mainboard/google/oak/tpm_tis.c M src/mainboard/google/octopus/bootblock.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/octopus/ec.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/romstage.c M src/mainboard/google/octopus/smihandler.c M src/mainboard/google/octopus/variants/ampton/gpio.c M src/mainboard/google/octopus/variants/ampton/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/ampton/include/variant/ec.h M src/mainboard/google/octopus/variants/ampton/include/variant/gpio.h M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/octopus/variants/baseboard/memory.c M src/mainboard/google/octopus/variants/baseboard/nhlt.c M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/bloog/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/bloog/include/variant/ec.h M src/mainboard/google/octopus/variants/bloog/include/variant/gpio.h M src/mainboard/google/octopus/variants/bloog/variant.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/bobba/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/bobba/include/variant/ec.h M src/mainboard/google/octopus/variants/bobba/include/variant/gpio.h M src/mainboard/google/octopus/variants/bobba/variant.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/casta/include/variant/ec.h M src/mainboard/google/octopus/variants/casta/include/variant/gpio.h M src/mainboard/google/octopus/variants/casta/variant.c M src/mainboard/google/octopus/variants/dood/gpio.c M src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/dood/include/variant/ec.h M src/mainboard/google/octopus/variants/dood/include/variant/gpio.h M src/mainboard/google/octopus/variants/dood/variant.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/fleex/include/variant/ec.h M src/mainboard/google/octopus/variants/fleex/include/variant/gpio.h M src/mainboard/google/octopus/variants/foob/gpio.c M src/mainboard/google/octopus/variants/foob/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/foob/include/variant/ec.h M src/mainboard/google/octopus/variants/foob/include/variant/gpio.h M src/mainboard/google/octopus/variants/foob/variant.c M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/garg/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/garg/include/variant/ec.h M src/mainboard/google/octopus/variants/garg/include/variant/gpio.h M src/mainboard/google/octopus/variants/garg/include/variant/sku.h M src/mainboard/google/octopus/variants/garg/variant.c M src/mainboard/google/octopus/variants/lick/gpio.c M src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/lick/include/variant/ec.h M src/mainboard/google/octopus/variants/lick/include/variant/gpio.h M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/meep/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/meep/include/variant/ec.h M src/mainboard/google/octopus/variants/meep/include/variant/gpio.h M src/mainboard/google/octopus/variants/meep/include/variant/sku.h M src/mainboard/google/octopus/variants/meep/variant.c M src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/octopus/include/variant/ec.h M src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/phaser/include/variant/ec.h M src/mainboard/google/octopus/variants/phaser/include/variant/gpio.h M src/mainboard/google/octopus/variants/phaser/mainboard.c M src/mainboard/google/octopus/variants/phaser/variant.c M src/mainboard/google/octopus/variants/yorp/gpio.c M src/mainboard/google/octopus/variants/yorp/include/variant/acpi/dptf.asl M src/mainboard/google/octopus/variants/yorp/include/variant/ec.h M src/mainboard/google/octopus/variants/yorp/include/variant/gpio.h M src/mainboard/google/parrot/acpi/ec.asl M src/mainboard/google/parrot/acpi/mainboard.asl M src/mainboard/google/parrot/acpi/platform.asl M src/mainboard/google/parrot/acpi/superio.asl M src/mainboard/google/parrot/acpi/thermal.asl M src/mainboard/google/parrot/acpi/usb.asl M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/parrot/early_init.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/ec.h M src/mainboard/google/parrot/gpio.c M src/mainboard/google/parrot/hda_verb.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/parrot/onboard.h M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/parrot/thermal.h M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/peach_pit/memlayout.ld M src/mainboard/google/peach_pit/memory.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/peach_pit/wakeup.c M src/mainboard/google/poppy/bootblock.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/poppy/ec.c M src/mainboard/google/poppy/mainboard.c M src/mainboard/google/poppy/ramstage.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/smihandler.c M src/mainboard/google/poppy/variants/atlas/gpio.c M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/variants/atlas/include/variant/ec.h M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/atlas/memory.c M src/mainboard/google/poppy/variants/atlas/nhlt.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/dptf.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/poppy/variants/baseboard/memory.c M src/mainboard/google/poppy/variants/baseboard/nhlt.c M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/nami/include/variant/ec.h M src/mainboard/google/poppy/variants/nami/include/variant/gpio.h M src/mainboard/google/poppy/variants/nami/include/variant/sku.h M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nami/memory.c M src/mainboard/google/poppy/variants/nami/nhlt.c M src/mainboard/google/poppy/variants/nami/smihandler.c M src/mainboard/google/poppy/variants/nautilus/gpio.c M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/camera.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_endpoints.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/ec.h M src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h M src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nautilus/memory.c M src/mainboard/google/poppy/variants/nautilus/nhlt.c M src/mainboard/google/poppy/variants/nautilus/sku.c M src/mainboard/google/poppy/variants/nautilus/smihandler.c M src/mainboard/google/poppy/variants/nocturne/ec.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/google/poppy/variants/nocturne/memory.c M src/mainboard/google/poppy/variants/nocturne/nhlt.c M src/mainboard/google/poppy/variants/poppy/include/variant/acpi/camera.asl M src/mainboard/google/poppy/variants/poppy/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/poppy/include/variant/ec.h M src/mainboard/google/poppy/variants/poppy/include/variant/gpio.h M src/mainboard/google/poppy/variants/rammus/gpio.c M src/mainboard/google/poppy/variants/rammus/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/rammus/include/variant/ec.h M src/mainboard/google/poppy/variants/rammus/include/variant/gpio.h M src/mainboard/google/poppy/variants/rammus/mainboard.c M src/mainboard/google/poppy/variants/rammus/memory.c M src/mainboard/google/poppy/variants/rammus/nhlt.c M src/mainboard/google/poppy/variants/soraka/gpio.c M src/mainboard/google/poppy/variants/soraka/include/variant/acpi/camera.asl M src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl M src/mainboard/google/poppy/variants/soraka/include/variant/ec.h M src/mainboard/google/poppy/variants/soraka/include/variant/gpio.h M src/mainboard/google/rambi/acpi/dptf.asl M src/mainboard/google/rambi/acpi/ec.asl M src/mainboard/google/rambi/acpi/mainboard.asl M src/mainboard/google/rambi/acpi/superio.asl M src/mainboard/google/rambi/acpi/touchscreen_atmel.asl M src/mainboard/google/rambi/acpi/touchscreen_elan.asl M src/mainboard/google/rambi/acpi/touchscreen_wdt.asl M src/mainboard/google/rambi/acpi/trackpad_atmel.asl M src/mainboard/google/rambi/acpi/trackpad_elan.asl M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/rambi/ec.c M src/mainboard/google/rambi/ec.h M src/mainboard/google/rambi/fadt.c M src/mainboard/google/rambi/irqroute.c M src/mainboard/google/rambi/irqroute.h M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/rambi/mainboard_smi.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/banjo/gpio.c M src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h M src/mainboard/google/rambi/variants/banjo/include/variant/variant.h M src/mainboard/google/rambi/variants/candy/gpio.c M src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl M src/mainboard/google/rambi/variants/candy/include/variant/onboard.h M src/mainboard/google/rambi/variants/candy/include/variant/variant.h M src/mainboard/google/rambi/variants/clapper/gpio.c M src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h M src/mainboard/google/rambi/variants/clapper/include/variant/variant.h M src/mainboard/google/rambi/variants/enguarde/gpio.c M src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h M src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h M src/mainboard/google/rambi/variants/glimmer/gpio.c M src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h M src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h M src/mainboard/google/rambi/variants/gnawty/gpio.c M src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h M src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h M src/mainboard/google/rambi/variants/heli/gpio.c M src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/heli/include/variant/onboard.h M src/mainboard/google/rambi/variants/heli/include/variant/variant.h M src/mainboard/google/rambi/variants/kip/gpio.c M src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/kip/include/variant/onboard.h M src/mainboard/google/rambi/variants/kip/include/variant/variant.h M src/mainboard/google/rambi/variants/ninja/gpio.c M src/mainboard/google/rambi/variants/ninja/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/ninja/include/variant/onboard.h M src/mainboard/google/rambi/variants/ninja/include/variant/variant.h M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/orco/gpio.c M src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/orco/include/variant/onboard.h M src/mainboard/google/rambi/variants/orco/include/variant/variant.h M src/mainboard/google/rambi/variants/quawks/gpio.c M src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h M src/mainboard/google/rambi/variants/quawks/include/variant/variant.h M src/mainboard/google/rambi/variants/rambi/gpio.c M src/mainboard/google/rambi/variants/rambi/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/rambi/include/variant/onboard.h M src/mainboard/google/rambi/variants/rambi/include/variant/variant.h M src/mainboard/google/rambi/variants/squawks/gpio.c M src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl M src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h M src/mainboard/google/rambi/variants/squawks/include/variant/variant.h M src/mainboard/google/rambi/variants/sumo/gpio.c M src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h M src/mainboard/google/rambi/variants/sumo/include/variant/variant.h M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/rambi/variants/swanky/gpio.c M src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h M src/mainboard/google/rambi/variants/swanky/include/variant/variant.h M src/mainboard/google/rambi/variants/winky/gpio.c M src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl M src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl M src/mainboard/google/rambi/variants/winky/include/variant/onboard.h M src/mainboard/google/rambi/variants/winky/include/variant/variant.h M src/mainboard/google/rambi/w25q64.c M src/mainboard/google/reef/bootblock.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/reef/ec.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/reef/romstage.c M src/mainboard/google/reef/smihandler.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl M src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/reef/variants/baseboard/memory.c M src/mainboard/google/reef/variants/baseboard/nhlt.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/coral/include/variant/ec.h M src/mainboard/google/reef/variants/coral/include/variant/gpio.h M src/mainboard/google/reef/variants/coral/mainboard.c M src/mainboard/google/reef/variants/nasher/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/nasher/include/variant/ec.h M src/mainboard/google/reef/variants/nasher/include/variant/gpio.h M src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/pyro/include/variant/ec.h M src/mainboard/google/reef/variants/pyro/include/variant/gpio.h M src/mainboard/google/reef/variants/pyro/memory.c M src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/reef/include/variant/ec.h M src/mainboard/google/reef/variants/reef/include/variant/gpio.h M src/mainboard/google/reef/variants/sand/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/sand/include/variant/ec.h M src/mainboard/google/reef/variants/sand/include/variant/gpio.h M src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl M src/mainboard/google/reef/variants/snappy/include/variant/ec.h M src/mainboard/google/reef/variants/snappy/include/variant/gpio.h M src/mainboard/google/reef/variants/snappy/mainboard.c M src/mainboard/google/sarien/bootblock.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/sarien/ec.c M src/mainboard/google/sarien/hda_verb.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/sku.c M src/mainboard/google/sarien/smihandler.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/arcada/include/variant/ec.h M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h M src/mainboard/google/sarien/variants/arcada/include/variant/variant.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h M src/mainboard/google/sarien/variants/sarien/include/variant/variant.h M src/mainboard/google/slippy/acpi/ec.asl M src/mainboard/google/slippy/acpi/mainboard.asl M src/mainboard/google/slippy/acpi/platform.asl M src/mainboard/google/slippy/acpi/superio.asl M src/mainboard/google/slippy/acpi/thermal.asl M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/slippy/ec.c M src/mainboard/google/slippy/ec.h M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/slippy/onboard.h M src/mainboard/google/slippy/romstage.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/slippy/thermal.h M src/mainboard/google/slippy/variant.h M src/mainboard/google/slippy/variants/falco/hda_verb.c M src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/falco/include/variant/gpio.h M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/hda_verb.c M src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/leon/include/variant/gpio.h M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/hda_verb.c M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl M src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/hda_verb.c M src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl M src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/smaug/boardid.c M src/mainboard/google/smaug/bootblock.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/smaug/gpio.h M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/smaug/memlayout.ld M src/mainboard/google/smaug/pmic.c M src/mainboard/google/smaug/pmic.h M src/mainboard/google/smaug/reset.c M src/mainboard/google/smaug/romstage.c M src/mainboard/google/smaug/sdram_configs.c M src/mainboard/google/storm/boardid.c M src/mainboard/google/storm/cdp.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/storm/mainboard.c M src/mainboard/google/storm/memlayout.ld M src/mainboard/google/storm/reset.c M src/mainboard/google/storm/romstage.c M src/mainboard/google/stout/acpi/ec.asl M src/mainboard/google/stout/acpi/mainboard.asl M src/mainboard/google/stout/acpi/platform.asl M src/mainboard/google/stout/acpi/superio.asl M src/mainboard/google/stout/acpi/thermal.asl M src/mainboard/google/stout/acpi_tables.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/dsdt.asl M src/mainboard/google/stout/early_init.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/ec.h M src/mainboard/google/stout/gpio.c M src/mainboard/google/stout/hda_verb.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/onboard.h M src/mainboard/google/stout/thermal.h M src/mainboard/google/trogdor/boardid.c M src/mainboard/google/trogdor/reset.c M src/mainboard/google/veyron/board.h M src/mainboard/google/veyron/boardid.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/memlayout.ld M src/mainboard/google/veyron/reset.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/board.h M src/mainboard/google/veyron_mickey/boardid.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/memlayout.ld M src/mainboard/google/veyron_mickey/reset.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/board.h M src/mainboard/google/veyron_rialto/boardid.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/memlayout.ld M src/mainboard/google/veyron_rialto/reset.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc M src/mainboard/google/volteer/acpi/mipi_camera.asl M src/mainboard/google/volteer/variants/ripto/gpio.c M src/mainboard/google/volteer/variants/ripto/include/variant/ec.h M src/mainboard/google/volteer/variants/ripto/include/variant/gpio.h 1,125 files changed, 2,240 insertions(+), 14,550 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/40079/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I661dbb585bd5198206b998f0a1a0e4cf2d05d4be Gerrit-Change-Number: 40079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/cannonlake: Enables CSE update flow for hatch
by Sridhar Siricilla (Code Review) 05 Apr '20

05 Apr '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39227 ) Change subject: src/soc/intel/cannonlake: Enables CSE update flow for hatch ...................................................................... src/soc/intel/cannonlake: Enables CSE update flow for hatch BUG=b:111330995 Change-Id: I79232b5fdf55a1808b2b9815b462d0a0443ff675 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/soc/intel/common/basecode/fw_update/Kconfig 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39227/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index c411077..2484e12 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -23,9 +23,9 @@ select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE select SYSTEM_TYPE_LAPTOP - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE - select INTEL_CSE_FW_SKU_CUSTOM + select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_PUFF + select RT8168_SET_LED_MODE if BOARD_GOOGLE_PUFF + select INTEL_CSE_UPDATE if BOARD_GOOGLE_HATCH if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/soc/intel/common/basecode/fw_update/Kconfig b/src/soc/intel/common/basecode/fw_update/Kconfig index 2b0835a..2a24bc5 100644 --- a/src/soc/intel/common/basecode/fw_update/Kconfig +++ b/src/soc/intel/common/basecode/fw_update/Kconfig @@ -1,6 +1,7 @@ config INTEL_CSE_UPDATE bool default n + select INTEL_CSE_FW_SKU_CUSTOM config ADD_ME_RW_BINARY bool -- To view, visit https://review.coreboot.org/c/coreboot/+/39227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79232b5fdf55a1808b2b9815b462d0a0443ff675 Gerrit-Change-Number: 39227 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2020