Hello build bot (Jenkins), Paul Menzel, Aaron Durbin,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
......................................................................
mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
The jack detect GPIOs are initialized as dual edge-triggered GPIs,
and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or
ActiveBoth -- a single interrupt is detected on jack insertion or
removal.
The Windows drivers on the other hand, will not function unless the
codec and LPE ACPI interrupts entries are set as in the Intel
Cherrytrail Tianocore platform reference code.
So adjust the ACPI interrupt triggers to make Windows happy, since
Linux doesn't care either way.
Test: boot Linux and Windows 10 on google/edgar, observe functional
audio output for both built-in speakers and headphones.
Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/cyan/acpi/codec_maxim.asl
M src/mainboard/google/cyan/acpi/codec_realtek.asl
2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/24989/3
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Gerrit-Change-Number: 24989
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 )
Change subject: google/cyan: fix ACPI interrupt triggering for audio codecs
......................................................................
Patch Set 2:
> Patch Set 2:
>
> Yes, the question is why it is fixed. Is this because there's an inversion being done somewhere where it shouldn't?
>
> We should dump the the gpio config for the one in question and compare w/ the coreboot settings vs what the kerne's pinmux might be doing.
every cyan variant has the jack detect GPIO defined as 95, PCIE_CLKREQ3B/AUDIO_CODEC_IRQ,
and every one sets it as a GPI, edge triggered both. The kernel cherrytrail pinmux driver actually skips over 95 since it's only listed as having a single/primary function (PCIE_CLKREQ3B)
Given that, 'ActiveBoth' would seem to be the correct setting for both the codec and LPE device. I'll test and adjust the patch if that works here
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Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov,
I'd like you to reexamine a change. Please visit
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Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
......................................................................
mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
Update UPD IIO bifurcation at run-time accroding to different
hardware configurations such as different Riser cards.
With the engineering build FSP, it can only configure IIO for
one socket so my local test need to remove all socket1 elements
from tp_iio_bifur_table.
Tested=OCP Tioga Pass can see socket0 IIO being updated with
an engineering build FSP.
Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
---
M src/mainboard/ocp/tiogapass/romstage.c
M src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
2 files changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39895/6
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39895 )
Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas…
File src/mainboard/ocp/tiogapass/romstage.c:
https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas…
PS5, Line 28: * Read GPIO, SMBUS data or IPMI command to decide
: * IIO bifurcation at run-time.
> there is gpio driver at CB:39453 […]
Picked the related 6 changes but does not boot.
gpio_pad_reset_config_override: Logical to Chipset mapping not found
ASSERTION ERROR: file 'src/soc/intel/common/block/gpio/gpio.c', line 93
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mainboard: Add Acer ES1-572
......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31
PS5, Line 31: - Battery. I have it somewhere.
> yes but no. […]
ACPI code needs to be added to communicate with the EC. Check the vendor's DSDT
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572…
File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572…
PS5, Line 266: device pci 1f.5 off end # PCH SPI
> breaks rom console, too
Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. Is there any reason why this is the case, or should we fix it (preferably with a check against a lockdown related config, CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION or CB:32704)?
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