Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
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mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
Update UPD IIO bifurcation at run-time accroding to different
hardware configurations such as different Riser cards.
With the engineering build FSP, it can only configure IIO for
one socket so my local test need to remove all socket1 elements
from tp_iio_bifur_table.
Tested=OCP Tioga Pass can see socket0 IIO being updated with
an engineering build FSP.
Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
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M src/mainboard/ocp/tiogapass/romstage.c
M src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
2 files changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39895/6
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Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Gerrit-Change-Number: 39895
Gerrit-PatchSet: 6
Gerrit-Owner: Johnny Lin
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39895 )
Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
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Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas…
File src/mainboard/ocp/tiogapass/romstage.c:
https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas…
PS5, Line 28: * Read GPIO, SMBUS data or IPMI command to decide
: * IIO bifurcation at run-time.
> there is gpio driver at CB:39453 […]
Picked the related 6 changes but does not boot.
gpio_pad_reset_config_override: Logical to Chipset mapping not found
ASSERTION ERROR: file 'src/soc/intel/common/block/gpio/gpio.c', line 93
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mainboard: Add Acer ES1-572
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Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31
PS5, Line 31: - Battery. I have it somewhere.
> yes but no. […]
ACPI code needs to be added to communicate with the EC. Check the vendor's DSDT
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572…
File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572…
PS5, Line 266: device pci 1f.5 off end # PCH SPI
> breaks rom console, too
Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. Is there any reason why this is the case, or should we fix it (preferably with a check against a lockdown related config, CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION or CB:32704)?
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