coreboot-gerrit April 2020

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Change in coreboot[master]: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Paul Menzel, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/24989 to look at the new patch set (#3). Change subject: mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs ...................................................................... mb/google/cyan: Adjust ACPI interrupt triggering for audio codecs The jack detect GPIOs are initialized as dual edge-triggered GPIs, and Linux doesn't care if they are set to ActiveLow, ActiveHigh, or ActiveBoth -- a single interrupt is detected on jack insertion or removal. The Windows drivers on the other hand, will not function unless the codec and LPE ACPI interrupts entries are set as in the Intel Cherrytrail Tianocore platform reference code. So adjust the ACPI interrupt triggers to make Windows happy, since Linux doesn't care either way. Test: boot Linux and Windows 10 on google/edgar, observe functional audio output for both built-in speakers and headphones. Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/24989/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/cyan: fix ACPI interrupt triggering for audio codecs
by Matt DeVillier (Code Review) 01 Apr '20

01 Apr '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24989 ) Change subject: google/cyan: fix ACPI interrupt triggering for audio codecs ...................................................................... Patch Set 2: > Patch Set 2: > > Yes, the question is why it is fixed. Is this because there's an inversion being done somewhere where it shouldn't? > > We should dump the the gpio config for the one in question and compare w/ the coreboot settings vs what the kerne's pinmux might be doing. every cyan variant has the jack detect GPIO defined as 95, PCIE_CLKREQ3B/AUDIO_CODEC_IRQ, and every one sets it as a GPI, edge triggered both. The kernel cherrytrail pinmux driver actually skips over 95 since it's only listed as having a single/primary function (PCIE_CLKREQ3B) Given that, 'ActiveBoth' would seem to be the correct setting for both the codec and LPE device. I'll test and adjust the patch if that works here -- To view, visit https://review.coreboot.org/c/coreboot/+/24989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1dd8ece610d761791c060ece2d0aa51addf97ad Gerrit-Change-Number: 24989 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 01:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39895 ) Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time ...................................................................... Patch Set 6: (20 comments) https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h: https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 23: Socket0_Iou0 = 0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 23: Socket0_Iou0 = 0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 24: Socket0_Iou1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 24: Socket0_Iou1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 25: Socket0_Iou2, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 25: Socket0_Iou2, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 26: Socket0_Mcp0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 26: Socket0_Mcp0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 27: Socket0_Mcp1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 27: Socket0_Mcp1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 28: Socket1_Iou0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 28: Socket1_Iou0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 29: Socket1_Iou1, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 29: Socket1_Iou1, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 30: Socket1_Iou2, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 30: Socket1_Iou2, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 31: Socket1_Mcp0, > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 31: Socket1_Mcp0, > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 32: Socket1_Mcp1 > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39895/5/src/mainboard/ocp/tiogapas… PS5, Line 32: Socket1_Mcp1 > code indent should use tabs where possible Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Gerrit-Change-Number: 39895 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Apr 2020 01:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39895 to look at the new patch set (#6). Change subject: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time ...................................................................... mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time Update UPD IIO bifurcation at run-time accroding to different hardware configurations such as different Riser cards. With the engineering build FSP, it can only configure IIO for one socket so my local test need to remove all socket1 elements from tp_iio_bifur_table. Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/tiogapass/romstage.c M src/mainboard/ocp/tiogapass/skxsp_tp_iio.h 2 files changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39895/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/39895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Gerrit-Change-Number: 39895 Gerrit-PatchSet: 6 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time
by Johnny Lin (Code Review) 01 Apr '20

01 Apr '20

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Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Benjamin Doron (Code Review) 01 Apr '20

01 Apr '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere. > yes but no. […] ACPI code needs to be added to communicate with the EC. Check the vendor's DSDT https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 266: device pci 1f.5 off end # PCH SPI > breaks rom console, too Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. Is there any reason why this is the case, or should we fix it (preferably with a check against a lockdown related config, CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION or CB:32704)? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Apr 2020 00:12:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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coreboot-gerrit April 2020