coreboot-gerrit April 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 05 Apr '20

05 Apr '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 73: (2 comments) https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… PS71, Line 85: struct > I renamed it. Done https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/71/src/soc/intel/common/bloc… PS71, Line 229: CSE > Any CSE Firmware SKU has max 3 boot partitions.But, they are layout is specific to CSE SKU. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 73 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Apr 2020 09:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 05 Apr '20

05 Apr '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 ) Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... Patch Set 71: (12 comments) https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/Kconfig: https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 1: INTEL_CSE_UPDATE > Fine with build process. […] Yes, CSE FW update is implemented without the INTEL_CSE_UPDATE Kconfig. In both above 2 cases, coreboot just ignores CSE FW update, switches to RW (if required) and continues to boot. https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 6: ADD_ME_RW_BINARY > Same here. This config will not be required. Yes, this is not required. I removed the same. https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 18: ME_RW_FILE > In order to keep consistent naming, I think: […] Yes,implemented the same. But I used below KConfigs for the same. I have used below KConfigs SOC_INTEL_CSE_RW_CBFS_NAME SOC_INTEL_CSE_RW_FILE https://review.coreboot.org/c/coreboot/+/35403/2/src/soc/intel/common/basec… File src/soc/intel/common/basecode/fw_update/cse_update.c: https://review.coreboot.org/c/coreboot/+/35403/2/src/soc/intel/common/basec… PS2, Line 377: Previous update is incomplete or RW Boot partition is corrupte > can we differentiate between the 2 possibilities here? Done https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/cse_update.c: https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 294: if (rec_mode) { : printk(BIOS_DEBUG, "me_fwu: Skip FW update in the recovery path\n"); : return; : } > Done Done https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 317: if (get_cbfs_me_rw_ver(&me_rw_ver_cbfs) < 0) { : printk(BIOS_ERR, "me_fwu: Failed to get cbfs ME for update\n"); : goto failed; : } : > The same blob contains RW FW + Version. Done https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 332: rdev_mmap > I organized the code as above but deviated little bit. Please check. Done https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 346: if (!cse_check_rw_status(&me_rw_part_status)) { : printk(BIOS_ERR, "me_fwu: me rw status check fail\n"); : goto failed; : } > I pushed this code after recovery check. […] Done https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/base… PS67, Line 395: printk(BIOS_ERR, "me_fwu: Failed %s\n", __func__); : do_global_reset(); > No where in this path I see recovery being triggered. […] May I know your comment on triggering recovery through set_recovery_mode_into_vbnv(1) API and followed do_global_reset()? https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/bloc… PS67, Line 866: cse_enable_fw_sku_custom > As mentioned here: https://review.coreboot. […] I made small change to point E) Check if RW update is required. It can be based on two things: (i) RW's signature is not matching BTW,If RW signature is not valid, status id for RW partition is set to 1 (ii) If status ID for RW partition is 0 and RW version in boot info does not match RW version in CBFS. If either of the above is yes, update is required https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/bloc… PS67, Line 885: * TODO: Check to move this to bootblock */ > It is not possible to move to bootblock. […] Ack https://review.coreboot.org/c/coreboot/+/35403/67/src/soc/intel/common/bloc… PS67, Line 887: rec_mode && current_bp != BP1 > I mentioned this on https://review.coreboot. […] do_global_reset() guarantees reset. So, EC/H1 help is not required here. -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 71 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Apr 2020 09:28:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 05 Apr '20

05 Apr '20

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Change in coreboot[master]: mb/volteer: enable Early Command Training
by Paul Menzel (Code Review) 05 Apr '20

05 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40023 ) Change subject: mb/volteer: enable Early Command Training ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/40023/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40023/5//COMMIT_MSG@11 PS5, Line 11: ECT enabled. > This is enabled on all platforms, we had temporarily disabled it until MRC matures. […] Thanks, but that is not what the commit message says. It says “FSP 2527 requires” this. You answered, that it was disabled due to a bug with MRC stuff. (What is MRC in regards to FSP? I only know the term *Memory Reference Code* which was used for Google Chromebooks before FSP was introduced. -- To view, visit https://review.coreboot.org/c/coreboot/+/40023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3 Gerrit-Change-Number: 40023 Gerrit-PatchSet: 6 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Apr 2020 08:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver
by Paul Menzel (Code Review) 05 Apr '20

05 Apr '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39425 ) Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver ...................................................................... Patch Set 19: (2 comments) https://review.coreboot.org/c/coreboot/+/39425/19//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39425/19//COMMIT_MSG@13 PS19, Line 13: intetool inteltool https://review.coreboot.org/c/coreboot/+/39425/19//COMMIT_MSG@18 PS19, Line 18: kernel for Lewisburg PCH GPIO hardware [2] 1. Please add a dot/period at the end of sentences. 2. Please mention the used Liunx version. -- To view, visit https://review.coreboot.org/c/coreboot/+/39425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5 Gerrit-Change-Number: 39425 Gerrit-PatchSet: 19 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Apr 2020 08:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: assert.h: Add a tag parameter to dead_code()
by Nico Huber (Code Review) 04 Apr '20

04 Apr '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40140 ) Change subject: assert.h: Add a tag parameter to dead_code() ...................................................................... assert.h: Add a tag parameter to dead_code() When dead_code() is used in inline functions in a header file, the generated function names (based on the line number) may collide with a dead_code() in the code file. Now that we are hit by such a case, we need a quick solution: Add a tag argument for all invocations in header files. Change-Id: I0c548ce998cf8e28ae9f76b5c0ea5630b4e91ae2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/assert.h M src/security/vboot/misc.h 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/40140/1 diff --git a/src/include/assert.h b/src/include/assert.h index 990cee1..fbaf11a 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -65,13 +65,13 @@ * ramstage/lib/bootmode.o: In function `display_init_required': * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' */ -#define __dead_code(line) do { \ - extern void dead_code_assertion_failed_at_line_##line(void) \ +#define __dead_code(tag, line) do { \ + extern void dead_code_assertion_failed##tag##_at_line_##line(void) \ __attribute__((noreturn)); \ - dead_code_assertion_failed_at_line_##line(); \ + dead_code_assertion_failed##tag##_at_line_##line(); \ } while (0) -#define _dead_code(line) __dead_code(line) -#define dead_code() _dead_code(__LINE__) +#define _dead_code(tag, line) __dead_code(tag, line) +#define dead_code(tag) _dead_code(tag, __LINE__) /* This can be used in the context of an expression of type 'type'. */ #define dead_code_t(type) ({ \ diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index fd422b2..22cc750 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -53,7 +53,7 @@ else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return ENV_BOOTBLOCK; else - dead_code(); + dead_code(_in_vboot_misc_h); } static inline int verstage_should_load(void) @@ -82,7 +82,7 @@ /* Post-RAM stages are "after the romstage" */ return !ENV_ROMSTAGE_OR_BEFORE; } else { - dead_code(); + dead_code(_in_vboot_misc_h); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c548ce998cf8e28ae9f76b5c0ea5630b4e91ae2 Gerrit-Change-Number: 40140 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in gerrit-avatars[master]: Add avatar for Felix Held
by Felix Held (Code Review) 04 Apr '20

04 Apr '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/40139 ) Change subject: Add avatar for Felix Held ...................................................................... Add avatar for Felix Held Signed-off-by: Felix Held <felix-github(a)felixheld.de> Change-Id: I0a073d0e09a0897d6e0d464afc87f48bb55654c9 --- A 1000476.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/39/40139/1 diff --git a/1000476.jpg b/1000476.jpg new file mode 100644 index 0000000..76c4848 --- /dev/null +++ b/1000476.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/40139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I0a073d0e09a0897d6e0d464afc87f48bb55654c9 Gerrit-Change-Number: 40139 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/samsung/stumpy: Drop ACPI brightness controls
by Matt DeVillier (Code Review) 04 Apr '20

04 Apr '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40046 ) Change subject: mb/samsung/stumpy: Drop ACPI brightness controls ...................................................................... mb/samsung/stumpy: Drop ACPI brightness controls Stumpy is a Chromebox without a built-in display, and now that default_brightness_levels.asl is no longer required for all boards in a platform, drop it and the default panel definition. Test: build/boot stumpy Change-Id: Iaf475f3529dd19330ea46532e9ffd20b44893f7e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/dsdt.asl 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40046/1 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 8e79b39..df640b5 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -1,6 +1,4 @@ chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 425efa8..dd2b37e 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -39,8 +39,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/40046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf475f3529dd19330ea46532e9ffd20b44893f7e Gerrit-Change-Number: 40046 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 04 Apr '20

04 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40058 ) Change subject: src/soc: Use SPDX for GPL-2.0-only files ...................................................................... src/soc: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I0bbe12b2b0ac84ff945b107bc51b11083e178733 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/acpi/lpc.asl M src/soc/amd/common/acpi/thermal_zone.asl M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/alink/alink.c M src/soc/amd/common/block/cpu/car/ap_exit_car.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/car/exit_car.S M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/hda/hda.c M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h M src/soc/amd/common/block/include/amdblocks/alink.h M src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/include/amdblocks/car.h M src/soc/amd/common/block/include/amdblocks/dimm_spd.h M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/image.h M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/include/amdblocks/s3_resume.h M src/soc/amd/common/block/include/amdblocks/sata.h M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/common/block/pci/amd_pci_mmconf.c M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/pi/heapmanager.c M src/soc/amd/common/block/pi/image.c M src/soc/amd/common/block/pi/refcode_loader.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/amd/common/block/sata/sata.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/acpi/acpi_wake_source.asl M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/picasso/acpi/pci_int.asl M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/acpi/sleepstates.asl M src/soc/amd/picasso/acpi/soc.asl M src/soc/amd/picasso/acpi/usb.asl M src/soc/amd/picasso/cfg_util.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/finalize.c M src/soc/amd/picasso/gpio.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/pmutil.c M src/soc/amd/picasso/reset.c M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/sata.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/picasso/uart.c M src/soc/amd/picasso/usb.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/acpi_wake_source.asl M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/pci_int.asl M src/soc/amd/stoneyridge/acpi/pcie.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sleepstates.asl M src/soc/amd/stoneyridge/acpi/soc.asl M src/soc/amd/stoneyridge/acpi/usb.asl M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/finalize.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/i2c.c M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/soc/cpu.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/mca.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/pmutil.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/uart.c M src/soc/amd/stoneyridge/usb.c M src/soc/cavium/cn81xx/bl31_plat_params.c M src/soc/cavium/cn81xx/bootblock.c M src/soc/cavium/cn81xx/bootblock_custom.S M src/soc/cavium/cn81xx/cbmem.c M src/soc/cavium/cn81xx/chip.h M src/soc/cavium/cn81xx/clock.c M src/soc/cavium/cn81xx/cpu.c M src/soc/cavium/cn81xx/cpu_secondary.S M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/include/atf/plat_params.h M src/soc/cavium/cn81xx/include/soc/addressmap.h M src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h M src/soc/cavium/cn81xx/include/soc/clock.h M src/soc/cavium/cn81xx/include/soc/cpu.h M src/soc/cavium/cn81xx/include/soc/ecam0.h M src/soc/cavium/cn81xx/include/soc/gpio.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/cavium/cn81xx/include/soc/mmu.h M src/soc/cavium/cn81xx/include/soc/sdram.h M src/soc/cavium/cn81xx/include/soc/soc.h M src/soc/cavium/cn81xx/include/soc/spi.h M src/soc/cavium/cn81xx/include/soc/timer.h M src/soc/cavium/cn81xx/include/soc/twsi.h M src/soc/cavium/cn81xx/include/soc/uart.h M src/soc/cavium/cn81xx/mmu.c M src/soc/cavium/cn81xx/sdram.c M src/soc/cavium/cn81xx/soc.c M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/cn81xx/uart.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/cavium/common/bootblock.c M src/soc/cavium/common/ecam.c M src/soc/cavium/common/include/soc/bootblock.h M src/soc/cavium/common/include/soc/ecam.h M src/soc/cavium/common/include/soc/sysreg.h M src/soc/cavium/common/pci/chip.h M src/soc/cavium/common/pci/uart.c M src/soc/intel/apollolake/acpi/dptf.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/platform.asl M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/acpi/scs.asl M src/soc/intel/apollolake/acpi/xhci.asl M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/elog.c M src/soc/intel/apollolake/i2c.c M src/soc/intel/apollolake/include/soc/gpe.h M src/soc/intel/apollolake/include/soc/itss.h M src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/apollolake/include/soc/meminit.h M src/soc/intel/apollolake/include/soc/p2sb.h M src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/apollolake/include/soc/pnpconfig.h M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/apollolake/include/soc/soc_chip.h M src/soc/intel/apollolake/meminit.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/apollolake/reset.c M src/soc/intel/apollolake/sd.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/apollolake/xhci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/device_nvs.asl M src/soc/intel/baytrail/acpi/dptf/charger.asl M src/soc/intel/baytrail/acpi/dptf/cpu.asl M src/soc/intel/baytrail/acpi/dptf/dptf.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/gpio.asl M src/soc/intel/baytrail/acpi/irq_helper.h M src/soc/intel/baytrail/acpi/irqlinks.asl M src/soc/intel/baytrail/acpi/irqroute.asl M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/baytrail/acpi/lpe.asl M src/soc/intel/baytrail/acpi/lpss.asl M src/soc/intel/baytrail/acpi/pcie.asl M src/soc/intel/baytrail/acpi/platform.asl M src/soc/intel/baytrail/acpi/scc.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/acpi/xhci.asl M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/chip.h M src/soc/intel/baytrail/cpu.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/ehci.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/baytrail/include/soc/device_nvs.h M src/soc/intel/baytrail/include/soc/ehci.h M src/soc/intel/baytrail/include/soc/gfx.h M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/include/soc/iomap.h M src/soc/intel/baytrail/include/soc/iosf.h M src/soc/intel/baytrail/include/soc/irq.h M src/soc/intel/baytrail/include/soc/lpc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/baytrail/include/soc/pattrs.h M src/soc/intel/baytrail/include/soc/pci_devs.h M src/soc/intel/baytrail/include/soc/pcie.h M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/include/soc/sata.h M src/soc/intel/baytrail/include/soc/smm.h M src/soc/intel/baytrail/include/soc/spi.h M src/soc/intel/baytrail/include/soc/xhci.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/placeholders.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/refcode.c M src/soc/intel/baytrail/romstage/gfx.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/scc.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/baytrail/xhci.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/device_nvs.asl M src/soc/intel/braswell/acpi/dptf/charger.asl M src/soc/intel/braswell/acpi/dptf/cpu.asl M src/soc/intel/braswell/acpi/dptf/dptf.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/wifi.asl M src/soc/intel/braswell/acpi/dptf/wwan.asl M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/gpio.asl M src/soc/intel/braswell/acpi/irq_helper.h M src/soc/intel/braswell/acpi/irqlinks.asl M src/soc/intel/braswell/acpi/irqroute.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/acpi/lpss.asl M src/soc/intel/braswell/acpi/platform.asl M src/soc/intel/braswell/acpi/scc.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/acpi/xhci.asl M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/gpio_support.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/include/soc/device_nvs.h M src/soc/intel/braswell/include/soc/ehci.h M src/soc/intel/braswell/include/soc/gfx.h M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/include/soc/gpio_defs.h M src/soc/intel/braswell/include/soc/hda.h M src/soc/intel/braswell/include/soc/iomap.h M src/soc/intel/braswell/include/soc/iosf.h M src/soc/intel/braswell/include/soc/irq.h M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/braswell/include/soc/pattrs.h M src/soc/intel/braswell/include/soc/pci_devs.h M src/soc/intel/braswell/include/soc/pcie.h M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/include/soc/ramstage.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/include/soc/sata.h M src/soc/intel/braswell/include/soc/smbus.h M src/soc/intel/braswell/include/soc/smm.h M src/soc/intel/braswell/include/soc/spi.h M src/soc/intel/braswell/include/soc/xhci.h M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/placeholders.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/smbus.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/braswell/xhci.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/adsp.asl M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/device_nvs.asl M src/soc/intel/broadwell/acpi/ehci.asl M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/acpi/gpio.asl M src/soc/intel/broadwell/acpi/hda.asl M src/soc/intel/broadwell/acpi/irqlinks.asl M src/soc/intel/broadwell/acpi/lpc.asl M src/soc/intel/broadwell/acpi/pch.asl M src/soc/intel/broadwell/acpi/pci_irqs.asl M src/soc/intel/broadwell/acpi/pcie.asl M src/soc/intel/broadwell/acpi/pcie_port.asl M src/soc/intel/broadwell/acpi/platform.asl M src/soc/intel/broadwell/acpi/sata.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/soc/intel/broadwell/acpi/smbus.asl M src/soc/intel/broadwell/acpi/systemagent.asl M src/soc/intel/broadwell/acpi/xhci.asl M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/elog.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/broadwell/include/soc/adsp.h M src/soc/intel/broadwell/include/soc/cpu.h M src/soc/intel/broadwell/include/soc/device_nvs.h M src/soc/intel/broadwell/include/soc/ehci.h M src/soc/intel/broadwell/include/soc/gpio.h M src/soc/intel/broadwell/include/soc/igd.h M src/soc/intel/broadwell/include/soc/iobp.h M src/soc/intel/broadwell/include/soc/iomap.h M src/soc/intel/broadwell/include/soc/lpc.h M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/include/soc/pei_wrapper.h M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/include/soc/rcba.h M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/include/soc/sata.h M src/soc/intel/broadwell/include/soc/serialio.h M src/soc/intel/broadwell/include/soc/smbus.h M src/soc/intel/broadwell/include/soc/spi.h M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/broadwell/romstage/cpu.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/smi.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/tsc_freq.c M src/soc/intel/broadwell/usb_debug.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/dptf.asl M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/cannonlake/acpi/ish.asl M src/soc/intel/cannonlake/acpi/pch_glan.asl M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/pcie.asl M src/soc/intel/cannonlake/acpi/platform.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/acpi/serialio.asl M src/soc/intel/cannonlake/acpi/smbus.asl M src/soc/intel/cannonlake/acpi/xhci.asl M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/cpu.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/i2c.c M src/soc/intel/cannonlake/include/soc/bootblock.h M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/gpe.h M src/soc/intel/cannonlake/include/soc/gpio.h M src/soc/intel/cannonlake/include/soc/gpio_common.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/irq.h M src/soc/intel/cannonlake/include/soc/itss.h M src/soc/intel/cannonlake/include/soc/lpc.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/cannonlake/include/soc/nvs.h M src/soc/intel/cannonlake/include/soc/p2sb.h M src/soc/intel/cannonlake/include/soc/pch.h M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/include/soc/ramstage.h M src/soc/intel/cannonlake/include/soc/romstage.h M src/soc/intel/cannonlake/include/soc/sata.h M src/soc/intel/cannonlake/include/soc/serialio.h M src/soc/intel/cannonlake/include/soc/smbus.h M src/soc/intel/cannonlake/include/soc/soc_chip.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/include/soc/usb.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/me.c M src/soc/intel/cannonlake/p2sb.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/pch.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/cannonlake/romstage/systemagent.c M src/soc/intel/cannonlake/sd.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/cannonlake/xhci.c M src/soc/intel/common/acpi/acpi_debug.asl M src/soc/intel/common/acpi/acpi_wake_source.asl M src/soc/intel/common/acpi/dptf/charger.asl M src/soc/intel/common/acpi/dptf/cpu.asl M src/soc/intel/common/acpi/dptf/dptf.asl M src/soc/intel/common/acpi/dptf/fan.asl M src/soc/intel/common/acpi/dptf/thermal.asl M src/soc/intel/common/acpi/pci_osc.asl M src/soc/intel/common/acpi/pcr.asl M src/soc/intel/common/acpi/platform.asl M src/soc/intel/common/acpi/sgx.asl M src/soc/intel/common/acpi/wifi.asl M src/soc/intel/common/acpi_wake_source.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/ipu.asl M src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/common/block/chip/chip.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car_fsp.S M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/imc/imc.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/common/block/include/intelblocks/gspi.h M src/soc/intel/common/block/include/intelblocks/imc.h M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/include/intelblocks/pcie_rp.h M src/soc/intel/common/block/include/intelblocks/pcr.h M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/include/intelblocks/rtc.h M src/soc/intel/common/block/include/intelblocks/sd.h M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/include/intelblocks/smbus.h M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/include/intelblocks/sram.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/include/intelblocks/xdci.h M src/soc/intel/common/block/include/intelblocks/xhci.h M src/soc/intel/common/block/itss/itss.c M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pcie/pcie_rp.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/rtc/rtc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/smbus/smbuslib.c M src/soc/intel/common/block/smbus/smbuslib.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/common/block/smm/smm.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/block/thermal/thermal.c M src/soc/intel/common/block/timer/timer.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/elog.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/hda_verb.c M src/soc/intel/common/hda_verb.h M src/soc/intel/common/mma.c M src/soc/intel/common/mma.h M src/soc/intel/common/nhlt.c M src/soc/intel/common/pch/include/intelpch/lockdown.h M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/common/reset.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/common/tpm_tis.c M src/soc/intel/common/vbt.c M src/soc/intel/common/vbt.h M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/irqlinks.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/npk.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/denverton_ns/acpi/pcie_port.asl M src/soc/intel/denverton_ns/acpi/pmc.asl M src/soc/intel/denverton_ns/acpi/sata.asl M src/soc/intel/denverton_ns/acpi/sata2.asl M src/soc/intel/denverton_ns/acpi/smbus.asl M src/soc/intel/denverton_ns/acpi/smbus2.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl M src/soc/intel/denverton_ns/acpi/xhci.asl M src/soc/intel/denverton_ns/chip.h M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/fiamux.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/hob_mem.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/bootblock.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/denverton_ns/include/soc/fiamux.h M src/soc/intel/denverton_ns/include/soc/gpio.h M src/soc/intel/denverton_ns/include/soc/gpio_defs.h M src/soc/intel/denverton_ns/include/soc/gpio_dnv.h M src/soc/intel/denverton_ns/include/soc/hob_mem.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/lpc.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/denverton_ns/include/soc/nvs.h M src/soc/intel/denverton_ns/include/soc/p2sb.h M src/soc/intel/denverton_ns/include/soc/pattrs.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pcr.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/include/soc/ramstage.h M src/soc/intel/denverton_ns/include/soc/sata.h M src/soc/intel/denverton_ns/include/soc/smbus.h M src/soc/intel/denverton_ns/include/soc/smm.h M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/include/soc/uart.h M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/reset.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/tsc_freq.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/icelake/acpi/pch_glan.asl M src/soc/intel/icelake/acpi/pch_hda.asl M src/soc/intel/icelake/acpi/pcie.asl M src/soc/intel/icelake/acpi/platform.asl M src/soc/intel/icelake/acpi/scs.asl M src/soc/intel/icelake/acpi/serialio.asl M src/soc/intel/icelake/acpi/smbus.asl M src/soc/intel/icelake/acpi/xhci.asl M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/cpu.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/elog.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/i2c.c M src/soc/intel/icelake/include/soc/bootblock.h M src/soc/intel/icelake/include/soc/cpu.h M src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/gpe.h M src/soc/intel/icelake/include/soc/gpio.h M src/soc/intel/icelake/include/soc/gpio_defs.h M src/soc/intel/icelake/include/soc/gpio_soc_defs.h M src/soc/intel/icelake/include/soc/iomap.h M src/soc/intel/icelake/include/soc/irq.h M src/soc/intel/icelake/include/soc/itss.h M src/soc/intel/icelake/include/soc/me.h M src/soc/intel/icelake/include/soc/msr.h M src/soc/intel/icelake/include/soc/nvs.h M src/soc/intel/icelake/include/soc/p2sb.h M src/soc/intel/icelake/include/soc/pch.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pcr_ids.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/include/soc/pmc.h M src/soc/intel/icelake/include/soc/ramstage.h M src/soc/intel/icelake/include/soc/romstage.h M src/soc/intel/icelake/include/soc/serialio.h M src/soc/intel/icelake/include/soc/smbus.h M src/soc/intel/icelake/include/soc/soc_chip.h M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/include/soc/usb.h M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/p2sb.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/reset.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/romstage/pch.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/icelake/romstage/systemagent.c M src/soc/intel/icelake/sd.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/systemagent.c M src/soc/intel/icelake/uart.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio_op.asl M src/soc/intel/jasperlake/acpi/ipu.asl M src/soc/intel/jasperlake/acpi/ish.asl M src/soc/intel/jasperlake/acpi/pch_glan.asl M src/soc/intel/jasperlake/acpi/pch_hda.asl M src/soc/intel/jasperlake/acpi/pcie.asl M src/soc/intel/jasperlake/acpi/platform.asl M src/soc/intel/jasperlake/acpi/pmc.asl M src/soc/intel/jasperlake/acpi/scs.asl M src/soc/intel/jasperlake/acpi/serialio.asl M src/soc/intel/jasperlake/acpi/smbus.asl M src/soc/intel/jasperlake/acpi/xhci.asl M src/soc/intel/jasperlake/bootblock/bootblock.c M src/soc/intel/jasperlake/bootblock/cpu.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/report_platform.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/i2c.c M src/soc/intel/jasperlake/include/soc/bootblock.h M src/soc/intel/jasperlake/include/soc/cpu.h M src/soc/intel/jasperlake/include/soc/espi.h M src/soc/intel/jasperlake/include/soc/gpe.h M src/soc/intel/jasperlake/include/soc/gpio.h M src/soc/intel/jasperlake/include/soc/gpio_defs.h M src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h M src/soc/intel/jasperlake/include/soc/iomap.h M src/soc/intel/jasperlake/include/soc/irq.h M src/soc/intel/jasperlake/include/soc/itss.h M src/soc/intel/jasperlake/include/soc/me.h M src/soc/intel/jasperlake/include/soc/meminit.h M src/soc/intel/jasperlake/include/soc/msr.h M src/soc/intel/jasperlake/include/soc/nvs.h M src/soc/intel/jasperlake/include/soc/p2sb.h M src/soc/intel/jasperlake/include/soc/pch.h M src/soc/intel/jasperlake/include/soc/pci_devs.h M src/soc/intel/jasperlake/include/soc/pcr_ids.h M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/include/soc/pmc.h M src/soc/intel/jasperlake/include/soc/ramstage.h M src/soc/intel/jasperlake/include/soc/romstage.h M src/soc/intel/jasperlake/include/soc/serialio.h M src/soc/intel/jasperlake/include/soc/smbus.h M src/soc/intel/jasperlake/include/soc/soc_chip.h M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/include/soc/usb.h M src/soc/intel/jasperlake/lockdown.c M src/soc/intel/jasperlake/meminit.c M src/soc/intel/jasperlake/p2sb.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/jasperlake/reset.c M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/jasperlake/romstage/pch.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/systemagent.c M src/soc/intel/jasperlake/sd.c M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/jasperlake/uart.c M src/soc/intel/quark/acpi.c M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/chip.c M src/soc/intel/quark/chip.h M src/soc/intel/quark/ehci.c M src/soc/intel/quark/fsp_params.c M src/soc/intel/quark/gpio_i2c.c M src/soc/intel/quark/i2c.c M src/soc/intel/quark/include/soc/acpi.h M src/soc/intel/quark/include/soc/car.h M src/soc/intel/quark/include/soc/cpu.h M src/soc/intel/quark/include/soc/i2c.h M src/soc/intel/quark/include/soc/iomap.h M src/soc/intel/quark/include/soc/pci_devs.h M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/include/soc/romstage.h M src/soc/intel/quark/include/soc/sd.h M src/soc/intel/quark/include/soc/spi.h M src/soc/intel/quark/include/soc/storage_test.h M src/soc/intel/quark/lpc.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/quark/reg_access.c M src/soc/intel/quark/reset.c M src/soc/intel/quark/romstage/car.c M src/soc/intel/quark/romstage/debug.c M src/soc/intel/quark/romstage/fsp_params.c M src/soc/intel/quark/romstage/mtrr.c M src/soc/intel/quark/romstage/pcie.c M src/soc/intel/quark/romstage/report_platform.c M src/soc/intel/quark/romstage/romstage.c M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/quark/tsc_freq.c M src/soc/intel/quark/uart.c M src/soc/intel/quark/uart_common.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/gpio.asl M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/pci_irqs.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/skylake/acpi/platform.asl M src/soc/intel/skylake/acpi/pmc.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/serialio.asl M src/soc/intel/skylake/acpi/smbus.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/i2c.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/gpe.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h M src/soc/intel/skylake/include/soc/gpio_soc_defs.h M src/soc/intel/skylake/include/soc/interrupt.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/irq.h M src/soc/intel/skylake/include/soc/itss.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/p2sb.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/skylake/include/soc/ramstage.h M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/include/soc/serialio.h M src/soc/intel/skylake/include/soc/smbus.h M src/soc/intel/skylake/include/soc/soc_chip.h M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/include/soc/usb.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/nhlt/dmic.c M src/soc/intel/skylake/nhlt/max98357.c M src/soc/intel/skylake/nhlt/max98373.c M src/soc/intel/skylake/nhlt/max98927.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/nhlt/ssm4567.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/sd.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/skylake/xhci.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_op.asl M src/soc/intel/tigerlake/acpi/ipu.asl M src/soc/intel/tigerlake/acpi/ish.asl M src/soc/intel/tigerlake/acpi/pch_glan.asl M src/soc/intel/tigerlake/acpi/pch_hda.asl M src/soc/intel/tigerlake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/platform.asl M src/soc/intel/tigerlake/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/scs.asl M src/soc/intel/tigerlake/acpi/serialio.asl M src/soc/intel/tigerlake/acpi/smbus.asl M src/soc/intel/tigerlake/acpi/xhci.asl M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/cpu.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/i2c.c M src/soc/intel/tigerlake/include/soc/bootblock.h M src/soc/intel/tigerlake/include/soc/cpu.h M src/soc/intel/tigerlake/include/soc/espi.h M src/soc/intel/tigerlake/include/soc/gpe.h M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/tigerlake/include/soc/gpio_defs.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/irq.h M src/soc/intel/tigerlake/include/soc/itss.h M src/soc/intel/tigerlake/include/soc/me.h M src/soc/intel/tigerlake/include/soc/msr.h M src/soc/intel/tigerlake/include/soc/nvs.h M src/soc/intel/tigerlake/include/soc/p2sb.h M src/soc/intel/tigerlake/include/soc/pch.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/include/soc/pcr_ids.h M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/include/soc/pmc.h M src/soc/intel/tigerlake/include/soc/ramstage.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/include/soc/serialio.h M src/soc/intel/tigerlake/include/soc/smbus.h M src/soc/intel/tigerlake/include/soc/soc_chip.h M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/include/soc/usb.h M src/soc/intel/tigerlake/lockdown.c M src/soc/intel/tigerlake/p2sb.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/reset.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/systemagent.c M src/soc/intel/tigerlake/sd.c M src/soc/intel/tigerlake/smihandler.c M src/soc/intel/tigerlake/smmrelocate.c M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/tigerlake/uart.c M src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl M src/soc/intel/xeon_sp/skx/include/soc/nvs.h M src/soc/mediatek/common/cbmem.c M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/ddp_common.h M src/soc/mediatek/common/include/soc/dsi_common.h M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/common/include/soc/mmu_operations.h M src/soc/mediatek/common/include/soc/mtcmos.h M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/include/soc/timer.h M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/include/soc/wdt.h M src/soc/mediatek/common/memory_test.c M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/reset.c M src/soc/mediatek/common/rtc.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/bootblock.c M src/soc/mediatek/mt8173/da9212.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/addressmap.h M src/soc/mediatek/mt8173/include/soc/da9212.h M src/soc/mediatek/mt8173/include/soc/ddp.h M src/soc/mediatek/mt8173/include/soc/dramc_common.h M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8173/include/soc/dramc_register.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8173/include/soc/emi.h M src/soc/mediatek/mt8173/include/soc/flash_controller.h M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/mediatek/mt8173/include/soc/gpio_base.h M src/soc/mediatek/mt8173/include/soc/i2c.h M src/soc/mediatek/mt8173/include/soc/infracfg.h M src/soc/mediatek/mt8173/include/soc/mcucfg.h M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/mipi.h M src/soc/mediatek/mt8173/include/soc/mt6311.h M src/soc/mediatek/mt8173/include/soc/mt6391.h M src/soc/mediatek/mt8173/include/soc/pericfg.h M src/soc/mediatek/mt8173/include/soc/pll.h M src/soc/mediatek/mt8173/include/soc/pmic_wrap.h M src/soc/mediatek/mt8173/include/soc/rtc.h M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/include/soc/spm.h M src/soc/mediatek/mt8173/include/soc/symbols.h M src/soc/mediatek/mt8173/include/soc/usb.h M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mmu_operations.c M src/soc/mediatek/mt8173/mt6311.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8173/rtc.c M src/soc/mediatek/mt8173/soc.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8173/usb.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/bootblock.c M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/decompressor.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_param.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/addressmap.h M src/soc/mediatek/mt8183/include/soc/auxadc.h M src/soc/mediatek/mt8183/include/soc/ddp.h M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/mediatek/mt8183/include/soc/efuse.h M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/include/soc/flash_controller.h M src/soc/mediatek/mt8183/include/soc/gpio.h M src/soc/mediatek/mt8183/include/soc/gpio_base.h M src/soc/mediatek/mt8183/include/soc/i2c.h M src/soc/mediatek/mt8183/include/soc/infracfg.h M src/soc/mediatek/mt8183/include/soc/mcucfg.h M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/include/soc/mt8183.h M src/soc/mediatek/mt8183/include/soc/pll.h M src/soc/mediatek/mt8183/include/soc/pmic_wrap.h M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/include/soc/smi.h M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/mediatek/mt8183/include/soc/sspm.h M src/soc/mediatek/mt8183/include/soc/usb.h M src/soc/mediatek/mt8183/memory.c M src/soc/mediatek/mt8183/mmu_operations.c M src/soc/mediatek/mt8183/mt6358.c M src/soc/mediatek/mt8183/mt8183.c M src/soc/mediatek/mt8183/mtcmos.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8183/soc.c M src/soc/mediatek/mt8183/spi.c M src/soc/mediatek/mt8183/spm.c M src/soc/mediatek/mt8183/sspm.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra/apbmisc.h M src/soc/nvidia/tegra/displayport.h M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra/gpio.h M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra/i2c.h M src/soc/nvidia/tegra/pingroup.c M src/soc/nvidia/tegra/pingroup.h M src/soc/nvidia/tegra/pinmux.c M src/soc/nvidia/tegra/pinmux.h M src/soc/nvidia/tegra/software_i2c.c M src/soc/nvidia/tegra/types.h M src/soc/nvidia/tegra/usb.c M src/soc/nvidia/tegra/usb.h M src/soc/nvidia/tegra124/bootblock.c M src/soc/nvidia/tegra124/bootblock_asm.S M src/soc/nvidia/tegra124/cache.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/i2c.c M src/soc/nvidia/tegra124/include/soc/addressmap.h M src/soc/nvidia/tegra124/include/soc/cache.h M src/soc/nvidia/tegra124/include/soc/clk_rst.h M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/include/soc/display.h M src/soc/nvidia/tegra124/include/soc/dma.h M src/soc/nvidia/tegra124/include/soc/early_configs.h M src/soc/nvidia/tegra124/include/soc/emc.h M src/soc/nvidia/tegra124/include/soc/flow.h M src/soc/nvidia/tegra124/include/soc/gpio.h M src/soc/nvidia/tegra124/include/soc/maincpu.h M src/soc/nvidia/tegra124/include/soc/mc.h M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/pingroup.h M src/soc/nvidia/tegra124/include/soc/pinmux.h M src/soc/nvidia/tegra124/include/soc/pmc.h M src/soc/nvidia/tegra124/include/soc/power.h M src/soc/nvidia/tegra124/include/soc/sdram.h M src/soc/nvidia/tegra124/include/soc/sdram_param.h M src/soc/nvidia/tegra124/include/soc/spi.h M src/soc/nvidia/tegra124/include/soc/sysctr.h M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.ld M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra124/verstage.c M src/soc/nvidia/tegra210/addressmap.c M src/soc/nvidia/tegra210/ape.c M src/soc/nvidia/tegra210/arm_tf.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/bootblock_asm.S M src/soc/nvidia/tegra210/cbmem.c M src/soc/nvidia/tegra210/ccplex.c M src/soc/nvidia/tegra210/chip.h M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/cpu.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/gic.c M src/soc/nvidia/tegra210/i2c.c M src/soc/nvidia/tegra210/i2c6.c M src/soc/nvidia/tegra210/include/soc/addressmap.h M src/soc/nvidia/tegra210/include/soc/ccplex.h M src/soc/nvidia/tegra210/include/soc/clk_rst.h M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/clst_clk.h M src/soc/nvidia/tegra210/include/soc/console_uart.h M src/soc/nvidia/tegra210/include/soc/cpu.h M src/soc/nvidia/tegra210/include/soc/display.h M src/soc/nvidia/tegra210/include/soc/dma.h M src/soc/nvidia/tegra210/include/soc/emc.h M src/soc/nvidia/tegra210/include/soc/flow.h M src/soc/nvidia/tegra210/include/soc/flow_ctrl.h M src/soc/nvidia/tegra210/include/soc/funitcfg.h M src/soc/nvidia/tegra210/include/soc/gpio.h M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/include/soc/maincpu.h M src/soc/nvidia/tegra210/include/soc/mc.h M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/mipi-phy.h M src/soc/nvidia/tegra210/include/soc/mipi_display.h M src/soc/nvidia/tegra210/include/soc/mipi_dsi.h M src/soc/nvidia/tegra210/include/soc/mmu_operations.h M src/soc/nvidia/tegra210/include/soc/mtc.h M src/soc/nvidia/tegra210/include/soc/padconfig.h M src/soc/nvidia/tegra210/include/soc/pinmux.h M src/soc/nvidia/tegra210/include/soc/pmc.h M src/soc/nvidia/tegra210/include/soc/power.h M src/soc/nvidia/tegra210/include/soc/romstage.h M src/soc/nvidia/tegra210/include/soc/sdram.h M src/soc/nvidia/tegra210/include/soc/sdram_configs.h M src/soc/nvidia/tegra210/include/soc/sdram_param.h M src/soc/nvidia/tegra210/include/soc/secure_boot.h M src/soc/nvidia/tegra210/include/soc/spi.h M src/soc/nvidia/tegra210/include/soc/sysctr.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/nvidia/tegra210/include/soc/verstage.h M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.ld M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/mmu_operations.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/mtc.c M src/soc/nvidia/tegra210/padconfig.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/ram_code.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/nvidia/tegra210/romstage.c M src/soc/nvidia/tegra210/romstage_asm.S M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/sdram_lp0.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/nvidia/tegra210/spi.c M src/soc/nvidia/tegra210/stack.S M src/soc/nvidia/tegra210/stage_entry.S M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/soc_services.h M src/soc/qualcomm/ipq40xx/include/soc/usb.h M src/soc/qualcomm/ipq40xx/include/soc/verstage.h M src/soc/qualcomm/ipq40xx/mbn_header.h M src/soc/qualcomm/ipq40xx/soc.c M src/soc/qualcomm/ipq40xx/usb.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/ipq806x/clock.c M src/soc/qualcomm/ipq806x/include/soc/cdp.h M src/soc/qualcomm/ipq806x/include/soc/ebi2.h M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/soc_services.h M src/soc/qualcomm/ipq806x/include/soc/spi.h M src/soc/qualcomm/ipq806x/include/soc/usb.h M src/soc/qualcomm/ipq806x/mbn_header.h M src/soc/qualcomm/ipq806x/soc.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/qcs405/gpio.c M src/soc/qualcomm/sc7180/gpio.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/rockchip/common/cbmem.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/edp.h M src/soc/rockchip/common/include/soc/gpio.h M src/soc/rockchip/common/include/soc/i2c.h M src/soc/rockchip/common/include/soc/pwm.h M src/soc/rockchip/common/include/soc/rk808.h M src/soc/rockchip/common/include/soc/soc.h M src/soc/rockchip/common/include/soc/spi.h M src/soc/rockchip/common/include/soc/vop.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/rk808.c M src/soc/rockchip/common/spi.c M src/soc/rockchip/common/uart.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/bootblock.c M src/soc/rockchip/rk3288/chip.h M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/crypto.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/include/soc/addressmap.h M src/soc/rockchip/rk3288/include/soc/clock.h M src/soc/rockchip/rk3288/include/soc/display.h M src/soc/rockchip/rk3288/include/soc/grf.h M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/pmu.h M src/soc/rockchip/rk3288/include/soc/sdram.h M src/soc/rockchip/rk3288/include/soc/timer.h M src/soc/rockchip/rk3288/include/soc/tsadc.h M src/soc/rockchip/rk3288/sdram.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bootblock.c M src/soc/rockchip/rk3399/chip.h M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/include/soc/addressmap.h M src/soc/rockchip/rk3399/include/soc/clock.h M src/soc/rockchip/rk3399/include/soc/display.h M src/soc/rockchip/rk3399/include/soc/grf.h M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/mipi.h M src/soc/rockchip/rk3399/include/soc/mmu_operations.h M src/soc/rockchip/rk3399/include/soc/saradc.h M src/soc/rockchip/rk3399/include/soc/sdram.h M src/soc/rockchip/rk3399/include/soc/symbols.h M src/soc/rockchip/rk3399/include/soc/timer.h M src/soc/rockchip/rk3399/include/soc/tsadc.h M src/soc/rockchip/rk3399/include/soc/usb.h M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/sdram.c M src/soc/rockchip/rk3399/soc.c M src/soc/rockchip/rk3399/spi_bitbang.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5250/bootblock.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5250/chip.h M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/clock_init.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5250/dmc_common.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/dp-reg.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/gpio.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5250/include/soc/clk.h M src/soc/samsung/exynos5250/include/soc/cpu.h M src/soc/samsung/exynos5250/include/soc/dmc.h M src/soc/samsung/exynos5250/include/soc/dp-core.h M src/soc/samsung/exynos5250/include/soc/dp.h M src/soc/samsung/exynos5250/include/soc/dsim.h M src/soc/samsung/exynos5250/include/soc/fimd.h M src/soc/samsung/exynos5250/include/soc/gpio.h M src/soc/samsung/exynos5250/include/soc/i2c.h M src/soc/samsung/exynos5250/include/soc/i2s-regs.h M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/periph.h M src/soc/samsung/exynos5250/include/soc/pinmux.h M src/soc/samsung/exynos5250/include/soc/power.h M src/soc/samsung/exynos5250/include/soc/setup.h M src/soc/samsung/exynos5250/include/soc/spi.h M src/soc/samsung/exynos5250/include/soc/sysreg.h M src/soc/samsung/exynos5250/include/soc/tmu.h M src/soc/samsung/exynos5250/include/soc/trustzone.h M src/soc/samsung/exynos5250/include/soc/uart.h M src/soc/samsung/exynos5250/include/soc/usb.h M src/soc/samsung/exynos5250/include/soc/wakeup.h M src/soc/samsung/exynos5250/pinmux.c M src/soc/samsung/exynos5250/power.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5250/tmu.c M src/soc/samsung/exynos5250/trustzone.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5250/usb.c M src/soc/samsung/exynos5250/wakeup.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/bootblock.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/samsung/exynos5420/chip.h M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dmc_common.c M src/soc/samsung/exynos5420/gpio.c M src/soc/samsung/exynos5420/i2c.c M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5420/include/soc/clk.h M src/soc/samsung/exynos5420/include/soc/cpu.h M src/soc/samsung/exynos5420/include/soc/dmc.h M src/soc/samsung/exynos5420/include/soc/dp.h M src/soc/samsung/exynos5420/include/soc/dsim.h M src/soc/samsung/exynos5420/include/soc/fimd.h M src/soc/samsung/exynos5420/include/soc/gpio.h M src/soc/samsung/exynos5420/include/soc/i2c.h M src/soc/samsung/exynos5420/include/soc/i2s-regs.h M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/periph.h M src/soc/samsung/exynos5420/include/soc/pinmux.h M src/soc/samsung/exynos5420/include/soc/power.h M src/soc/samsung/exynos5420/include/soc/setup.h M src/soc/samsung/exynos5420/include/soc/spi.h M src/soc/samsung/exynos5420/include/soc/sysreg.h M src/soc/samsung/exynos5420/include/soc/tmu.h M src/soc/samsung/exynos5420/include/soc/trustzone.h M src/soc/samsung/exynos5420/include/soc/uart.h M src/soc/samsung/exynos5420/include/soc/usb.h M src/soc/samsung/exynos5420/include/soc/wakeup.h M src/soc/samsung/exynos5420/pinmux.c M src/soc/samsung/exynos5420/power.c M src/soc/samsung/exynos5420/smp.c M src/soc/samsung/exynos5420/spi.c M src/soc/samsung/exynos5420/timer.c M src/soc/samsung/exynos5420/tmu.c M src/soc/samsung/exynos5420/trustzone.c M src/soc/samsung/exynos5420/uart.c M src/soc/samsung/exynos5420/usb.c M src/soc/samsung/exynos5420/wakeup.c M src/soc/sifive/fu540/bootblock.c M src/soc/sifive/fu540/cbmem.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/include/soc/addressmap.h M src/soc/sifive/fu540/include/soc/clock.h M src/soc/sifive/fu540/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/otp.h M src/soc/sifive/fu540/include/soc/sdram.h M src/soc/sifive/fu540/include/soc/spi.h M src/soc/sifive/fu540/otp.c M src/soc/sifive/fu540/sdram.c M src/soc/sifive/fu540/spi.c M src/soc/sifive/fu540/spi_internal.h M src/soc/sifive/fu540/uart.c M src/soc/ucb/riscv/cbmem.c 1,461 files changed, 2,830 insertions(+), 18,840 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40058/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/40058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bbe12b2b0ac84ff945b107bc51b11083e178733 Gerrit-Change-Number: 40058 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mainboard/siemens: Use SPDX for GPL-2.0-only files
by Angel Pons (Code Review) 04 Apr '20

04 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40099 ) Change subject: mainboard/siemens: Use SPDX for GPL-2.0-only files ...................................................................... mainboard/siemens: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/bootblock.c M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/romstage.c M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c M src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h M src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 21 files changed, 42 insertions(+), 273 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/40099/1 diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index 3c8d5bd..695aaac 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootblock_common.h> #include <intelblocks/lpc_lib.h> diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index b597480..a13f387 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/acpi.h> DefinitionBlock( diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 716f4e0..1a134a5 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <device/mmio.h> diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index c967063..366a139 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <hwilib.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index eeab878..c2c28791 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 1ee4281..afbeb33 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef _BASEBOARD_VARIANTS_H_ #define _BASEBOARD_VARIANTS_H_ diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c index c90e1e4..99481eb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <baseboard/variants.h> #include <commonlib/helpers.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c index 5efced8..0412900 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 9698c2b..d9a6db0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootstate.h> #include <console/console.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index 4a7255e..aceab33 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index e6aff80..1aa5fb2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootstate.h> #include <console/console.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index 12f8339f..fb1499b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 36c736b..a69677b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/io.h> #include <bootstate.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 8b3e7e2..f23bc3f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c index 641b748..5fe21f6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c index af0bf46..6ebaf5f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/memory.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <baseboard/variants.h> #include <commonlib/helpers.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 39e086a..68e2ca9 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c index 90aade5..5576b56 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <console/console.h> #include <device/device.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 4c696ad..023195f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <bootstate.h> #include <console/console.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c index 38b7c44..53f18ca 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <commonlib/helpers.h> #include <baseboard/variants.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 6ba13fe..aa96d9b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include <arch/io.h> #include <bootstate.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/40099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636 Gerrit-Change-Number: 40099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2020