coreboot-gerrit April 2020

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Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: WIP: update blobs repo submodule
by Martin Kepplinger (Code Review) 06 Aug '23

06 Aug '23

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33197 Change subject: WIP: update blobs repo submodule ...................................................................... WIP: update blobs repo submodule Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33197/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..8147d6b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 8147d6b601050f6fac6f4c5ccfd8cdadbe3507de -- To view, visit https://review.coreboot.org/c/coreboot/+/33197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12fc447ee78d986f93f4c39bac282cb6a9a73814 Gerrit-Change-Number: 33197 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/Makefile.inc: Clean up targets
by Arthur Heymans (Code Review) 04 Aug '23

04 Aug '23

Hello Martin Roth, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36460 to review the following change. Change subject: payloads/external/Makefile.inc: Clean up targets ...................................................................... payloads/external/Makefile.inc: Clean up targets - Combine the short target name with the filename. - All targets depend on top level dotconfig. - Payload targets depend on their payload .config. - Add .PHONY target for the short target names. - Add additional short target names grub, uboot, and memtest. - Remove reversed dependencies of config files on the output. - Set SeaBIOS vgabios target at same level as main SeaBIOS target to prevent rebuilds because of the vbios being included. This fixes an issue with SeaBIOS and Filo rebuilding every time. Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/Makefile.inc 1 file changed, 18 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36460/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f6417fd..cdc5552 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -17,14 +17,20 @@ ## ###################################################################### + +SEABIOS_DIR=payloads/external/SeaBIOS/seabios +SEABIOS_OUT=$(SEABIOS_DIR)/out +FILO_DIR=payloads/external/FILO/filo +FILO_OUT=$(FILO_DIR)/build + # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config -PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h +PAYLOAD_CONFIG=$(SEABIOS_DIR)/.config +PAYLOAD_VERSION=$(SEABIOS_OUT)/autoversion.h endif ifeq ($(CONFIG_PAYLOAD_FILO),y) -PAYLOAD_CONFIG=payloads/external/FILO/filo/.config -PAYLOAD_VERSION=payloads/external/FILO/filo/build/version.h +PAYLOAD_CONFIG=$(FILO_DIR)/.config +PAYLOAD_VERSION=$(FILO_OUT)/version.h endif ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y) PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config @@ -75,10 +81,12 @@ etc/grub.cfg-type := raw etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUNTIME_CONFIG_FILE)) +.PHONY: seabios depthcharge grub2 grub tint memtest u-boot uboot ipxe + # SeaBIOS SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) -payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) +$(SEABIOS_OUT)/vgabios.bin $(SEABIOS_OUT)/bios.bin.elf seabios: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/SeaBIOS \ HOSTCC="$(HOSTCC)" \ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \ @@ -104,10 +112,6 @@ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) -payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios -payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf -payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf - # add a SeaBIOS bootorder file ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),) cbfs-files-y += bootorder @@ -117,7 +121,7 @@ # Depthcharge -payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) +payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/depthcharge \ BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ @@ -153,7 +157,7 @@ # FILO -filo: +$(FILO_OUT)/filo.elf filo: $(DOTCONFIG) $(PAYLOAD_CONFIG) $(MAKE) -C payloads/external/FILO \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ @@ -161,13 +165,9 @@ CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) -payloads/external/FILO/filo/build/filo.elf: filo -payloads/external/FILO/filo/.config: filo -payloads/external/FILO/filo/build/version.h: filo - # Grub -grub2: $(obj)/config.h +payloads/external/GRUB2/grub2/build/default_payload.elf grub2 grub: $(DOTCONFIG) $(MAKE) -C payloads/external/GRUB2 \ HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" \ @@ -179,11 +179,9 @@ CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \ CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES) -payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 - # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot uboot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) @@ -211,7 +209,7 @@ SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) endif -payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) +payloads/external/Memtest86Plus/memtest86plus/memtest memtest: $(DOTCONFIG) $(MAKE) -C payloads/external/Memtest86Plus all \ CC="$(CC_x86_32)" \ LD="$(LD_x86_32)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c4cce46461ed15212a86dc01b703f818aba23 Gerrit-Change-Number: 36460 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable
by Name of user not set (Code Review) 03 Aug '23

03 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38495 ) Change subject: vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ...................................................................... vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable FinalRxEnCycle[ByteLane] does not get set in mtthrcSeedTrain.c if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && \ ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) evaluates FALSE. According to Coverity, this could result in cases where RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane] is used with an uninitialized value. Move the FinalRxEnCycle[ByteLane] initial assignment up a line so it gets initialized regardless. Tested on Lenovo G505s. Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Signed-off-by: Joe Moore <awokd(a)danwin1210.me> Found-by: Coverity CID 1370599 --- M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38495/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c index 991667b..d21c246 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -504,8 +504,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c index 1446f3e..7ea7c56 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c @@ -505,8 +505,8 @@ for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { if (RxEnDlyTargetFound[ByteLane] == FALSE) { MemClkCycle = (UINT8) (FailTestRxEnDly[ByteLane] >> 5); + FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane])) { - FinalRxEnCycle[ByteLane] = PassTestRxEnDly[ByteLane] - 0x10; if (((UINT16) FinalRxEnCycle[ByteLane] >= NBPtr->MinRxEnSeedGross) && ((UINT16) FinalRxEnCycle[ByteLane] <= NBPtr->MaxRxEnSeedTotal)) { // Since FailTestRxEnDly, we can set FinalRxEnCycle MemTRdPosRxEnSeedSetDly3 (TechPtr, (UINT16) FinalRxEnCycle[ByteLane], ByteLane); -- To view, visit https://review.coreboot.org/c/coreboot/+/38495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d3580c8915ba31e87059851fec2ae4b8b0e1da Gerrit-Change-Number: 38495 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/pcengines/apu2: describe serial ports in ACPI
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32989 Change subject: mb/pcengines/apu2: describe serial ports in ACPI ...................................................................... mb/pcengines/apu2: describe serial ports in ACPI FreeBSD users had to manually configure serial ports on their installations. Defining serial ports in ACPI save that effort. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 --- A src/mainboard/pcengines/apu2/acpi/superio.asl M src/mainboard/pcengines/apu2/dsdt.asl 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32989/1 diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 index 0000000..c61e3d7 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 PC Engines Gmbh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.LIBR) { + + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x02F8, 0x2F8, 0x08, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) + } +} \ No newline at end of file diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl index 3bf0ed6..409f03d 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -81,5 +81,8 @@ /* Define the System Indicators for the platform */ #include "acpi/si.asl" + + /* Super IO devices (COM ports) */ + #include "acpi/superio.asl" } /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de4172a1884abbe9d625060a9045c9d71469e27 Gerrit-Change-Number: 32989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

6 12

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 02 Aug '23

02 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/google: Add ALIGNED flag to known sections that need alignment
by Hung-Te Lin (Code Review) 14 Jun '23

14 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37263 ) Change subject: mb/google: Add ALIGNED flag to known sections that need alignment ...................................................................... mb/google: Add ALIGNED flag to known sections that need alignment Update sections in chromeos.fmd that need 4k alignment: - RW_ELOG: By src/driver/elog/elog.c - RW_NVRAM: By src/security/vboot/vbnv_flash.c - {RO,RW}_DDR_TRAINING: By soc/qualcomm/common/qclib.c and mainboard/kukui/romstage.c Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/dragonegg/chromeos.fmd M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/foster/chromeos.fmd M src/mainboard/google/gale/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/gru/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/mistral/chromeos.fmd M src/mainboard/google/nyan/chromeos.fmd M src/mainboard/google/nyan_big/chromeos.fmd M src/mainboard/google/nyan_blaze/chromeos.fmd M src/mainboard/google/oak/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/smaug/chromeos.fmd M src/mainboard/google/storm/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/trogdor/chromeos.fmd M src/mainboard/google/veyron/chromeos.fmd M src/mainboard/google/veyron_mickey/chromeos.fmd M src/mainboard/google/veyron_rialto/chromeos.fmd 39 files changed, 70 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37263/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99..109f61b 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 7bdeb17..a0bf5f2 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 6e9170e..da90787 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -25,13 +25,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd index f9a531c..5f47ba7 100644 --- a/src/mainboard/google/foster/chromeos.fmd +++ b/src/mainboard/google/foster/chromeos.fmd @@ -17,12 +17,12 @@ RW_SHARED@0x378000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x37c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x37c000 0x4000 RW_SECTION_B@0x380000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 RW_FWID_B@0x77f00 0x100 } RW_VPD(PRESERVE)@0x3f8000 0x4000 - RW_NVRAM(PRESERVE)@0x3fc000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3fc000 0x4000 } diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/gale/chromeos.fmd +++ b/src/mainboard/google/gale/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 9ba1bf7..0f516e2 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -15,13 +15,13 @@ RW_FWID_B@0x3effc0 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG(PRESERVE)@0x7f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x7f0000 0x4000 RW_SHARED@0x7f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x7f8000 0x2000 - RW_NVRAM(PRESERVE)@0x7fa000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x7fa000 0x6000 SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index 032f472..cada219 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,11 +20,11 @@ FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG(PRESERVE)@0x5d8000 0x1000 + RW_ELOG(PRESERVE,ALIGNED)@0x5d8000 0x1000 RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 } - RW_NVRAM(PRESERVE)@0x5f0000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0x5f0000 0x10000 RW_LEGACY(CBFS)@0x600000 0x200000 } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f..bbc666a 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } # RW_LEGACY needs to be minimum of 1MB RW_LEGACY(CBFS)@0x700000 0x100000 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 8368b0a..9e649d7 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -23,13 +23,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index d7d0a88..0888262 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -14,14 +14,14 @@ FW_MAIN_B(CBFS)@0x10000 0x20DFC0 RW_FWID_B@0x21DFC0 0x40 } - RW_ELOG(PRESERVE)@0x45D000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x45D000 0x4000 RW_SHARED@0x461000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x465000 0x2000 - RW_NVRAM(PRESERVE)@0x467000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 SMMSTORE(PRESERVE)@0x480000 0x20000 RW_LEGACY(CBFS)@0x4a0000 0x760000 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 098ce49..c75233e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select RTC + select FMD_GENPARSER select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854..9456393 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -28,9 +28,9 @@ } RW_MISC 36K { RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + RW_NVRAM(PRESERVE,ALIGNED) 8K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K # Only ELOG_SIZE needed. } RW_SECTION_B 1500K { VBLOCK_B 8K diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 3841445..cf7f76d 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666..d2d92e6 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -23,13 +23,13 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 128K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan/chromeos.fmd +++ b/src/mainboard/google/nyan/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_big/chromeos.fmd +++ b/src/mainboard/google/nyan_big/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.fmd +++ b/src/mainboard/google/nyan_blaze/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/oak/chromeos.fmd +++ b/src/mainboard/google/oak/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..28c1a5f 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -19,13 +19,13 @@ RW_VAR_MRC_CACHE@0x20000 0x1000 } } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 6752888..625a30e 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 87eb4e7..72d8df1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -17,13 +17,13 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 65a915a..b63149f4 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -26,13 +26,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x1800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd index 4b1ba19..cb5ec8e 100644 --- a/src/mainboard/google/smaug/chromeos.fmd +++ b/src/mainboard/google/smaug/chromeos.fmd @@ -21,7 +21,7 @@ } RW_SHARED@0xf00000 0x4000 SHARED_DATA@0xf04000 0x4000 - RW_ELOG(PRESERVE)@0xf08000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0xf08000 0x4000 RW_VPD(PRESERVE)@0xf0c000 0x8000 - RW_NVRAM(PRESERVE)@0xf20000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0xf20000 0x10000 } diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/storm/chromeos.fmd +++ b/src/mainboard/google/storm/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51..27ff291 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -23,16 +23,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/veyron/chromeos.fmd +++ b/src/mainboard/google/veyron/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd index 76ab2c3..da8bbc5 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.fmd +++ b/src/mainboard/google/veyron_mickey/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.fmd +++ b/src/mainboard/google/veyron_rialto/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Gerrit-Change-Number: 37263 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in vboot[master]: [Debug] Disable Wimplicit-fallthrough
by Selma Bensaid (Code Review) 10 Jun '23

10 Jun '23

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/vboot/+/38910 to review the following change. Change subject: [Debug] Disable Wimplicit-fallthrough ...................................................................... [Debug] Disable Wimplicit-fallthrough Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/10/38910/1 diff --git a/Makefile b/Makefile index 0539e8d..62c0307 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ -Wundef -Wmissing-prototypes -Wno-trigraphs -Wredundant-decls -Wshadow \ -Wwrite-strings -Wstrict-aliasing -Wdate-time -Wno-unknown-warning \ -Wno-address-of-packed-member -ffunction-sections -fdata-sections \ - -Wimplicit-fallthrough ${DEBUG_FLAGS} + ${DEBUG_FLAGS} # Note: FIRMWARE_ARCH is defined by the Chromium OS ebuild. ifeq (${FIRMWARE_ARCH},arm) -- To view, visit https://review.coreboot.org/c/vboot/+/38910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f Gerrit-Change-Number: 38910 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build
by Pablo Moyano (Code Review) 10 Jun '23

10 Jun '23

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34105 ) Change subject: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build ...................................................................... payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build At some point between Grub 2.02 and 2.04, something was added and it refuses to build without it. Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Signed-off-by: Pablo <42.pablo.ms(a)gmail.com> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34105/1 diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c4066..b036aeb 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Gerrit-Change-Number: 34105 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-MessageType: newchange

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