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Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 03 Aug '23

03 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/google: Add ALIGNED flag to known sections that need alignment
by Hung-Te Lin (Code Review) 14 Jun '23

14 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37263 ) Change subject: mb/google: Add ALIGNED flag to known sections that need alignment ...................................................................... mb/google: Add ALIGNED flag to known sections that need alignment Update sections in chromeos.fmd that need 4k alignment: - RW_ELOG: By src/driver/elog/elog.c - RW_NVRAM: By src/security/vboot/vbnv_flash.c - {RO,RW}_DDR_TRAINING: By soc/qualcomm/common/qclib.c and mainboard/kukui/romstage.c Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/dragonegg/chromeos.fmd M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/foster/chromeos.fmd M src/mainboard/google/gale/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/gru/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/mistral/chromeos.fmd M src/mainboard/google/nyan/chromeos.fmd M src/mainboard/google/nyan_big/chromeos.fmd M src/mainboard/google/nyan_blaze/chromeos.fmd M src/mainboard/google/oak/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/smaug/chromeos.fmd M src/mainboard/google/storm/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/trogdor/chromeos.fmd M src/mainboard/google/veyron/chromeos.fmd M src/mainboard/google/veyron_mickey/chromeos.fmd M src/mainboard/google/veyron_rialto/chromeos.fmd 39 files changed, 70 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37263/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99..109f61b 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 7bdeb17..a0bf5f2 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 6e9170e..da90787 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -25,13 +25,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd index f9a531c..5f47ba7 100644 --- a/src/mainboard/google/foster/chromeos.fmd +++ b/src/mainboard/google/foster/chromeos.fmd @@ -17,12 +17,12 @@ RW_SHARED@0x378000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x37c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x37c000 0x4000 RW_SECTION_B@0x380000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 RW_FWID_B@0x77f00 0x100 } RW_VPD(PRESERVE)@0x3f8000 0x4000 - RW_NVRAM(PRESERVE)@0x3fc000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3fc000 0x4000 } diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/gale/chromeos.fmd +++ b/src/mainboard/google/gale/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 9ba1bf7..0f516e2 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -15,13 +15,13 @@ RW_FWID_B@0x3effc0 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG(PRESERVE)@0x7f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x7f0000 0x4000 RW_SHARED@0x7f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x7f8000 0x2000 - RW_NVRAM(PRESERVE)@0x7fa000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x7fa000 0x6000 SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index 032f472..cada219 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,11 +20,11 @@ FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG(PRESERVE)@0x5d8000 0x1000 + RW_ELOG(PRESERVE,ALIGNED)@0x5d8000 0x1000 RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 } - RW_NVRAM(PRESERVE)@0x5f0000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0x5f0000 0x10000 RW_LEGACY(CBFS)@0x600000 0x200000 } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f..bbc666a 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } # RW_LEGACY needs to be minimum of 1MB RW_LEGACY(CBFS)@0x700000 0x100000 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 8368b0a..9e649d7 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -23,13 +23,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index d7d0a88..0888262 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -14,14 +14,14 @@ FW_MAIN_B(CBFS)@0x10000 0x20DFC0 RW_FWID_B@0x21DFC0 0x40 } - RW_ELOG(PRESERVE)@0x45D000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x45D000 0x4000 RW_SHARED@0x461000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x465000 0x2000 - RW_NVRAM(PRESERVE)@0x467000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 SMMSTORE(PRESERVE)@0x480000 0x20000 RW_LEGACY(CBFS)@0x4a0000 0x760000 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 098ce49..c75233e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select RTC + select FMD_GENPARSER select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854..9456393 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -28,9 +28,9 @@ } RW_MISC 36K { RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + RW_NVRAM(PRESERVE,ALIGNED) 8K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K # Only ELOG_SIZE needed. } RW_SECTION_B 1500K { VBLOCK_B 8K diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 3841445..cf7f76d 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666..d2d92e6 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -23,13 +23,13 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 128K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan/chromeos.fmd +++ b/src/mainboard/google/nyan/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_big/chromeos.fmd +++ b/src/mainboard/google/nyan_big/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.fmd +++ b/src/mainboard/google/nyan_blaze/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/oak/chromeos.fmd +++ b/src/mainboard/google/oak/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..28c1a5f 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -19,13 +19,13 @@ RW_VAR_MRC_CACHE@0x20000 0x1000 } } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 6752888..625a30e 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 87eb4e7..72d8df1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -17,13 +17,13 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 65a915a..b63149f4 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -26,13 +26,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x1800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd index 4b1ba19..cb5ec8e 100644 --- a/src/mainboard/google/smaug/chromeos.fmd +++ b/src/mainboard/google/smaug/chromeos.fmd @@ -21,7 +21,7 @@ } RW_SHARED@0xf00000 0x4000 SHARED_DATA@0xf04000 0x4000 - RW_ELOG(PRESERVE)@0xf08000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0xf08000 0x4000 RW_VPD(PRESERVE)@0xf0c000 0x8000 - RW_NVRAM(PRESERVE)@0xf20000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0xf20000 0x10000 } diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/storm/chromeos.fmd +++ b/src/mainboard/google/storm/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51..27ff291 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -23,16 +23,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/veyron/chromeos.fmd +++ b/src/mainboard/google/veyron/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd index 76ab2c3..da8bbc5 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.fmd +++ b/src/mainboard/google/veyron_mickey/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.fmd +++ b/src/mainboard/google/veyron_rialto/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Gerrit-Change-Number: 37263 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in vboot[master]: [Debug] Disable Wimplicit-fallthrough
by Selma Bensaid (Code Review) 10 Jun '23

10 Jun '23

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/vboot/+/38910 to review the following change. Change subject: [Debug] Disable Wimplicit-fallthrough ...................................................................... [Debug] Disable Wimplicit-fallthrough Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/10/38910/1 diff --git a/Makefile b/Makefile index 0539e8d..62c0307 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ -Wundef -Wmissing-prototypes -Wno-trigraphs -Wredundant-decls -Wshadow \ -Wwrite-strings -Wstrict-aliasing -Wdate-time -Wno-unknown-warning \ -Wno-address-of-packed-member -ffunction-sections -fdata-sections \ - -Wimplicit-fallthrough ${DEBUG_FLAGS} + ${DEBUG_FLAGS} # Note: FIRMWARE_ARCH is defined by the Chromium OS ebuild. ifeq (${FIRMWARE_ARCH},arm) -- To view, visit https://review.coreboot.org/c/vboot/+/38910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f Gerrit-Change-Number: 38910 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build
by Pablo Moyano (Code Review) 10 Jun '23

10 Jun '23

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34105 ) Change subject: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build ...................................................................... payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build At some point between Grub 2.02 and 2.04, something was added and it refuses to build without it. Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Signed-off-by: Pablo <42.pablo.ms(a)gmail.com> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34105/1 diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c4066..b036aeb 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Gerrit-Change-Number: 34105 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/intel/dg41wv: Inherit the subsystemid
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30470 Change subject: mb/intel/dg41wv: Inherit the subsystemid ...................................................................... mb/intel/dg41wv: Inherit the subsystemid Don't reprogram the same subsystemid for each PCI device. Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/devicetree.cb 1 file changed, 23 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30470/1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..da91ea2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -24,14 +24,10 @@ end end device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x8086 0x5756 - end + subsystemid 0x8086 0x5756 inherit + device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG - device pci 2.0 on # Integrated graphics controller - subsystemid 0x8086 0x5756 - end + device pci 2.0 on end # Integrated graphics controller chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -66,39 +62,24 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" - device pci 1b.0 on # Audio - subsystemid 0x8086 0x5756 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on end end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - subsystemid 0x8086 0x5756 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.1 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.2 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.3 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.7 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio Controller - device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - subsystemid 0x8086 0x5756 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy # global @@ -155,12 +136,9 @@ end end device pci 1f.1 off end # PATA/IDE - device pci 1f.2 on # SATA - subsystemid 0x8086 0x5756 - end - device pci 1f.3 on # SMbus - subsystemid 0x8086 0x5756 - chip drivers/i2c/ck505 + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -173,7 +151,6 @@ 0x06, 0x00, 0xea }" device i2c 69 on end end - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Gerrit-Change-Number: 30470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: force --divide for iPXE default build
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35820 ) Change subject: force --divide for iPXE default build ...................................................................... force --divide for iPXE default build Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35820/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa..7005016 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -72,7 +72,7 @@ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom WORKAROUND_ASFLAGS="--divide" endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) -- To view, visit https://review.coreboot.org/c/coreboot/+/35820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Gerrit-Change-Number: 35820 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37674 ) Change subject: [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries ...................................................................... [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries Change-Id: Ia1174e2df7a6b0a634ea6f784abae65137ffc8f7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A util/fsp-defaults/.gitignore A util/fsp-defaults/Makefile A util/fsp-defaults/fspdef.awk A util/fsp-defaults/fspdef.h A util/fsp-defaults/main.c 5 files changed, 213 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37674/1 diff --git a/util/fsp-defaults/.gitignore b/util/fsp-defaults/.gitignore new file mode 100644 index 0000000..1f5666f --- /dev/null +++ b/util/fsp-defaults/.gitignore @@ -0,0 +1,5 @@ +.fsp_inc +.udk_base +fspdef +fspm.c +fsps.c diff --git a/util/fsp-defaults/Makefile b/util/fsp-defaults/Makefile new file mode 100644 index 0000000..8adc0a9 --- /dev/null +++ b/util/fsp-defaults/Makefile @@ -0,0 +1,30 @@ +ifeq ($(UDK_BASE),) +$(warning Need to specify UDK_BASE=) +endif +$(shell if [ "$(UDK_BASE)" != "$$(cat .udk_base 2>/dev/null)" ]; then echo "$(UDK_BASE)" >.udk_base; fi) + +ifeq ($(FSP_INC),) +$(warning Need to specify FSP_INC=) +endif +$(shell if [ "$(FSP_INC)" != "$$(cat .fsp_inc 2>/dev/null)" ]; then echo "$(FSP_INC)" >.fsp_inc; fi) + +_CPPFLAGS = \ + -I../../src/commonlib/include/ \ + -I$(UDK_BASE)/MdePkg/Include/Ia32/ \ + -I$(UDK_BASE)/MdePkg/Include/ \ + -I$(UDK_BASE)/IntelFsp2Pkg/Include/ \ + -I$(FSP_INC)/ \ + +fspdef: main.c fspm.c fsps.c .fsp_inc .udk_base + gcc -m32 $(_CPPFLAGS) -o $@ $< fspm.c fsps.c + +fspm.c: $(FSP_INC)/FspmUpd.h fspdef.awk .fsp_inc .udk_base + gcc $(_CPPFLAGS) -E $< | gawk -f fspdef.awk > $@ + +fsps.c: $(FSP_INC)/FspsUpd.h fspdef.awk .fsp_inc .udk_base + gcc $(_CPPFLAGS) -E $< | gawk -f fspdef.awk > $@ + +clean: + rm -f fspm.c fsps.c fspdef + +.PHONY: clean diff --git a/util/fsp-defaults/fspdef.awk b/util/fsp-defaults/fspdef.awk new file mode 100644 index 0000000..07a9756 --- /dev/null +++ b/util/fsp-defaults/fspdef.awk @@ -0,0 +1,97 @@ +function process(field, width) { + printf("\tif (config->%s)\n", field); + printf("\t\tprintf(\"\\t\\t/* 0x%%04x */ .%s = 0x%%\"PRIx%s\",\\n\", offset + offsetof(typeof(*config), %s), config->%s);\n", + field, width, field, field); +} + +function process_array(field, width) { + printf("\tfor (i = 0; i < ARRAY_SIZE(config->%s); ++i) {\n", field); + printf("\t\tif (config->%s[i])\n", field); + printf("\t\t\tbreak;\n"); + printf("\t}\n"); + printf("\tif (i < ARRAY_SIZE(config->%s)) {\n", field); + printf("\t\tprintf(\"\\t\\t/* 0x%%04x */ .%s = {\", offset + offsetof(typeof(*config), %s));\n", + field, field); + printf("\t\tfor (i = 0; i < ARRAY_SIZE(config->%s); ++i) {\n", field); + printf("\t\t\tif (i % 8 == 0)\n"); + printf("\t\t\t\tprintf(\"\\n\\t\\t\\t\");\n"); + printf("\t\t\tprintf(\"0x%%\"PRIx%s\",\", config->%s[i]);\n", width, field); + printf("\t\t\tif ((i + 1) % 8 != 0 && i != ARRAY_SIZE(config->%s) - 1)\n", field); + printf("\t\t\t\tprintf(\" \");\n"); + printf("\t\t}\n"); + printf("\t\tprintf(\"\\n\\t\\t},\\n\");\n"); + printf("\t}\n"); +} + +function process_struct(cname, tname) { + printf("void process_%s(const size_t offset, const %s *const config)\n{\n", cname, tname); + printf("\tunsigned int i;\n"); + printf("\tprintf(\"\\tstatic const %s default_%s = {\\n\");\n\n", tname, cname); + for (field in fields) { + if (field in arrays) + process_array(fields[field], widths[field]); + else + process(fields[field], widths[field]); + printf("\n"); + } + printf("\tprintf(\"\\t};\\n\\n\");\n"); + printf("}\n\n"); +} + +BEGIN { + gather = 0; + + printf("#include <stdio.h>\n"); + printf("#include <stddef.h>\n"); + printf("#include <inttypes.h>\n"); + printf("#include <commonlib/helpers.h>\n"); + printf("#include <FspmUpd.h>\n"); + printf("#include <FspsUpd.h>\n\n"); + printf("#include \"fspdef.h\"\n\n"); +} + +/typedef struct {/ { + gather = 1; + field = 0; +} + +# match single identifiers +match($0, /(UINT|CHAR)([0-9]+) ([0-9a-zA-Z]+);/, matches) { + if (gather) { + fields[field] = matches[3]; + widths[field] = matches[2]; + ++field; + } +} + +# match array identifiers +match($0, /(UINT|CHAR)([0-9]+) ([0-9a-zA-Z]+)\[([0-9]+)\];/, matches) { + if (gather) { + fields[field] = matches[3]; + widths[field] = matches[2]; + arrays[field] = "dummy"; + ++field; + } +} + +/} FSP_M_CONFIG;/ { + process_struct("fsp_m_config", "FSP_M_CONFIG"); +} + +/} FSP_M_TEST_CONFIG;/ { + process_struct("fsp_m_tconfig", "FSP_M_TEST_CONFIG"); +} + +/} FSP_S_CONFIG;/ { + process_struct("fsp_s_config", "FSP_S_CONFIG"); +} + +/} FSP_S_TEST_CONFIG;/ { + process_struct("fsp_s_tconfig", "FSP_S_TEST_CONFIG"); +} + +/} .*;/ { + gather = 0; + delete fields; + delete arrays; +} diff --git a/util/fsp-defaults/fspdef.h b/util/fsp-defaults/fspdef.h new file mode 100644 index 0000000..72d99ad --- /dev/null +++ b/util/fsp-defaults/fspdef.h @@ -0,0 +1,12 @@ +#ifndef UTIL_FSP_DEFAULTS_FSPDEF_H +#define UTIL_FSP_DEFAULTS_FSPDEF_H + +#include <FspmUpd.h> +#include <FspsUpd.h> + +void process_fsp_m_config(size_t offset, const FSP_M_CONFIG *); +void process_fsp_m_tconfig(size_t offset, const FSP_M_TEST_CONFIG *); +void process_fsp_s_config(size_t offset, const FSP_S_CONFIG *); +void process_fsp_s_tconfig(size_t offset, const FSP_S_TEST_CONFIG *); + +#endif /* UTIL_FSP_DEFAULTS_FSPDEF_H */ diff --git a/util/fsp-defaults/main.c b/util/fsp-defaults/main.c new file mode 100644 index 0000000..eb4d2a9 --- /dev/null +++ b/util/fsp-defaults/main.c @@ -0,0 +1,69 @@ +#include <stdio.h> +#include <stddef.h> +#include <stdint.h> +#include <fcntl.h> +#include <unistd.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <FspUpd.h> +#include <FspmUpd.h> +#include <FspsUpd.h> + +#include "fspdef.h" + +int main(const int argc, const char *const argv[]) +{ + if (argc != 2) { + fprintf(stderr, "Usage: %s <path-to-FSP.fd>\n", argv[0]); + return 1; + } + + const int fd = open(argv[1], O_RDONLY); + if (fd == -1) { + perror("Failed to open FSP.fd"); + return 2; + } + + struct stat stat; + if (fstat(fd, &stat)) { + perror("Failed to stat FSP.fd"); + return 3; + } + + const void *const fsp = mmap(NULL, stat.st_size, PROT_READ, MAP_SHARED, fd, 0); + close(fd); + if (fsp == MAP_FAILED) { + perror("Failed to map FSP.fd"); + return 3; + } + + const uint8_t *it, *const end = (const uint8_t *)fsp + stat.st_size; + for (it = fsp; it < end; ++it) { + const uint64_t *const sig = (const uint64_t *)it; + const FSPM_UPD *fspm; + const FSPS_UPD *fsps; + switch (*sig) { + case FSPM_UPD_SIGNATURE: + fspm = (const FSPM_UPD *)sig; + process_fsp_m_config( + offsetof(FSPM_UPD, FspmConfig), + &fspm->FspmConfig); + process_fsp_m_tconfig( + offsetof(FSPM_UPD, FspmTestConfig), + &fspm->FspmTestConfig); + break; + case FSPS_UPD_SIGNATURE: + fsps = (const FSPS_UPD *)sig; + process_fsp_s_config( + offsetof(FSPS_UPD, FspsConfig), + &fsps->FspsConfig); + process_fsp_s_tconfig( + offsetof(FSPS_UPD, FspsTestConfig), + &fsps->FspsTestConfig); + break; + } + } + + munmap((void *)fsp, stat.st_size); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1174e2df7a6b0a634ea6f784abae65137ffc8f7 Gerrit-Change-Number: 37674 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/...
by Kevin Cody-Little (Code Review) 10 Jun '23

10 Jun '23

Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38207 ) Change subject: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. ...................................................................... Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Signed-off-by: Kevin Cody <kcodyjr(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/soc/intel/skylake/Kconfig 13 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38207/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..165c440 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -16,6 +16,7 @@ select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 3261661..2dabb2b 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b38..34a0368 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index cafb855..9abf2bc 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -26,6 +26,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SPD_READ_BY_WORD + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index bc0c67b..e8f3e3e 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 5a621bb..b2f28fa 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index afc510f..cd5f8a2 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d7706d1..6bad7c8 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 315104e..f985cde 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -30,6 +30,7 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a..cfef895 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -11,6 +11,7 @@ select SPD_READ_BY_WORD select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_PURISM_BASEBOARD_LIBREM_SKL diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 903d7ba..4aa6669 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -16,6 +16,7 @@ select HAVE_ACPI_TABLES select ADD_FSP_BINARIES select FSP_USE_REPO + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 5a99f7a..27b4e44 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d90fb6b..ab944b6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -57,7 +57,6 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/38207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Gerrit-Change-Number: 38207 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/car/bootblock: Add post-console init callbacks
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36711 ) Change subject: soc/intel/car/bootblock: Add post-console init callbacks ...................................................................... soc/intel/car/bootblock: Add post-console init callbacks Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/bootblock.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36711/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5..063b444 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -35,8 +35,16 @@ bootblock_early_cpu_init(); } +void __weak bootblock_northbridge_init(void) { } +void __weak bootblock_southbridge_init(void) { } +void __weak bootblock_cpu_init(void) { } + void bootblock_soc_init(void) { /* Halt if there was a built in self test failure */ report_bist_failure(saved_bist); + /* Post console init */ + bootblock_northbridge_init(); + bootblock_southbridge_init(); + bootblock_cpu_init(); } diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h index 5adfd87..af9e45e 100644 --- a/src/cpu/intel/car/bootblock.h +++ b/src/cpu/intel/car/bootblock.h @@ -18,4 +18,8 @@ void bootblock_early_northbridge_init(void); void bootblock_early_southbridge_init(void); +void bootblock_northbridge_init(void); +void bootblock_southbridge_init(void); +void bootblock_cpu_init(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Gerrit-Change-Number: 36711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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