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Change in coreboot[master]: Documentation: Add MacBook internal flashing tutorial
by Evgeny Zinoviev (Code Review) 07 Aug '23

07 Aug '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38770 ) Change subject: Documentation: Add MacBook internal flashing tutorial ...................................................................... Documentation: Add MacBook internal flashing tutorial Change-Id: I2650d5d60db7a29a1567e44e89b785def9342df2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/flash_tutorial/int_flashrom.md A Documentation/flash_tutorial/int_macbook.md 2 files changed, 294 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38770/1 diff --git a/Documentation/flash_tutorial/int_flashrom.md b/Documentation/flash_tutorial/int_flashrom.md index 28b534b..0ca59af 100644 --- a/Documentation/flash_tutorial/int_flashrom.md +++ b/Documentation/flash_tutorial/int_flashrom.md @@ -16,4 +16,9 @@ flashrom -p internal -w coreboot.rom ``` +## Vendor-specific + +- [Lenovo ThinkPad xx30 series](../lenovo/ivb_internal_flashing) +- [Apple MacBook](int_macbook.md) - 2011-2012 models + [flashrom's wiki]: https://www.flashrom.org/Flashrom diff --git a/Documentation/flash_tutorial/int_macbook.md b/Documentation/flash_tutorial/int_macbook.md new file mode 100644 index 0000000..b0638ca --- /dev/null +++ b/Documentation/flash_tutorial/int_macbook.md @@ -0,0 +1,289 @@ +# Apple MacBook internal flashing + +This page describes a method of flashing coreboot on 2011-2012 models of +Apple MacBooks. Whether it can be used on other generations of MacBooks +is unknown. + +This is a very delicate prodecure. Be very careful, check everything +twice, especially the numbers. A single mistake may brick your machine +and you'll have to flash the backup externally. Given this fact, you +should have an external means of flashing, just in case. + +It was tested and confirmed to work on following models: +- MacBook Air 5,2 +- MacBook Pro 8,1 +- MacBook Pro 10,1 + +MacBook Air 4,2 should work too, but it's not tested. + +## Introduction + +Apple's "Think Different" slogan fits perfectly with their approach to +firmware security. Besides the fact that they do not use SMM_BWP to +protect SPI flash from being writable from userspace, they do not even +protect Flash Descriptor (`fd`) and Management Engine (`me`) regions. + +The Intel Flash Descriptor is a data structure of fixed size (4KB) +stored on the flash chip (resides in `0x0000-0x0fff`), that contains +various information such as space allocated for each region on the +flash, access permissions, some chipset configuration and more. In +particular, it contains access permissions for `fd` and `me` regions. +Normally they should be read-only in production, but Apple, for whatever +reasons, keeps them read-write. + +Instead, they decided to use SPI Protected Range Registers (PR0-PR4) to +set protection over `fd`, but here they failed again. Due to a bug in +their firmware, `0x0000-0x0fff` is not write-protected after cold boot +and becomes read-only only after resuming from S3. You can dump PRx +protections by running `flashrom -p internal`. + +This is what you should see after a cold boot (if so, then you can use +this guide): +``` +PR0: Warning: 0x00190000-0x0066ffff is read-only. +PR1: Warning: 0x00692000-0x01ffffff is read-only. +``` + +And this is after resuming from S3: +``` +PR0: Warning: 0x00000000-0x00000fff is read-only. +PR1: Warning: 0x00190000-0x0066ffff is read-only. +PR2: Warning: 0x00692000-0x01ffffff is read-only. +``` + +So, after cold boot flash descriptor is not protected neither by PRx +registers nor by access permissions bits on the flash descriptor itself. +Under certain circumstances, **writable flash descriptor allows to flash +whole SPI flash** by using a couple of tricks. + +The idea is that we can shrink ME firmware with me_cleaner, flash small +coreboot image on the freed space and move reset vector there. Then +power off, boot coreboot and flash full image, as there will be no more +PRx set. + +## Stage 1. Flashing temporary BIOS + +#### Preparations + +Dump your ROM: +``` +flashrom -p internal -r orig.bin +``` + +Please save this backup to an external drive. You may need it in case of +failure. + +Extract flash layout: +``` +ifdtool -f orig_layout.txt orig.bin +cat orig_layout.txt +``` + +You should see something like or exactly this: +``` +00000000:00000fff fd +00190000:007fffff bios +00001000:0018ffff me +``` +If you compare these regions with what's protected by PR0 and PR1, +you'll notice that `fd` and `me` regions are fully writable and only +`bios` is protected. Writable ME region gives us around 1.5 MB which we +can use for our goals. + +Extract flash regions from the dump into separate files: +``` +ifdtool -x orig.bin +``` + +You can see that 3 new files were created: +``` +ls flash* +flashregion_0_flashdescriptor.bin flashregion_1_bios.bin flashregion_2_intel_me.bin +``` + +The ME firmware is ~1.5 MB in size, but we can truncate it with +me_cleaner: +``` +me_cleaner.py -t -r -O flashregion_2_intel_me_truncated.bin flashregion_2_intel_me.bin +``` + +The truncated firmware should be around 90K: +``` +stat --printf=%s flashregion_2_intel_me_truncated.bin +94208 +``` + +Rename the original `flashregion_2_intel_me.bin` file to not mix them up +in future: +``` +mv flashregion_2_intel_me.bin flashregion_2_intel_me_orig.bin +``` + +Now we need to write a new flash layout. 128K is more than enough for +the "neutered" ME firmware. We can use the rest for new `bios` region, +but 892K is enough: + +``` +00000000:00000fff fd +00001000:00020fff me +00021000:000fffff bios +00100000:007fffff pd +``` + +Note that we must allocate the remaining `0x100000-0x7fffff` for +something to be able to address and flash it in future. Let's just mark +it as `pd` (which stands for "Platform Data") for now. + +Save the new layout to a file `new_layout.txt` and update regions in the +dump: +``` +ifdtool -n new_layout.txt orig.bin +``` + +The updated image will be saved to `orig.bin.new`. Move it to a +separate directory for convenience: +``` +mkdir patched && cd $_ +mv ../orig.bin.new . +``` + +Extract flash regions again, now from the updated image: +``` +fdtool -x orig.bin.new +``` + +By now we have new `flashregion_0_flashdescriptor.bin` file with our +custom layout. Let's also move the patched ME here: +``` +rm flashregion_2_intel_me.bin +mv ../flashregion_2_intel_me_truncated.bin . +``` + +So far, so good. At this point our preparations for the first stage are +finished and we're ready to configure coreboot. + +#### Configuring and flashing coreboot + +Run `make menuconfig` and configure as shown below. Note that you need +to change **ROM chip size**, **CBFS size** and specify paths to modified +`flashregion_0_flashdescriptor.bin` and +`flashregion_2_intel_me_truncated.bin`. + +``` +Mainboard ---> + Mainboard vendor (Apple) + Mainboard model () # Set according to your model + ROM chip size (1024 KB (1 MB)) + (0xd0000) Size of CBFS filesystem in ROM + +Chipset ---> + [*] Add Intel descriptor.bin file + (/path/to/patched/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file + [*] Add Intel ME/TXE firmware + (/path/to/patched/flashregion_2_intel_me_truncated.bin) Path to management engine firmware + [ ] Verify the integrity of the supplied ME/TXE firmware + [ ] Strip down the Intel ME/TXE firmware + Protect flash regions (Unlock flash regions) +``` + +Then you need to decide which payload to use. For now, it's recommended +to use GRUB2. Be sure to include a good config for it that can load variety +of setups. SeaBIOS works too, but currently needs a patch for internal +MacBook's keyboard to work. + +When configuration is done, run `make` to build coreboot. In the end you +should have 1024 KB coreboot ROM at `build/coreboot.rom`. Flashrom won't +accept it, because it's size must match the chip, so we have to make it +8 MB. Just add 7 MB of zeroes: +``` +dd if=/dev/zero of=7M.bin bs=1024 count=7168 +``` +``` +cat build/coreboot.rom 7M.bin > coreboot8.rom +``` + +Now cross your fingers and flash the new **`fd`** (`0x0000-0x0fff`), +**`me`** (`0x1000-0x20fff`) and **`bios`** (`0x21000-0xfffff`) regions +using the layout file: +``` +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i fd -N +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i me -N +flashrom -p internal -w coreboot8.rom -l new_layout.txt -i bios -N +``` + +The first stage is completed. Power off the machine now. Reboot won't +work: new flash descriptor becomes active on cold boot. + +On the next boot, if you're lucky and didn't do any mistake, coreboot +will be loaded from the new `bios` region, and Apple's EFI, that still +resides in `0x190000-0x7fffff`, will be ignored. + +## Stage 2. Flashing full ROM + +Now we can flash whole 8 MB chip, because no PRx are set anymore. Let's +relayout the chip again. + +If you want to continue using truncated ME: +``` +00000000:00000fff fd +00001000:00020fff me +00021000:007fffff bios +``` + +If you want to flash full ME firmware back: +``` +00000000:00000fff fd +00001000:0018ffff me +00190000:007fffff bios +``` + +Save it to `final_layout.txt` and create new flash descriptor again. +``` +mkdir patched2 && cd $_ +cp ../orig.bin . +ifdtool -n final_layout.txt orig.bin +ifdtool -x orig.bin.new +``` + +Go back to coreboot directory and run `make menuconfing`. + +In the **Mainboard** section change **ROM chip size** back to 8 MB and +set **Size of CBFS** according to your needs: now you have plenty of +space. `0x500000` or so should work just fine. + +In the **Chipset** section, update paths to the flash descriptor and ME +firmware files. If you decided to stick to truncated ME, use +`flashregion_2_intel_me_truncated.bin`, otherwise use +`flashregion_2_intel_me_orig.bin`. + +``` +Mainboard ---> + ROM chip size (8192 KB (8 MB)) + (0x500000) Size of CBFS filesystem in ROM + +Chipset ---> + [*] Add Intel descriptor.bin file + + # Use the latest flashdescriptor from the patched2 directory + (/path/to/patched2/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file + + [*] Add Intel ME/TXE firmware + (/path/to/patched/flashregion_2_intel_me_truncated.bin) Path to management engine firmware + [ ] Verify the integrity of the supplied ME/TXE firmware + [ ] Strip down the Intel ME/TXE firmware +``` + +Save the config and `make` it again. Then flash `fd` and `bios` +according to the `final_layout.txt`: +``` +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i fd -N +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i bios -N +``` + +If you changed ME firmware back to original, flash it as well: +``` +flashrom -p internal -w build/coreboot.rom -l final_layout.txt -i me -N +``` + +Stage 2 is completed. Power off (reboot won't work again). On the next +boot, you will have completely corebooted MacBook. -- To view, visit https://review.coreboot.org/c/coreboot/+/38770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2650d5d60db7a29a1567e44e89b785def9342df2 Gerrit-Change-Number: 38770 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: vboot/Kconfig: Handle VBNV RTC offset in code
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Hello Julius Werner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38918 to review the following change. Change subject: vboot/Kconfig: Handle VBNV RTC offset in code ...................................................................... vboot/Kconfig: Handle VBNV RTC offset in code This way, programmers and reviewers don't have to make the calculation over and over in their heads. Change-Id: I928457febd399526fa77108d12b804ca7e53f80b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/security/vboot/Kconfig M src/security/vboot/vbnv_cmos.c M src/vendorcode/google/chromeos/acpi/chromeos.asl 17 files changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38918/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..33ce503 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -212,7 +212,7 @@ vbnv = (struct lb_range *)lb_new_record(header); vbnv->tag = LB_TAG_VBNV; vbnv->size = sizeof(*vbnv); - vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET + 14; + vbnv->range_start = CONFIG_VBOOT_VBNV_OFFSET; vbnv->range_size = VBOOT_VBNV_BLOCK_SIZE; #endif } diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c27b1e..fde47c2 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -38,7 +38,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2c + default 0x3a config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee430d0..a0a7175 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -37,7 +37,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2c + default 0x3a config MAINBOARD_DIR string diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 7d98d89..c538e12 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -107,7 +107,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2A + default 0x38 config CHROMEOS select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index dc288d6..b07601a 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -28,7 +28,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index deb6c8e..0cd4e5c 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -39,7 +39,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x82 + default 0x90 config FMDFILE string diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 5d60565..744c62d 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -37,7 +37,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index d26ad17..342cb35 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -41,7 +41,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 89f84fc..3cf721a 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -40,7 +40,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 6d31be2..304ff84 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -40,7 +40,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config VARIANT_DIR string diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 432c805..0d1b3f5 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -36,7 +36,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x82 + default 0x90 config FMDFILE string diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a94d24e..9feb8da 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -36,7 +36,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index b20255e..4e93da7 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -39,7 +39,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e0f468c..674426d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -56,7 +56,7 @@ config VBOOT_VBNV_OFFSET hex - default 0x2a + default 0x38 config FMDFILE string diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea70e65..c534d7f 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -73,11 +73,11 @@ config VBOOT_VBNV_OFFSET hex - default 0x26 + default 0x34 depends on VBOOT_VBNV_CMOS help CMOS offset for VbNv data. This value must match cmos.layout - in the mainboard directory, minus 14 bytes for the RTC. + in the mainboard directory. config VBOOT_VBNV_CMOS_BACKUP_TO_FLASH bool diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c index 7758ef6..5cb1e96 100644 --- a/src/security/vboot/vbnv_cmos.c +++ b/src/security/vboot/vbnv_cmos.c @@ -62,7 +62,7 @@ int i; for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++) - vbnv_copy[i] = cmos_read(CONFIG_VBOOT_VBNV_OFFSET + 14 + i); + vbnv_copy[i] = cmos_read(CONFIG_VBOOT_VBNV_OFFSET + i); /* Verify contents before attempting a restore from backup storage. */ if (verify_vbnv(vbnv_copy)) @@ -76,7 +76,7 @@ int i; for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++) - cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + 14 + i); + cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + i); } void vbnv_init_cmos(uint8_t *vbnv_copy) diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 4852600..29c04ef 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -76,7 +76,7 @@ Name(VNBV, Package() { // See src/vendorcode/google/chromeos/Kconfig // for the definition of these: - CONFIG_VBOOT_VBNV_OFFSET, + CONFIG_VBOOT_VBNV_OFFSET - 14, VBOOT_VBNV_BLOCK_SIZE }) Return(VNBV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I928457febd399526fa77108d12b804ca7e53f80b Gerrit-Change-Number: 38918 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: [WIP]coreboot_tables: Support multiple framebuffers
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39005 ) Change subject: [WIP]coreboot_tables: Support multiple framebuffers ...................................................................... [WIP]coreboot_tables: Support multiple framebuffers Advertise each framebuffer in a seperate CB table and get rid of fill_lb_framebuffer. Change-Id: I31c3da71ca0b96fb25219d6125c5f89d12157f74 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/lib/edid_fill_fb.c 3 files changed, 23 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39005/1 diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 5bebd4a..3887a29 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -18,14 +18,11 @@ void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data); +void lb_framebuffer(struct lb_header *header); /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); -/* Define this function to fill in the frame buffer returning 0 on success and - < 0 on error. */ -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer); - /* Allow arch to add records. */ void lb_arch_add_records(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..3f9b2dc 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -133,28 +133,6 @@ console->type = consoletype; } -static void lb_framebuffer(struct lb_header *header) -{ - struct lb_framebuffer *framebuffer; - struct lb_framebuffer fb = {0}; - - if (!CONFIG(LINEAR_FRAMEBUFFER) || fill_lb_framebuffer(&fb)) - return; - - framebuffer = (struct lb_framebuffer *)lb_new_record(header); - memcpy(framebuffer, &fb, sizeof(*framebuffer)); - framebuffer->tag = LB_TAG_FRAMEBUFFER; - framebuffer->size = sizeof(*framebuffer); - - if (CONFIG(BOOTSPLASH)) { - uint8_t *fb_ptr = (uint8_t *)(uintptr_t)framebuffer->physical_address; - unsigned int width = framebuffer->x_resolution; - unsigned int height = framebuffer->y_resolution; - unsigned int depth = framebuffer->bits_per_pixel; - set_bootsplash(fb_ptr, width, height, depth); - } -} - void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count) { @@ -531,8 +509,10 @@ /* Record our various random string information */ lb_strings(head); lb_record_version_timestamp(head); + /* Record our framebuffer */ - lb_framebuffer(head); + if (CONFIG(LINEAR_FRAMEBUFFER)) + lb_framebuffer(head); #if CONFIG(CHROMEOS) /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 3abcdd0..1928335 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -36,6 +36,8 @@ /* * Allocate a new framebuffer info struct on heap. + * The caller must not free the returned pointer. + * * Returns NULL on error. */ struct edid_fb_info *fb_new_framebuffer_info(void) @@ -147,13 +149,25 @@ return info; } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +void lb_framebuffer(struct lb_header *header) { + struct lb_framebuffer *framebuffer; + for (struct edid_fb_info *i = list; i != NULL; i = i->next) { - if (i->valid) { - *framebuffer = i->edid_fb; - return 0; + if (!i->valid) + continue; + + framebuffer = (struct lb_framebuffer *)lb_new_record(header); + memcpy(framebuffer, &i->edid_fb, sizeof(*framebuffer)); + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + + if (CONFIG(BOOTSPLASH)) { + uint8_t *fb_ptr = (uint8_t *)(uintptr_t)framebuffer->physical_address; + unsigned int width = framebuffer->x_resolution; + unsigned int height = framebuffer->y_resolution; + unsigned int depth = framebuffer->bits_per_pixel; + set_bootsplash(fb_ptr, width, height, depth); } } - return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31c3da71ca0b96fb25219d6125c5f89d12157f74 Gerrit-Change-Number: 39005 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: drivers/analogix: fixup the video banking area timing to meet chip
by jitao shi (Code Review) 07 Aug '23

07 Aug '23

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39026 ) Change subject: drivers/analogix: fixup the video banking area timing to meet chip ...................................................................... drivers/analogix: fixup the video banking area timing to meet chip Fixup HFP/HBP/HSYNC meet the chip (must larger than 8 and even number) BUG=b:149051882 BRANCH=kukui TEST=None Change-Id: I3715fa854649f20fbef4e0bdfce59ebfa1f5f2b5 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39026/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index d2d09d8..10aa8b5 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -827,6 +827,119 @@ dt->vactive, dt->vsync_len, dt->vfront_porch, dt->vback_porch); } +static void anx7625_modify_edid(struct edid *edid, + struct display_timing *dt) +{ + u32 hsync, hfp, hbp, hactive, hblanking, htotal, vtotal; + u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; + u32 vref, adj_clock; + + hactive = dt->hactive; + hfp = dt->hfront_porch; + hbp = dt->hback_porch; + hsync = dt->hsync_len; + hblanking = hfp + hbp + hsync; + htotal = hactive + hfp + hbp + hsync; + vtotal = dt->vactive + dt->vsync_len + + dt->vfront_porch + dt->vback_porch; + + ANXINFO("before mode fixup\n"); + ANXINFO("hsync(%d),hfp(%d),hbp(%d),clock(%d)\n", + hsync, + hfp, + hbp, + dt->pixelclock); + + adj_hfp = hfp; + adj_hsync = hsync; + adj_hbp = hbp; + adj_hblanking = hblanking; + + /* plus 1 if hfp is odd */ + if (hfp & 0x1) { + adj_hfp = hfp + 1; + adj_hblanking += 1; + } + + /* minus 1 if hbp is odd */ + if (hbp & 0x1) { + adj_hbp = hbp - 1; + adj_hblanking -= 1; + } + + /* plus 1 if hsync is odd */ + if (hsync & 0x1) { + if (adj_hblanking < hblanking) + adj_hsync = hsync + 1; + else + adj_hsync = hsync - 1; + } + + /* + * once illegal timing detected, use default HFP, HSYNC, HBP + */ + if ((hblanking < HBLANKING_MIN) || (hfp < HP_MIN && hbp < HP_MIN)) + { + adj_hsync = SYNC_LEN_DEF; + adj_hfp = HFP_HBP_DEF; + adj_hbp = HFP_HBP_DEF; + vref = dt->pixelclock * 1000 / (htotal * vtotal); + if (hblanking < HBLANKING_MIN) { + delta_adj = HBLANKING_MIN - hblanking; + adj_clock = vref * delta_adj * vtotal; + dt->pixelclock += DIV_ROUND_UP(adj_clock, 1000); + } else { + delta_adj = hblanking - HBLANKING_MIN; + adj_clock = vref * delta_adj * vtotal; + dt->pixelclock -= DIV_ROUND_UP(adj_clock, 1000); + } + + ANXINFO("warn: illegal hblanking timing, use default.\n"); + ANXINFO("warn: hfp(%d),hbp(%d),hsync(%d).\n", hfp, hbp, hsync); + } else if (adj_hfp < HP_MIN) { + /* adjust hfp if hfp less than HP_MIN */ + delta_adj = HP_MIN - adj_hfp; + adj_hfp = HP_MIN; + + /* + * balance total HBlanking pixel, if HBP hasn't enough space, + * adjust HSYNC length, otherwize adjust HBP + */ + if ((adj_hbp - delta_adj) < HP_MIN) + /* hbp not enough space */ + adj_hsync -= delta_adj; + else + adj_hbp -= delta_adj; + } else if (adj_hbp < HP_MIN) { + delta_adj = HP_MIN - adj_hbp; + adj_hbp = HP_MIN; + + /* + * balance total HBlanking pixel, if HBP hasn't enough space, + * adjust HSYNC length, otherwize adjust HBP + */ + if ((adj_hfp - delta_adj) < HP_MIN) + /* hbp not enough space */ + adj_hsync -= delta_adj; + else + adj_hfp -= delta_adj; + } + + ANXINFO("after mode fixup\n"); + ANXINFO("hsync(%d),hfp(%d),hbp(%d),clock(%d)\n", + adj_hsync, + adj_hfp, + adj_hbp, + dt->pixelclock); + + /* reconstructure EDID */ + edid->mode.hspw = adj_hsync; + edid->mode.hso = adj_hfp + edid->mode.hborder; + edid->mode.hbl = adj_hbp + edid->mode.hso + + edid->mode.hspw + edid->mode.hborder; + edid->mode.pixel_clock = dt->pixelclock; +} + int anx7625_dp_start(uint8_t bus, const struct edid *edid) { int ret; @@ -847,6 +960,7 @@ { int block_num; int ret; + struct display_timing dtiming; u8 edid[FOUR_BLOCK_SIZE]; block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); @@ -861,6 +975,10 @@ return -1; } + anx7625_parse_edid(out, &dtiming); + + anx7625_modify_edid(out, &dtiming); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3715fa854649f20fbef4e0bdfce59ebfa1f5f2b5 Gerrit-Change-Number: 39026 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: Signed-off-by: mirek190 <mirek190@gmail.com>
by Miroslaw Kocur (Code Review) 07 Aug '23

07 Aug '23

Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39219 ) Change subject: Signed-off-by: mirek190 <mirek190(a)gmail.com> ...................................................................... Signed-off-by: mirek190 <mirek190(a)gmail.com> Inicial device tree for Microtech etabpro Platform Inlet GLK Tablet with the stylus and attachable keboard Change-Id: I0fcc4f313303fdbc6d44d4cdc7005564969b4afe --- A src/mainboard/microtech/Kconfig A src/mainboard/microtech/Kconfig.name A src/mainboard/microtech/etabpro/Kconfig A src/mainboard/microtech/etabpro/Kconfig.name A src/mainboard/microtech/etabpro/Makefile.inc A src/mainboard/microtech/etabpro/board_info.txt A src/mainboard/microtech/etabpro/boardid.c A src/mainboard/microtech/etabpro/bootblock.c A src/mainboard/microtech/etabpro/chromeos.c A src/mainboard/microtech/etabpro/devicetree.cb A src/mainboard/microtech/etabpro/dptf.asl A src/mainboard/microtech/etabpro/dsdt.asl A src/mainboard/microtech/etabpro/ec.c A src/mainboard/microtech/etabpro/ec.h A src/mainboard/microtech/etabpro/etab.fmd A src/mainboard/microtech/etabpro/gpio.c A src/mainboard/microtech/etabpro/gpio.h A src/mainboard/microtech/etabpro/mainboard.c A src/mainboard/microtech/etabpro/memory.c A src/mainboard/microtech/etabpro/nhlt.c A src/mainboard/microtech/etabpro/romstage.c A src/mainboard/microtech/etabpro/smihandler.c A src/mainboard/microtech/etabpro/touchpad.asl A src/mainboard/microtech/etabpro/touchpanel.asl A src/mainboard/microtech/etabpro/variants.h 25 files changed, 1,986 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39219/1 diff --git a/src/mainboard/microtech/Kconfig b/src/mainboard/microtech/Kconfig new file mode 100644 index 0000000..a757136 --- /dev/null +++ b/src/mainboard/microtech/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_MICROTECH + +choice + prompt "Mainboard model" + +source "src/mainboard/microtech/*/Kconfig.name" + +endchoice + +source "src/mainboard/microtech/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "MCROTECH" + +endif # VENDOR_MICROTECH diff --git a/src/mainboard/microtech/Kconfig.name b/src/mainboard/microtech/Kconfig.name new file mode 100644 index 0000000..bc37123 --- /dev/null +++ b/src/mainboard/microtech/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_MICROTECH + bool "MICROTECH" diff --git a/src/mainboard/microtech/etabpro/Kconfig b/src/mainboard/microtech/etabpro/Kconfig new file mode 100644 index 0000000..3510021 --- /dev/null +++ b/src/mainboard/microtech/etabpro/Kconfig @@ -0,0 +1,98 @@ +if BOARD_MICROTECH_ETABPRO + +config BOARD_INTEL_BASEBOARD_GLKRVP + def_bool n + select SOC_INTEL_GLK + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select SOC_ESPI +# Blobs +# select NEED_IFWI +# select HAVE_IFD_BIN +# config for GLK CHROME EC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select VBOOT_LID_SWITCH + select EC_GOOGLE_CHROMEEC_SWITCHES +# config for GLK INTEL_EC +# Not sure is VBOOT_NO_BOARD_SUPPORT is needed to work coreboot on GLK. Without it we got error if I choose GLK INTEL_EC... +# select EC_ACPI +# select VBOOT_NO_BOARD_SUPPORT + + +config IFWI_FILE + string + default "3rdparty/blobs/mainboard/microtech/etabpro/ifwi.bin" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/microtech/etabpro/ifd.bin" + +config BASEBOARD_GLKRVP_LAPTOP + def_bool y + select SYSTEM_TYPE_LAPTOP + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/etab.fmd" + +config CHROMEOS + bool + default y + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config MAINBOARD_DIR + string + default "microtech/etabpro" + +config VARIANT_DIR + string + default "glkrvp" + +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "etabpro" + +config MAINBOARD_FAMILY + string + default "Intel_Glkrvp" + +config MAX_CPUS + int + default 2 + +config UART_FOR_CONSOLE + int + default 2 + +config IS_GLK_RVP_1 + bool "Is this RVP1?" + default n + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool + default y + +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio" + select NHLT_DMIC_2CH_16B + select NHLT_DMIC_4CH_16B + select NHLT_MAX98357 + +endif # BOARD_MICROTECH_ETABPRO diff --git a/src/mainboard/microtech/etabpro/Kconfig.name b/src/mainboard/microtech/etabpro/Kconfig.name new file mode 100644 index 0000000..bc505e5 --- /dev/null +++ b/src/mainboard/microtech/etabpro/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_MICROTECH_ETABPRO + bool "etabpro" + select BOARD_INTEL_BASEBOARD_GLKRVP + select BASEBOARD_GLKRVP_LAPTOP diff --git a/src/mainboard/microtech/etabpro/Makefile.inc b/src/mainboard/microtech/etabpro/Makefile.inc new file mode 100644 index 0000000..9835dfb --- /dev/null +++ b/src/mainboard/microtech/etabpro/Makefile.inc @@ -0,0 +1,21 @@ +bootblock-y += bootblock.c +bootblock-y += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c + +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-y += smihandler.c + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += boardid.c +ramstage-y += gpio.c +ramstage-y += nhlt.c +smm-y += gpio.c + diff --git a/src/mainboard/microtech/etabpro/board_info.txt b/src/mainboard/microtech/etabpro/board_info.txt new file mode 100644 index 0000000..983b2df --- /dev/null +++ b/src/mainboard/microtech/etabpro/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Microtech +Board name: etabpro glk board 8 MB bios rom +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/microtech/etabpro/boardid.c b/src/mainboard/microtech/etabpro/boardid.c new file mode 100644 index 0000000..0923e9d --- /dev/null +++ b/src/mainboard/microtech/etabpro/boardid.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variants.h" +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +int variant_board_id(void) +{ + MAYBE_STATIC_NONZERO uint32_t id = BOARD_ID_INIT; + + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (id == BOARD_ID_INIT) { + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + } + return id; + } else { + return 0; + } +} diff --git a/src/mainboard/microtech/etabpro/bootblock.c b/src/mainboard/microtech/etabpro/bootblock.c new file mode 100644 index 0000000..3d27050 --- /dev/null +++ b/src/mainboard/microtech/etabpro/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variants.h" +#include <bootblock_common.h> +#include <ec/ec.h> +#include <intelblocks/lpc_lib.h> +#include <soc/gpio.h> +#include "ec.h" + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + lpc_configure_pads(); + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); + mainboard_ec_init(); +} diff --git a/src/mainboard/microtech/etabpro/chromeos.c b/src/mainboard/microtech/etabpro/chromeos.c new file mode 100644 index 0000000..f59b462 --- /dev/null +++ b/src/mainboard/microtech/etabpro/chromeos.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variants.h" +#include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/gpio.h> +#include "gpio.h" + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} + +int __weak get_lid_switch(void) +{ + return -1; +} diff --git a/src/mainboard/microtech/etabpro/devicetree.cb b/src/mainboard/microtech/etabpro/devicetree.cb new file mode 100644 index 0000000..e132f14 --- /dev/null +++ b/src/mainboard/microtech/etabpro/devicetree.cb @@ -0,0 +1,285 @@ +chip soc/intel/apollolake + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak) + # as it is required for detection + register "pcie_rp_deemphasis_enable[2]" = "0" + # Set de-emphasis to default (enabled) for remaining ports + register "pcie_rp_deemphasis_enable[0]" = "1" + register "pcie_rp_deemphasis_enable[1]" = "1" + register "pcie_rp_deemphasis_enable[3]" = "1" + register "pcie_rp_deemphasis_enable[4]" = "1" + register "pcie_rp_deemphasis_enable[5]" = "1" + + # GPIO for PERST_0 (WLAN_PE_RST) + register "prt0_gpio" = "GPIO_164" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + # DW1 is used by: + # - GPIO_63 - H1_PCH_INT_ODL + # DW2 is used by: + # - GPIO_141 - EC_PCH_WAKE_ODL + # - GPIO_142 - TRACKPAD_INT2_1V8_ODL + # - GPIO_144 - PEN_EJECT_ODL + # DW3 is used by: + # - GPIO_117 - LTE_WAKE_ODL + # - GPIO_119 - WLAN_PCIE_WAKE_ODL + register "gpe0_dw1" = "PMC_GPE_NW_63_32" + register "gpe0_dw2" = "PMC_GPE_N_95_64" + register "gpe0_dw3" = "PMC_GPE_N_63_32" + + # PL1 override 10000 mW: Due to error in the energy calculation for + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 10W. + register "tdp_pl1_override_mw" = "10000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + register "pnp_settings" = "PNP_PERF_POWER" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 off end # - Gen + device pci 03.0 off end # - Iunit + chip drivers/intel/wifi + register "wake" = "GPE0A_CNVI_PME_STS" + device pci 0c.0 on end # - CNVi + end + device pci 0d.0 off end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 off end # - Fast SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # - Audio + device pci 0f.0 on end # - Heci1 + device pci 0f.1 off end # - Heci2 + device pci 0f.2 off end # - Heci3 + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_11" + device pci 00.0 on end + end + end # - PCIe-A 0 Onboard M2 Slot(Wifi) + device pci 13.1 on end # - PCIe-A 1 + device pci 13.2 on end # - PCIe-A 2 + device pci 13.3 off end # - PCIe-A 3 + device pci 14.0 off end # - PCIe-B 0 + device pci 14.1 off end # - PCIe-B 1 + device pci 15.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""User Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""World Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""SDCard"" + register "type" = "UPC_TYPE_EXPRESSCARD" + device usb 3.5 on end + end + end + end + end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)" + device spi 0 on end + end + end # - GSPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # - ESPI + device pci 1f.1 on end # - SMBUS + end + + # FSP provides UPD interface to execute IPC command. PMIC has + # I2C_Slave_Address (31:24): 0x5E, Register_Offset (23:16): 0x43, + # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. + # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. + # uint8 RegOrValue, RegAndValue, PmicReadReg + # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0Xff); + # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0Xff); + # PmicReadReg &= RegAndValue; + # PmicReadReg |= RegOrValue; + # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field + # and D[7:3] RSVD will not be impacted. + + # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay + # from 100ms to 10ms. + # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, + # 101=50ms, 110=75ms, 111=100ms (default) + register "PmicPmcIpcCtrl" = "0x5e4302f8" +end diff --git a/src/mainboard/microtech/etabpro/dptf.asl b/src/mainboard/microtech/etabpro/dptf.asl new file mode 100644 index 0000000..f61f0b6 --- /dev/null +++ b/src/mainboard/microtech/etabpro/dptf.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/microtech/etabpro/dsdt.asl b/src/mainboard/microtech/etabpro/dsdt.asl new file mode 100644 index 0000000..c1c0924 --- /dev/null +++ b/src/mainboard/microtech/etabpro/dsdt.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include "dptf.asl" + /* Include soc specific DPTF changes */ + #include <soc/intel/apollolake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/microtech/etabpro/ec.c b/src/mainboard/microtech/etabpro/ec.c new file mode 100644 index 0000000..9d44ea9 --- /dev/null +++ b/src/mainboard/microtech/etabpro/ec.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/lpc_lib.h> +#include "ec.h" + +static void ramstage_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + printk(BIOS_ERR, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +static void bootblock_ec_init(void) +{ + uint16_t ec_ioport_base; + size_t ec_ioport_size; + + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 + | LPC_IOE_LGE_200); + google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size); + lpc_open_pmio_window(ec_ioport_base, ec_ioport_size); +} + +void mainboard_ec_init(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (ENV_RAMSTAGE) + ramstage_ec_init(); + else if (ENV_BOOTBLOCK) + bootblock_ec_init(); + } else if (ENV_BOOTBLOCK) { + /* + * Set up LPC decoding for the ChromeEC I/O port ranges: + * - Ports 62/66, 60/64, and 200->208 + * - ChromeEC specific communication I/O ports. + */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 + | LPC_IOE_LGE_200); + } + + if (CONFIG(GLK_INTEL_EC)) { + printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n"); + outb(0xaa, 0x66); + printk(BIOS_INFO, "Hack to turn on the CPU fan\n"); + outb(0x81, 0x66); + outb(0x44, 0x62); + outb(0x32, 0x62); + /* Need delay here, hence second outb */ + outb(0x32, 0x62); + outb(0x1a, 0x66); + } +} diff --git a/src/mainboard/microtech/etabpro/ec.h b/src/mainboard/microtech/etabpro/ec.h new file mode 100644 index 0000000..d31d35a --- /dev/null +++ b/src/mainboard/microtech/etabpro/ec.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_EC_H +#define BASEBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif diff --git a/src/mainboard/microtech/etabpro/etab.fmd b/src/mainboard/microtech/etabpro/etab.fmd new file mode 100644 index 0000000..c71088a --- /dev/null +++ b/src/mainboard/microtech/etabpro/etab.fmd @@ -0,0 +1,35 @@ +FLASH 8M { + SI_DESC 0x1000 + SI_BIOS { + IFWI 0x2ff000 + OBBP { + FMAP 0x1000 + RO_FRID 0x40 + GBB 0x40000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + CONSOLE 0x20000 + COREBOOT(CBFS) + SIGN_CSE 0x2000 + BIOS_UNUSABLE 0x4000 + } + } + RW_SECTION_A 0x70100 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x60000 + RW_FWID_A 0x100 + } + RW_SECTION_B 0x70100 { + VBLOCK_B 0x10000 + FW_MAIN_B(CBFS) 0x60000 + RW_FWID_B 0x100 + } + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 + } +} + diff --git a/src/mainboard/microtech/etabpro/gpio.c b/src/mainboard/microtech/etabpro/gpio.c new file mode 100644 index 0000000..8dedbe0 --- /dev/null +++ b/src/mainboard/microtech/etabpro/gpio.c @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <gpio.h> +#include "variants.h" +#include <commonlib/helpers.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { +/* NORTHWEST COMMUNITY GPIOS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 1, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */ + PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */ + PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/ + PAD_CFG_GPI_APIC_IOS(GPIO_20, UP_20K, DEEP, LEVEL, INVERT, IGNORE, SAME),/* Audio Codec Interrupt*/ + PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */ + PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */ + PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Wake SCI */ + PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/ + PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */ + PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */ + PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */ + PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */ + PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SDA - Audio Codec*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SCL - Audio Codec */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SDA - NFC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SCL - NFC */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SDA - Touch Pad*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SCL - Touch Pad*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RXD - M.2dGNSS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-TXD - M.2dGNSS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RTS_B - M.2 dGNSS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-CTS_B - M.2 dGNSS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */ +#if CONFIG(TPM_ON_FAST_SPI) + PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */ +#endif + PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/ + PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/ + PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/ + PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/ + PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/ + PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/ + PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/ + PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/ + PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_212, UP_20K, DEEP),/*Touch Panel Int*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/ +/* NORTH COMMUNITY GPIOS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */ + PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/ + PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/ + PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ + PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ + PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ + PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/ + PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SDA*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SCL*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SDA*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SCL*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SDA*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SCL*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */ + PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/ + PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/ + PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ + PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/ + PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/ + PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ + PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/ + PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/ + PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/ + PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/ + PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ + PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/ + +/* AUDIO COMMUNITY GPIOS*/ + + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_BCLK*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_WS_SYNC*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, DN_20K, DEEP, NF2, HIZCRx1, SAME),/* AVS_I2S2_SDI*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_SD0*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S1_MCLK*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1),/*AVS_M_CLK_A1*/ + PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1),/*AVS_M_DATA_1*/ + PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/ + +/* SCC COMMUNITY GPIOS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD),/*SDCARD_CLK*/ + PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D0*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D1*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D2*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D3*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_CMD*/ + PAD_CFG_NF(GPIO_186, NONE, DEEP, NF1),/*SDCARD_CD_B*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, NONE, TxDRxE, SAME),/*SD Card*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), + PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/ + PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/ + PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/ + PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/ + PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/ + PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/ + PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/ + PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/ + PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/ + PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/ + PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/ + PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/ + PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/ + PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/ + PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/ +}; + +const struct pad_config * __weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */ +}; + +const struct pad_config * __weak +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* GPIO settings before entering sleep. */ +static const struct pad_config sleep_gpio_table[] = { +#if 0 + PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ +#endif +}; + +const struct pad_config * __weak +variant_sleep_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { +#if 0 + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +#endif +}; + +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/microtech/etabpro/gpio.h b/src/mainboard/microtech/etabpro/gpio.h new file mode 100644 index 0000000..170e87c --- /dev/null +++ b/src/mainboard/microtech/etabpro/gpio.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include <soc/gpio.h> + +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#if CONFIG(SOC_ESPI) +#define EC_SCI_GPI GPE0A_ESPI_SCI_STS +#else +#define EC_SCI_GPI GPE0_DW1_05 +#endif + +/* EC SMI */ +#define EC_SMI_GPI GPIO_41 + +#define GPE_EC_WAKE GPE0_DW1_06 + +/* Memory SKU GPIOs. */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/microtech/etabpro/mainboard.c b/src/mainboard/microtech/etabpro/mainboard.c new file mode 100644 index 0000000..af0b1a3 --- /dev/null +++ b/src/mainboard/microtech/etabpro/mainboard.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variants.h" +#include <boardid.h> +#include <console/console.h> +#include <device/device.h> +#include <ec/ec.h> +#include <nhlt.h> +#include <soc/gpio.h> +#include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include "ec.h" +#include "gpio.h" + +static void mainboard_init(void *chip_info) +{ + int boardid; + const struct pad_config *pads; + size_t num; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + mainboard_ec_init(); +} + +static unsigned long mainboard_write_acpi_tables( + struct device *device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/microtech/etabpro/memory.c b/src/mainboard/microtech/etabpro/memory.c new file mode 100644 index 0000000..3f738d6 --- /dev/null +++ b/src/mainboard/microtech/etabpro/memory.c @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variants.h" +#include <gpio.h> +#include <soc/meminit.h> +#include "gpio.h" + +const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = { + /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */ + .phys[LP4_PHYS_CH0A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 6, 7, 5, 4, 3, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 12, 10, 11, 13, 14, 8, 9, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 16, 22, 23, 20, 18, 17, 19, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 30, 28, 29, 25, 24, 26, 27, 31 }, + }, + .phys[LP4_PHYS_CH0B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 7, 3, 5, 2, 6, 0, 1, 4 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 9, 14, 12, 13, 10, 11, 8, 15 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 22, 23, 16, 19, 17, 18, 21 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 28, 24, 26, 27, 29, 30, 31, 25 }, + }, + .phys[LP4_PHYS_CH1A] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 2, 1, 6, 7, 5, 4, 3, 0 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 11, 10, 8, 9, 12, 15, 13, 14 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 17, 23, 19, 16, 21, 22, 20, 18 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 31, 29, 26, 25, 28, 27, 24, 30 }, + }, + .phys[LP4_PHYS_CH1B] = { + /* DQA[0:7] pins of LPDDR4 module. */ + .dqs[LP4_DQS0] = { 4, 3, 7, 5, 6, 1, 0, 2 }, + /* DQA[8:15] pins of LPDDR4 module. */ + .dqs[LP4_DQS1] = { 15, 9, 8, 11, 14, 13, 12, 10 }, + /* DQB[0:7] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS2] = { 20, 23, 22, 21, 18, 19, 16, 17 }, + /* DQB[7:15] pins of LPDDR4 module with offset of 16. */ + .dqs[LP4_DQS3] = { 25, 28, 30, 31, 26, 27, 24, 29 }, + }, +}; + +static const struct lpddr4_sku skus[] = { + /* + * K4F6E304HB-MGCJ - both logical channels While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the density as 8Gb per rank. + */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", + }, + /* + * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the density as 8Gb per rank. + */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, + }, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + [3] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, + }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &baseboard_lpddr4_swizzle, +}; + +const struct lpddr4_cfg * __weak variant_lpddr4_config(void) +{ + return &lp4cfg; +} + +size_t __weak variant_memory_sku(void) +{ + return 0; +} diff --git a/src/mainboard/microtech/etabpro/nhlt.c b/src/mainboard/microtech/etabpro/nhlt.c new file mode 100644 index 0000000..73cae3d --- /dev/null +++ b/src/mainboard/microtech/etabpro/nhlt.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variants.h" +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __weak variant_nhlt_init(struct nhlt *nhlt) +{ + /* 1-dmic configuration */ + if (CONFIG(NHLT_DMIC_1CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 1)) + printk(BIOS_ERR, "Added 1CH DMIC array.\n"); + /* 2-dmic configuration */ + if (CONFIG(NHLT_DMIC_2CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Added 2CH DMIC array.\n"); + /* 4-dmic configuration */ + if (CONFIG(NHLT_DMIC_4CH_16B) && + !nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Added 4CH DMIC array.\n"); + + /* Dialog for Headset codec. + * Headset codec is bi-directional but uses the same configuration + * settings for render and capture endpoints. + */ + if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2)) + printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Added Maxim_98357 codec.\n"); +} diff --git a/src/mainboard/microtech/etabpro/romstage.c b/src/mainboard/microtech/etabpro/romstage.c new file mode 100644 index 0000000..6cf48c3 --- /dev/null +++ b/src/mainboard/microtech/etabpro/romstage.c @@ -0,0 +1,239 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include "variants.h" +#include <boardid.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +#define BOARD_ID_GLK_RVP1_DDR4 0x5 /* GLK RVP1 - DDR4 */ +#define BOARD_ID_GLK_RVP2_LP4SD 0x7 /* GLK RVP2 - LP4 Solder Down */ +#define BOARD_ID_GLK_RVP2_LP4 0x8 /* RVP2 - LP4 Socket */ + +/* DDR4 specific swizzling data start */ + +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0_ddr4[] = { + 15, 14, 10, 11, 8, 9, 13, 12, 2, 7, 3, 6, 4, 0, 1, 5, + 29, 31, 27, 26, 24, 28, 25, 30, 19, 22, 18, 21, 23, 16, 17, 20, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1_ddr4[] = { + 1, 0, 4, 5, 7, 2, 6, 3, 24, 25, 28, 30, 26, 27, 31, 29, + 21, 20, 17, 16, 23, 22, 19, 18, 8, 12, 11, 15, 10, 9, 13, 14, +}; + +/* Channel 1 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch2_ddr4[] = { + 14, 12, 9, 13, 10, 15, 11, 8, 1, 3, 7, 5, 2, 6, 0, 4, + 27, 24, 29, 28, 30, 26, 31, 25, 19, 20, 18, 22, 16, 21, 23, 17, +}; + +/* Channel 0 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch3_ddr4[] = { + 12, 8, 13, 9, 15, 11, 14, 10, 0, 5, 1, 4, 7, 2, 6, 3, + 20, 16, 21, 17, 19, 18, 22, 23, 29, 24, 28, 26, 25, 30, 31, 27 +}; +/* DDR4 specific swizzling data end*/ + +/* LPDD4 specific swizzling data start */ + +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0_lpddr4[] = { + 10, 8, 12, 11, 9, 13, 14, 15, 1, 3, 2, 0, 5, 4, 6, 7, + 30, 26, 24, 25, 28, 29, 31, 27, 20, 21, 22, 16, 23, 17, 18, 19, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1_lpddr4[] = { + 0, 6, 7, 5, 3, 2, 1, 4, 12, 15, 13, 8, 9, 10, 11, 14, + 17, 18, 19, 16, 23, 20, 21, 22, 30, 31, 25, 27, 26, 29, 28, 24, +}; + +/* Channel 1 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch2_lpddr4[] = { + 15, 8, 11, 10, 14, 12, 13, 9, 5, 1, 0, 6, 2, 3, 7, 4, + 31, 25, 24, 27, 30, 29, 28, 26, 21, 18, 20, 23, 16, 17, 22, 19, +}; + +/* Channel 0 PHY 1 to DUnit DQ mapping */ +static const uint8_t swizzling_ch3_lpddr4[] = { + 15, 9, 8, 10, 13, 14, 12, 11, 7, 6, 5, 0, 4, 2, 1, 3, + 20, 21, 23, 22, 19, 17, 18, 16, 24, 27, 26, 30, 25, 31, 28, 29 +}; +/* LPDD4 specific swizzling data end */ + +static void fill_lpddr4_params(FSP_M_CONFIG *cfg) +{ + cfg->Package = 1; + cfg->MemoryDown = 1; + cfg->DDR3LPageSize = 0; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 2; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 0; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->RmtCheckRun = 0; + cfg->RmtMarginCheckScaleHighThreshold = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + cfg->Profile = 7; + cfg->DIMM0SPDAddress = 0x00; + cfg->DIMM1SPDAddress = 0x00; + cfg->Ch0_RankEnable = 0x1; + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch0_DramDensity = 0x2; + cfg->Ch0_Option = 0x3; + cfg->Ch0_TristateClk1 = 0; + cfg->Ch0_Mode2N = 0; + cfg->Ch0_OdtLevels = 0; + cfg->Ch1_RankEnable = 0x1; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch1_DramDensity = 0x2; + cfg->Ch1_Option = 0x3; + cfg->Ch1_TristateClk1 = 0; + cfg->Ch1_Mode2N = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch2_RankEnable = 0x1; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch2_DramDensity = 0x2; + cfg->Ch2_Option = 0x3; + cfg->Ch2_TristateClk1 = 0; + cfg->Ch2_Mode2N = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch3_RankEnable = 0x1; + cfg->Ch3_DeviceWidth = 0x1; + cfg->Ch3_DramDensity = 0x2; + cfg->Ch3_Option = 0x3; + cfg->Ch3_TristateClk1 = 0; + cfg->Ch3_Mode2N = 0; + cfg->Ch3_OdtLevels = 0; + /* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_lpddr4, + sizeof(swizzling_ch0_lpddr4)); + /* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_lpddr4, + sizeof(swizzling_ch1_lpddr4)); + /* phy1 ch1 */ + memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_lpddr4, + sizeof(swizzling_ch2_lpddr4)); + /* phy1 ch0 */ + memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_lpddr4, + sizeof(swizzling_ch3_lpddr4)); +} + +static void fill_ddr4_params(FSP_M_CONFIG *cfg) +{ + cfg->Package = 0; /* 0x1:BGA */ + cfg->MemoryDown = 0; + cfg->DDR3LPageSize = 1; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 0; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->RmtCheckRun = 0; + cfg->RmtMarginCheckScaleHighThreshold = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + cfg->Profile = 11; + cfg->DIMM0SPDAddress = 0xA0; + cfg->DIMM1SPDAddress = 0xA4; + cfg->Ch0_RankEnable = 0x3; + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch0_DramDensity = 0x0; + cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch0_TristateClk1 = 0; + cfg->Ch0_Mode2N = 0; + cfg->Ch0_OdtLevels = 0; + cfg->Ch1_RankEnable = 0x3; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch1_DramDensity = 0x2; + cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch1_TristateClk1 = 0; + cfg->Ch1_Mode2N = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch2_RankEnable = 0x0; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch2_DramDensity = 0x2; + cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch2_TristateClk1 = 0; + cfg->Ch2_Mode2N = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch3_RankEnable = 0x0; + cfg->Ch3_DeviceWidth = 0x1; + cfg->Ch3_DramDensity = 0x2; + cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch3_TristateClk1 = 0; + cfg->Ch3_Mode2N = 0; + cfg->Ch3_OdtLevels = 0; + + /* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4, + sizeof(swizzling_ch0_ddr4)); + /* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4, + sizeof(swizzling_ch1_ddr4)); + /* phy1 ch1 */ + memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_ddr4, + sizeof(swizzling_ch2_ddr4)); + /* phy1 ch0 */ + memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_ddr4, + sizeof(swizzling_ch3_ddr4)); +} + +static void fill_memory_params(FSP_M_CONFIG *cfg) +{ + uint8_t boardid; + + if (CONFIG(IS_GLK_RVP_1)) + boardid = BOARD_ID_GLK_RVP1_DDR4; + else + boardid = BOARD_ID_GLK_RVP2_LP4; + + switch (boardid) { + case BOARD_ID_GLK_RVP1_DDR4: + fill_ddr4_params(cfg); + break; + case BOARD_ID_GLK_RVP2_LP4SD: + case BOARD_ID_GLK_RVP2_LP4: + fill_lpddr4_params(cfg); + break; + } +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *cfg = &memupd->FspmConfig; + fill_memory_params(cfg); +} + +void mainboard_save_dimm_info(void) +{ + save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku()); +} diff --git a/src/mainboard/microtech/etabpro/smihandler.c b/src/mainboard/microtech/etabpro/smihandler.c new file mode 100644 index 0000000..edabd49 --- /dev/null +++ b/src/mainboard/microtech/etabpro/smihandler.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variants.h" +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <soc/pm.h> +#include <soc/gpio.h> +#include "ec.h" +#include "gpio.h" + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void mainboard_smi_espi_handler(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_process_events(); +} diff --git a/src/mainboard/microtech/etabpro/touchpad.asl b/src/mainboard/microtech/etabpro/touchpad.asl new file mode 100644 index 0000000..6168fbb --- /dev/null +++ b/src/mainboard/microtech/etabpro/touchpad.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope (\_SB.PCI0.I2C4) + { + Device (TPAD) + { + Name(_ADR, One) + Name (_HID, "ALPS0001") + Name (_CID, "PNP0C50") + Name (_DDN, "ALPS Touchpad") + Name (_UID, 1) + Name (ISTP, 1) /* Touchpad */ + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x2C, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C4", // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPIO_18_IRQ + } + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ,) + { + 18 + } + }) + + Method (_STA) + { + Return (0xF) + } + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C - HID driver does not load without DSM + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return (Buffer (One) {0x03}) + } + Else + { + Return (Buffer (One) {0x00}) + } + } ElseIf (LEqual(Arg2, One)) { // Function 1 : HID Function + // HID Descriptor Address (IHV Specific) + Return(0x0020) + } Else { + Return (Buffer (One) {0x00}) + } + } Else { + Return (Buffer (One) {0x00}) + } + } + } +} diff --git a/src/mainboard/microtech/etabpro/touchpanel.asl b/src/mainboard/microtech/etabpro/touchpanel.asl new file mode 100644 index 0000000..225b891 --- /dev/null +++ b/src/mainboard/microtech/etabpro/touchpanel.asl @@ -0,0 +1,71 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB.PCI0.I2C7) { +// Touch Panels on I2C7 +// GPIO_212:TCH_PNL_INTR_LS_N North Community, IRQ number 0x75. +//------------------------ + Device (TPL1) { + Name (HID2, 1) + Name (_HID, "WCOM508E") // _HID: Hardware ID + Name (_CID, "PNP0C50") // _CID: Compatible ID + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + Name (SBFB, ResourceTemplate () { + I2cSerialBus ( + 0x000A, + ControllerInitiated, + 1000000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C7", + 0x00, + ResourceConsumer, + , + ) + }) + // + // GLK: Touchpanel Interrupt: GPIO_212: Northwest + // Pin 77 + // Direct IRQ 0x75 + // + Name (SBFG, ResourceTemplate () { + GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { + 77 + } + }) + Name (SBFI, ResourceTemplate () { + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) + { + 0x75, + } + }) + + Method (_INI, 0, NotSerialized) // _INI: Initialize + { + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) { + Return (ConcatenateResTemplate(SBFB, SBFG)) + } + } // Device (TPL0) +} diff --git a/src/mainboard/microtech/etabpro/variants.h b/src/mainboard/microtech/etabpro/variants.h new file mode 100644 index 0000000..cf91a04 --- /dev/null +++ b/src/mainboard/microtech/etabpro/variants.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/** + * variant_board_id() - Get the board id for the current board variant + * + * Return: board id on success, -1 on failure/error. + */ +int variant_board_id(void); + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num); + +/* Baseboard default swizzle. Can be reused if swizzle is same. */ +extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; +/* Return LPDDR4 configuration structure. */ +const struct lpddr4_cfg *variant_lpddr4_config(void); +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + +#endif /* BASEBOARD_VARIANTS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fcc4f313303fdbc6d44d4cdc7005564969b4afe Gerrit-Change-Number: 39219 Gerrit-PatchSet: 1 Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig
by Joel Kitching (Code Review) 07 Aug '23

07 Aug '23

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39342 ) Change subject: vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig ...................................................................... vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig Just make the implementation in bootmode.c __weak like the other functions related to recovery switch. Boards may still enable vboot without implementing this function. Kconfig was originally added in CB:22102. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iccef100fac1d71625039990373e40b29d52a0167 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/mistral/Kconfig M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/up/squared/Kconfig M src/security/vboot/Kconfig M src/security/vboot/bootmode.c 24 files changed, 21 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/39342/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c27b1e..f9d7a67 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -19,7 +19,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee430d0..becfefe 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -18,7 +18,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 745f084..829ccef 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -33,15 +33,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get_value(GPIO_Y10); // RECMODE_GPIO } +#endif diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 05d9e86..ca01fe2 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -32,16 +32,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ -#if CONFIG(EC_GOOGLE_CHROMEEC) - uint64_t ec_events; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -#else - return 0; -#endif -} diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index b7d0d31..2db1fcb 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -17,7 +17,6 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_MOCK_SECDATA - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_FORCE_DEV_SWITCH_ON config MAINBOARD_DIR diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index a82f50f..9b2d8c5 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -33,15 +33,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get_value(GPIO_X07); // RECMODE_GPIO } +#endif diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index e14e2e5..42aba05 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -52,15 +52,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get(GPIO_RECOVERY)) - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get(GPIO_RECOVERY); } +#endif diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index 8f28baf..50faf7e 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -20,7 +20,6 @@ config VBOOT select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 5020e9b..62e4137 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -33,13 +33,8 @@ int get_lid_switch(void) { - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; + /* Lid always open */ + return 1; } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 0933fe6..c1bc404 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -36,11 +36,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index fda7431..4f66b5d 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -24,11 +24,6 @@ #include "gen1.h" #include "gen2.h" -int get_recovery_mode_switch(void) -{ - return 0; -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 0882e88..1e5dd99 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -36,11 +36,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 6ad0b39..3da8971 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -35,11 +35,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 6ad0b39..3da8971 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -35,11 +35,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 16ea993..8a4956d 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -19,9 +19,6 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Compile-time settings for recovery mode. */ -#define REC_MODE_SETTING 0 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,11 +29,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_recovery_mode_switch(void) -{ - return REC_MODE_SETTING; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3ba2a60..781b668 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -28,7 +28,6 @@ select MISSING_BOARD_RESET config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 6adf4e9..2701046 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -16,7 +16,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index b10bdc8..7799d34 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index e46a0de..52afba5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 864e808..bba2501 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -15,7 +15,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e0f468c..0111115 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -41,7 +41,6 @@ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index 5db76fd..41bb3d3 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -17,7 +17,6 @@ select HAVE_INTEL_PTT config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 6ffb065..d9ccb75 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -216,14 +216,6 @@ This is the second part of the FWID written to various regions of a vboot firmware image to identify its version. -config VBOOT_NO_BOARD_SUPPORT - bool "Allow the use of vboot without board support" - default n - help - Enable weak function for get_recovery_mode_switch in order to - proceed with refactoring of the vboot2 code base. Later on this - code is removed and replaced by interfaces. - config RO_REGION_ONLY string "Additional files that should not be copied to RW" default "" diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 78c4320..55c1e79 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -42,6 +42,16 @@ return vboot_get_context()->flags & VB2_CONTEXT_DEVELOPER_MODE; } +int __weak get_recovery_mode_switch(void) +{ + return 0; +} + +int __weak get_recovery_mode_retrain_switch(void) +{ + return 0; +} + int __weak clear_recovery_mode_switch(void) { return 0; @@ -66,20 +76,7 @@ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, do_clear_recovery_mode_switch, NULL); -int __weak get_recovery_mode_retrain_switch(void) -{ - return 0; -} - int vboot_recovery_mode_memory_retrain(void) { return get_recovery_mode_retrain_switch(); } - -#if CONFIG(VBOOT_NO_BOARD_SUPPORT) -int __weak get_recovery_mode_switch(void) -{ - return 0; -} - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccef100fac1d71625039990373e40b29d52a0167 Gerrit-Change-Number: 39342 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: amd/agesa/hudson: Disable `isa_dma_init()`
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39377 ) Change subject: amd/agesa/hudson: Disable `isa_dma_init()` ...................................................................... amd/agesa/hudson: Disable `isa_dma_init()` coreboot on the ASUS F2A85-M PRO hangs there. After removing it, it runs through. SeaBIOS also hangs reading CBFS, but GRUB works fine. So it looks like, it’s needed for some legacy stuff. Change-Id: I7f581606f9f234cfb7a3fec2cc7f4172589f8153 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39377/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9c65d04..251ddd1 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -44,9 +43,6 @@ dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); - /* Initialize isa dma */ - isa_dma_init(); - /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/39377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f581606f9f234cfb7a3fec2cc7f4172589f8153 Gerrit-Change-Number: 39377 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: new local repo and the point where I am now with vostro 3360
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39688 ) Change subject: new local repo and the point where I am now with vostro 3360 ...................................................................... new local repo and the point where I am now with vostro 3360 Change-Id: I82e9b7b7c333de644d8db0fbe787d915891b8467 --- A grub.cfg A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Kconfig A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c A src/mainboard/dell/dell_system_vostro_3360/board_info.txt A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl A src/mainboard/dell/dell_system_vostro_3360/early_init.c A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads A src/mainboard/dell/dell_system_vostro_3360/gpio.c A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c A src/mainboard/dell/dell_system_vostro_3360/mainboard.c 18 files changed, 718 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/39688/1 diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 0000000..2ad31ee --- /dev/null +++ b/grub.cfg @@ -0,0 +1,3 @@ +configfile (ahci0,3)/boot/grub/grub.cfg +terminal_output --append cbmemc +set debug=atkeyb diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig new file mode 100644 index 0000000..dfcc0e1 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig @@ -0,0 +1,43 @@ +if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select GFX_GMA_PANEL_1_ON_LVDS + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default dell/dell_system_vostro_3360 + +config MAINBOARD_PART_NUMBER + string + default "Dell System Vostro 3360" + +config VGA_BIOS_FILE + string + default "pci8086,0156.rom" + +config VGA_BIOS_ID + string + default "8086,0156" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name new file mode 100644 index 0000000..8925217 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + bool "Dell System Vostro 3360" diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl new file mode 100644 index 0000000..a9177df --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl @@ -0,0 +1 @@ +#include<drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl new file mode 100644 index 0000000..552fb6c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c new file mode 100644 index 0000000..cfc2061 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb new file mode 100644 index 0000000..d234325 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "1700" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00040911" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1028 0x055c + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x055c + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x055c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x055c + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x055c + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x055c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x055c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x055c + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x055c + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x055c + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1028 0x055c + end + end +end diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl new file mode 100644 index 0000000..98c2ad4 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c new file mode 100644 index 0000000..6dbf226 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 0, 1, 3 }, + { 0, 1, 3 }, + { 1, 1, 4 }, + { 0, 1, 4 }, + { 1, 1, 5 }, + { 0, 1, 5 }, + { 1, 1, 6 }, + { 0, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads new file mode 100644 index 0000000..6cb572a --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c new file mode 100644 index 0000000..d7db210 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c new file mode 100644 index 0000000..c55bf3c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134213, /* Codec Vendor / Device ID: Cirrus */ + 0x1028055c, /* Subsystem ID */ + 6, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x1028055c), + AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f), + AZALIA_PIN_CFG(0x0, 0x05, 0x90170010), + AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e), + AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0), + AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c new file mode 100644 index 0000000..e6f8258 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(struct device *const dev) + { + printk(BIOS_DEBUG, "Vostro3360: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + } + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/39688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e9b7b7c333de644d8db0fbe787d915891b8467 Gerrit-Change-Number: 39688 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002723 Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: [WIP]soc/intel/cfl: Try to enable Intel DCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39692 ) Change subject: [WIP]soc/intel/cfl: Try to enable Intel DCI ...................................................................... [WIP]soc/intel/cfl: Try to enable Intel DCI Enable DCI using P2SB interface as documented in Document Number: 332691-003EN "Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub (PCH) Vol2" Enable CPU debugging using MSR IA32_DEBUG_INTERFACE. Intel DCI needs hardware support and doesn't work on every mainboard. Tested: Doesn't work. Change-Id: I2c8bf7e82116bc44430f4be4498f2e445f904886 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h M src/include/cpu/x86/msr.h M src/soc/intel/cannonlake/bootblock/cpu.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pcr_ids.h 6 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39692/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index e149c38..d27fcc4 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -151,6 +151,7 @@ #define X86_VENDOR_UNKNOWN 0xff #define CPUID_FEATURE_PAE (1 << 6) +#define CPUID_FEAURE_SDBG (1 << 11) #define CPUID_FEATURE_PSE36 (1 << 17) #define CPUID_FEAURE_HTT (1 << 28) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc0..24e689f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -84,6 +84,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_DEBUG_INTERFACE 0xc80 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 0523aa0..1f0fdfd 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -15,6 +15,8 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <soc/bootblock.h> +#include <cpu/x86/msr.h> +#include <arch/cpu.h> void bootblock_cpu_init(void) { @@ -22,4 +24,13 @@ if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); + /* + * Enable processor debugging features. See Intel 64 and IA-32 Architectures SDM + * Document 326019-060US, Table 35-2 + */ + if (CONFIG(SOC_INTEL_DEBUG_CONSENT) && + (cpu_get_feature_flags_ecx() & CPUID_FEAURE_SDBG)) { + msr_t msr = {.lo = 1, .hi = 0}; + wrmsr(IA32_DEBUG_INTERFACE, msr); + } } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 7cff74b..6a94996 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -55,6 +55,9 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +#define PCR_DCI_ECTRL 0x4 +#define PCR_DCI_HDCIEN (1 << 4) + static uint32_t get_pmc_reg_base(void) { uint8_t pch_series; @@ -94,6 +97,21 @@ write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); } +static void pch_enable_dci(bool enable) +{ + /* + * Enable Intel DCI. See Intel + * Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub + * (PCH), Chapter 31.3.1 + */ + uint32_t dci_control = pcr_read32(PID_DCI, PCR_DCI_ECTRL); + if (enable) + dci_control |= PCR_DCI_HDCIEN; + else + dci_control &= ~PCR_DCI_HDCIEN; + pcr_write32(PID_DCI, PCR_DCI_ECTRL, dci_control); +} + void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); @@ -196,4 +214,6 @@ /* GPIO community PM configuration */ soc_gpio_pm_configuration(); + + pch_enable_dci(CONFIG(SOC_INTEL_DEBUG_CONSENT)); } diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4634806..ca2094a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -296,6 +296,8 @@ if (dev) { if (!xdci_can_enable()) dev->enabled = 0; + if (CONFIG(SOC_INTEL_DEBUG_CONSENT)) + dev->enabled = 1; params->XdciEnable = dev->enabled; } else params->XdciEnable = 0; diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index 99c37bc..d87d562 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -28,6 +28,7 @@ #define PID_PSTH 0x89 #define PID_CSME0 0x90 #define PID_ISCLK 0xad +#define PID_DCI 0xb8 #define PID_PSF1 0xba #define PID_PSF2 0xbb #define PID_PSF3 0xbc -- To view, visit https://review.coreboot.org/c/coreboot/+/39692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c8bf7e82116bc44430f4be4498f2e445f904886 Gerrit-Change-Number: 39692 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/edid: Drop bytes_per_line
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39773 ) Change subject: lib/edid: Drop bytes_per_line ...................................................................... lib/edid: Drop bytes_per_line There where only two users of this field, but in both cases incorrectly implemented, as there was either no producer or no consumer. Remove it as the same information is now be passed directly to the framebuffer info storage and thus it's no longer needed. Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/lib/edid.c M src/northbridge/intel/i945/gma.c 4 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39773/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 8091802..4b57308 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -224,13 +224,12 @@ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; - edid.bytes_per_line = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); /* Updated framebuffer info for ast_crtc_mode_set */ - fb.pitches[0] = edid.bytes_per_line; + fb.pitches[0] = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d @ %d BPP\n", - edid.x_resolution, edid.y_resolution, edid.bytes_per_line, + edid.x_resolution, edid.y_resolution, fb.pitches[0], edid.framebuffer_bits_per_pixel); /* Convert EDID to AST DRM mode */ @@ -250,7 +249,7 @@ fb_add_framebuffer_info_from_edid(&edid, fb.mmio_addr, 8); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)fb.mmio_addr, 0, fb.pitches[0] * edid.y_resolution); return 0; } diff --git a/src/include/edid.h b/src/include/edid.h index 02afae7..9733b0c 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -83,14 +83,13 @@ struct edid_mode mode; u8 mode_is_supported[NUM_KNOWN_MODES]; unsigned int link_clock; - /* 3 variables needed for coreboot framebuffer. + /* 2 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha * and va variables, but not always, as in the * case of a 1366 wide display. */ u32 x_resolution; u32 y_resolution; - u32 bytes_per_line; int hdmi_monitor_detected; char ascii_string[EDID_ASCII_STRING_LENGTH + 1]; diff --git a/src/lib/edid.c b/src/lib/edid.c index 048cc6a..473fc1b 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1689,13 +1689,15 @@ void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment) { + uint32_t bytes_per_line; + /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); row_byte_alignment = MAX(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; - edid->bytes_per_line = ALIGN_UP(edid->mode.ha * + bytes_per_line = ALIGN_UP(edid->mode.ha * DIV_ROUND_UP(fb_bpp, 8), row_byte_alignment); - edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); + edid->x_resolution = bytes_per_line / (fb_bpp / 8); edid->y_resolution = edid->mode.va; } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1b1a1bf..078ab74 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -108,6 +108,7 @@ unsigned long temp; int hpolarity, vpolarity; u32 smallest_err = 0xffffffff; + u32 bytes_per_line; u32 target_frequency; u32 pixel_p1 = 1; u32 pixel_p2; @@ -314,10 +315,11 @@ write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(mmiobase + DSPPOS(0), 0); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + bytes_per_line = DIV_ROUND_UP(hactive * 32 / 8, 64); + write32(mmiobase + DSPADDR(0), 0); write32(mmiobase + DSPSURF(0), 0); - write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmiobase + DSPSTRIDE(0), bytes_per_line); write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/39773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Gerrit-Change-Number: 39773 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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