coreboot-gerrit April 2020

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Change in coreboot[master]: vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig
by Joel Kitching (Code Review) 07 Aug '23

07 Aug '23

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39342 ) Change subject: vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig ...................................................................... vboot: remove VBOOT_NO_BOARD_SUPPORT Kconfig Just make the implementation in bootmode.c __weak like the other functions related to recovery switch. Boards may still enable vboot without implementing this function. Kconfig was originally added in CB:22102. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iccef100fac1d71625039990373e40b29d52a0167 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/mistral/Kconfig M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/up/squared/Kconfig M src/security/vboot/Kconfig M src/security/vboot/bootmode.c 24 files changed, 21 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/39342/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c27b1e..f9d7a67 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -19,7 +19,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ee430d0..becfefe 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -18,7 +18,6 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 745f084..829ccef 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -33,15 +33,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get_value(GPIO_Y10); // RECMODE_GPIO } +#endif diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 05d9e86..ca01fe2 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -32,16 +32,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ -#if CONFIG(EC_GOOGLE_CHROMEEC) - uint64_t ec_events; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -#else - return 0; -#endif -} diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index b7d0d31..2db1fcb 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -17,7 +17,6 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_MOCK_SECDATA - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_FORCE_DEV_SWITCH_ON config MAINBOARD_DIR diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index a82f50f..9b2d8c5 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -33,15 +33,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get_value(GPIO_X07); // RECMODE_GPIO } +#endif diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index e14e2e5..42aba05 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -52,15 +52,10 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +#if !CONFIG(EC_GOOGLE_CHROMEEC) int get_recovery_mode_switch(void) { - uint64_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get(GPIO_RECOVERY)) - return 1; - - ec_events = google_chromeec_get_events_b(); - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return !!gpio_get(GPIO_RECOVERY); } +#endif diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index 8f28baf..50faf7e 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -20,7 +20,6 @@ config VBOOT select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 5020e9b..62e4137 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -33,13 +33,8 @@ int get_lid_switch(void) { - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; + /* Lid always open */ + return 1; } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 0933fe6..c1bc404 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -36,11 +36,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index fda7431..4f66b5d 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -24,11 +24,6 @@ #include "gen1.h" #include "gen2.h" -int get_recovery_mode_switch(void) -{ - return 0; -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 0882e88..1e5dd99 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -36,11 +36,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 6ad0b39..3da8971 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -35,11 +35,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 6ad0b39..3da8971 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -35,11 +35,6 @@ return 1; } -int get_recovery_mode_switch(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 16ea993..8a4956d 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -19,9 +19,6 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* Compile-time settings for recovery mode. */ -#define REC_MODE_SETTING 0 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,11 +29,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_recovery_mode_switch(void) -{ - return REC_MODE_SETTING; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig index 3ba2a60..781b668 100644 --- a/src/mainboard/opencellular/elgon/Kconfig +++ b/src/mainboard/opencellular/elgon/Kconfig @@ -28,7 +28,6 @@ select MISSING_BOARD_RESET config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 6adf4e9..2701046 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -16,7 +16,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index b10bdc8..7799d34 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index e46a0de..52afba5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -19,7 +19,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 864e808..bba2501 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -15,7 +15,6 @@ config VBOOT select VBOOT_MEASURED_BOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index e0f468c..0111115 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -41,7 +41,6 @@ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index 5db76fd..41bb3d3 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -17,7 +17,6 @@ select HAVE_INTEL_PTT config VBOOT - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 6ffb065..d9ccb75 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -216,14 +216,6 @@ This is the second part of the FWID written to various regions of a vboot firmware image to identify its version. -config VBOOT_NO_BOARD_SUPPORT - bool "Allow the use of vboot without board support" - default n - help - Enable weak function for get_recovery_mode_switch in order to - proceed with refactoring of the vboot2 code base. Later on this - code is removed and replaced by interfaces. - config RO_REGION_ONLY string "Additional files that should not be copied to RW" default "" diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 78c4320..55c1e79 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -42,6 +42,16 @@ return vboot_get_context()->flags & VB2_CONTEXT_DEVELOPER_MODE; } +int __weak get_recovery_mode_switch(void) +{ + return 0; +} + +int __weak get_recovery_mode_retrain_switch(void) +{ + return 0; +} + int __weak clear_recovery_mode_switch(void) { return 0; @@ -66,20 +76,7 @@ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, do_clear_recovery_mode_switch, NULL); -int __weak get_recovery_mode_retrain_switch(void) -{ - return 0; -} - int vboot_recovery_mode_memory_retrain(void) { return get_recovery_mode_retrain_switch(); } - -#if CONFIG(VBOOT_NO_BOARD_SUPPORT) -int __weak get_recovery_mode_switch(void) -{ - return 0; -} - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccef100fac1d71625039990373e40b29d52a0167 Gerrit-Change-Number: 39342 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: amd/agesa/hudson: Disable `isa_dma_init()`
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39377 ) Change subject: amd/agesa/hudson: Disable `isa_dma_init()` ...................................................................... amd/agesa/hudson: Disable `isa_dma_init()` coreboot on the ASUS F2A85-M PRO hangs there. After removing it, it runs through. SeaBIOS also hangs reading CBFS, but GRUB works fine. So it looks like, it’s needed for some legacy stuff. Change-Id: I7f581606f9f234cfb7a3fec2cc7f4172589f8153 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39377/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9c65d04..251ddd1 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -44,9 +43,6 @@ dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); - /* Initialize isa dma */ - isa_dma_init(); - /* Enable DMA transaction on the LPC bus */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); -- To view, visit https://review.coreboot.org/c/coreboot/+/39377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f581606f9f234cfb7a3fec2cc7f4172589f8153 Gerrit-Change-Number: 39377 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: new local repo and the point where I am now with vostro 3360
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39688 ) Change subject: new local repo and the point where I am now with vostro 3360 ...................................................................... new local repo and the point where I am now with vostro 3360 Change-Id: I82e9b7b7c333de644d8db0fbe787d915891b8467 --- A grub.cfg A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Kconfig A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c A src/mainboard/dell/dell_system_vostro_3360/board_info.txt A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl A src/mainboard/dell/dell_system_vostro_3360/early_init.c A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads A src/mainboard/dell/dell_system_vostro_3360/gpio.c A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c A src/mainboard/dell/dell_system_vostro_3360/mainboard.c 18 files changed, 718 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/39688/1 diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 0000000..2ad31ee --- /dev/null +++ b/grub.cfg @@ -0,0 +1,3 @@ +configfile (ahci0,3)/boot/grub/grub.cfg +terminal_output --append cbmemc +set debug=atkeyb diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig new file mode 100644 index 0000000..dfcc0e1 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig @@ -0,0 +1,43 @@ +if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select GFX_GMA_PANEL_1_ON_LVDS + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default dell/dell_system_vostro_3360 + +config MAINBOARD_PART_NUMBER + string + default "Dell System Vostro 3360" + +config VGA_BIOS_FILE + string + default "pci8086,0156.rom" + +config VGA_BIOS_ID + string + default "8086,0156" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name new file mode 100644 index 0000000..8925217 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + bool "Dell System Vostro 3360" diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl new file mode 100644 index 0000000..a9177df --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl @@ -0,0 +1 @@ +#include<drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl new file mode 100644 index 0000000..552fb6c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c new file mode 100644 index 0000000..cfc2061 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb new file mode 100644 index 0000000..d234325 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "1700" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00040911" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1028 0x055c + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x055c + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x055c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x055c + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x055c + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x055c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x055c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x055c + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x055c + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x055c + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1028 0x055c + end + end +end diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl new file mode 100644 index 0000000..98c2ad4 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c new file mode 100644 index 0000000..6dbf226 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 0, 1, 3 }, + { 0, 1, 3 }, + { 1, 1, 4 }, + { 0, 1, 4 }, + { 1, 1, 5 }, + { 0, 1, 5 }, + { 1, 1, 6 }, + { 0, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads new file mode 100644 index 0000000..6cb572a --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c new file mode 100644 index 0000000..d7db210 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c new file mode 100644 index 0000000..c55bf3c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134213, /* Codec Vendor / Device ID: Cirrus */ + 0x1028055c, /* Subsystem ID */ + 6, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x1028055c), + AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f), + AZALIA_PIN_CFG(0x0, 0x05, 0x90170010), + AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e), + AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0), + AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c new file mode 100644 index 0000000..e6f8258 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(struct device *const dev) + { + printk(BIOS_DEBUG, "Vostro3360: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); + } + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/39688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e9b7b7c333de644d8db0fbe787d915891b8467 Gerrit-Change-Number: 39688 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002723 Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/cfl: Try to enable Intel DCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39692 ) Change subject: [WIP]soc/intel/cfl: Try to enable Intel DCI ...................................................................... [WIP]soc/intel/cfl: Try to enable Intel DCI Enable DCI using P2SB interface as documented in Document Number: 332691-003EN "Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub (PCH) Vol2" Enable CPU debugging using MSR IA32_DEBUG_INTERFACE. Intel DCI needs hardware support and doesn't work on every mainboard. Tested: Doesn't work. Change-Id: I2c8bf7e82116bc44430f4be4498f2e445f904886 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h M src/include/cpu/x86/msr.h M src/soc/intel/cannonlake/bootblock/cpu.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pcr_ids.h 6 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39692/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index e149c38..d27fcc4 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -151,6 +151,7 @@ #define X86_VENDOR_UNKNOWN 0xff #define CPUID_FEATURE_PAE (1 << 6) +#define CPUID_FEAURE_SDBG (1 << 11) #define CPUID_FEATURE_PSE36 (1 << 17) #define CPUID_FEAURE_HTT (1 << 28) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc0..24e689f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -84,6 +84,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_DEBUG_INTERFACE 0xc80 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index 0523aa0..1f0fdfd 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -15,6 +15,8 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <soc/bootblock.h> +#include <cpu/x86/msr.h> +#include <arch/cpu.h> void bootblock_cpu_init(void) { @@ -22,4 +24,13 @@ if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); + /* + * Enable processor debugging features. See Intel 64 and IA-32 Architectures SDM + * Document 326019-060US, Table 35-2 + */ + if (CONFIG(SOC_INTEL_DEBUG_CONSENT) && + (cpu_get_feature_flags_ecx() & CPUID_FEAURE_SDBG)) { + msr_t msr = {.lo = 1, .hi = 0}; + wrmsr(IA32_DEBUG_INTERFACE, msr); + } } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 7cff74b..6a94996 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -55,6 +55,9 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +#define PCR_DCI_ECTRL 0x4 +#define PCR_DCI_HDCIEN (1 << 4) + static uint32_t get_pmc_reg_base(void) { uint8_t pch_series; @@ -94,6 +97,21 @@ write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); } +static void pch_enable_dci(bool enable) +{ + /* + * Enable Intel DCI. See Intel + * Intel 100 Series and Intel C230 Series Chipset Family Platform Controller Hub + * (PCH), Chapter 31.3.1 + */ + uint32_t dci_control = pcr_read32(PID_DCI, PCR_DCI_ECTRL); + if (enable) + dci_control |= PCR_DCI_HDCIEN; + else + dci_control &= ~PCR_DCI_HDCIEN; + pcr_write32(PID_DCI, PCR_DCI_ECTRL, dci_control); +} + void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); @@ -196,4 +214,6 @@ /* GPIO community PM configuration */ soc_gpio_pm_configuration(); + + pch_enable_dci(CONFIG(SOC_INTEL_DEBUG_CONSENT)); } diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4634806..ca2094a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -296,6 +296,8 @@ if (dev) { if (!xdci_can_enable()) dev->enabled = 0; + if (CONFIG(SOC_INTEL_DEBUG_CONSENT)) + dev->enabled = 1; params->XdciEnable = dev->enabled; } else params->XdciEnable = 0; diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index 99c37bc..d87d562 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -28,6 +28,7 @@ #define PID_PSTH 0x89 #define PID_CSME0 0x90 #define PID_ISCLK 0xad +#define PID_DCI 0xb8 #define PID_PSF1 0xba #define PID_PSF2 0xbb #define PID_PSF3 0xbc -- To view, visit https://review.coreboot.org/c/coreboot/+/39692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c8bf7e82116bc44430f4be4498f2e445f904886 Gerrit-Change-Number: 39692 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/edid: Drop bytes_per_line
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39773 ) Change subject: lib/edid: Drop bytes_per_line ...................................................................... lib/edid: Drop bytes_per_line There where only two users of this field, but in both cases incorrectly implemented, as there was either no producer or no consumer. Remove it as the same information is now be passed directly to the framebuffer info storage and thus it's no longer needed. Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/include/edid.h M src/lib/edid.c M src/northbridge/intel/i945/gma.c 4 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39773/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 8091802..4b57308 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -224,13 +224,12 @@ edid.x_resolution = edid.mode.ha; edid.y_resolution = edid.mode.va; edid.framebuffer_bits_per_pixel = format.cpp[0] * 8; - edid.bytes_per_line = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); /* Updated framebuffer info for ast_crtc_mode_set */ - fb.pitches[0] = edid.bytes_per_line; + fb.pitches[0] = ALIGN_UP(edid.x_resolution * format.cpp[0], 8); printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d @ %d BPP\n", - edid.x_resolution, edid.y_resolution, edid.bytes_per_line, + edid.x_resolution, edid.y_resolution, fb.pitches[0], edid.framebuffer_bits_per_pixel); /* Convert EDID to AST DRM mode */ @@ -250,7 +249,7 @@ fb_add_framebuffer_info_from_edid(&edid, fb.mmio_addr, 8); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)fb.mmio_addr, 0, fb.pitches[0] * edid.y_resolution); return 0; } diff --git a/src/include/edid.h b/src/include/edid.h index 02afae7..9733b0c 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -83,14 +83,13 @@ struct edid_mode mode; u8 mode_is_supported[NUM_KNOWN_MODES]; unsigned int link_clock; - /* 3 variables needed for coreboot framebuffer. + /* 2 variables needed for coreboot framebuffer. * In most cases, they are the same as the ha * and va variables, but not always, as in the * case of a 1366 wide display. */ u32 x_resolution; u32 y_resolution; - u32 bytes_per_line; int hdmi_monitor_detected; char ascii_string[EDID_ASCII_STRING_LENGTH + 1]; diff --git a/src/lib/edid.c b/src/lib/edid.c index 048cc6a..473fc1b 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1689,13 +1689,15 @@ void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment) { + uint32_t bytes_per_line; + /* Caller should pass a supported value, everything else is BUG(). */ assert(fb_bpp == 32 || fb_bpp == 24 || fb_bpp == 16); row_byte_alignment = MAX(row_byte_alignment, 1); edid->framebuffer_bits_per_pixel = fb_bpp; - edid->bytes_per_line = ALIGN_UP(edid->mode.ha * + bytes_per_line = ALIGN_UP(edid->mode.ha * DIV_ROUND_UP(fb_bpp, 8), row_byte_alignment); - edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8); + edid->x_resolution = bytes_per_line / (fb_bpp / 8); edid->y_resolution = edid->mode.va; } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1b1a1bf..078ab74 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -108,6 +108,7 @@ unsigned long temp; int hpolarity, vpolarity; u32 smallest_err = 0xffffffff; + u32 bytes_per_line; u32 target_frequency; u32 pixel_p1 = 1; u32 pixel_p2; @@ -314,10 +315,11 @@ write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(mmiobase + DSPPOS(0), 0); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + bytes_per_line = DIV_ROUND_UP(hactive * 32 / 8, 64); + write32(mmiobase + DSPADDR(0), 0); write32(mmiobase + DSPSURF(0), 0); - write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmiobase + DSPSTRIDE(0), bytes_per_line); write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/39773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I898a9a36d7fa9b3529661dacd56c1adfacb606cd Gerrit-Change-Number: 39773 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK sc7180: BL31 config change to 3MB in memlayout HACK
by Manideep Kurumella (Code Review) 07 Aug '23

07 Aug '23

Manideep Kurumella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39858 ) Change subject: HACK sc7180: BL31 config change to 3MB in memlayout HACK ...................................................................... HACK sc7180: BL31 config change to 3MB in memlayout HACK Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39858/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 67a372a..c8a9232 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -62,8 +62,8 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x300000, 0x1000) - BL31(0x80C00000, 2M) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 3M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/39858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f Gerrit-Change-Number: 39858 Gerrit-PatchSet: 1 Gerrit-Owner: Manideep Kurumella <mkurumel(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40203 ) Change subject: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB ...................................................................... mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 8.720370] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input2 [ 8.729081] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device (gigabyte/ga-945gcm-s2l, intel/d945gclf).. Fixes: 6390e525 ("mb/asus/p5gc-mx: Add mainboard") Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/p5gc-mx/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40203/1 diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl index 5187b2a..bb86c6c 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -12,14 +12,6 @@ * GNU General Public License for more details. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Gerrit-Change-Number: 40203 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/acpi: Increase Max PCI bus count support
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40335 ) Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ...................................................................... src/arch/x86/acpi: Increase Max PCI bus count support This patch increase maximum bus end variable type to match latest SoC specification [Ice Lake EDS vol 1 chapter 3.18] Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40335/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6eded1d..ccc24db 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -104,7 +104,7 @@ } int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) + u16 seg_nr, u8 start, u16 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 644f52f..82faa8f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -871,7 +871,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u16 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -- To view, visit https://review.coreboot.org/c/coreboot/+/40335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Gerrit-Change-Number: 40335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86/smm: add mainboard intruder detection SMI handler prototype
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40341 ) Change subject: x86/smm: add mainboard intruder detection SMI handler prototype ...................................................................... x86/smm: add mainboard intruder detection SMI handler prototype Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 --- M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40341/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3169ace..eff512f 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -191,3 +191,4 @@ void __weak mainboard_smi_gpi(u32 gpi_sts) {} int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} +void __weak mainboard_smi_intruder(u32 tco_sts) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 0b76708..7a78268 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -44,6 +44,7 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); +void mainboard_smi_intruder(u32 tco_sts); /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/40341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 Gerrit-Change-Number: 40341 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/elog: add event log parsing tables
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40343 ) Change subject: commonlib/elog: add event log parsing tables ...................................................................... commonlib/elog: add event log parsing tables Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda --- A src/commonlib/include/commonlib/elog.h 1 file changed, 402 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40343/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9034579 --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#include <stdint.h> + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +struct elog_event_name { + uint8_t event_type; + char *event_name; +}; + +static const struct elog_event_name elog_event_to_name[] = { + { ELOG_TYPE_UNDEFINED_EVENT, "UNDEFINED EVENT" }, + { ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR, "Single-Bit ECC memory error" }, + { ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR, "Multi-Bit ECC memory error" }, + { ELOG_TYPE_MEM_PARITY_ERR, "Memory parity error" }, + { ELOG_TYPE_BUS_TIMEOUT, "Bus time-out" }, + { ELOG_TYPE_IO_CHECK, "IO channel check" }, + { ELOG_TYPE_SW_NMI, "Software NMI" }, + { ELOG_TYPE_POST_MEM_RESIZE, "Post memory resize" }, + { ELOG_TYPE_POST_ERR, "Post error" }, + { ELOG_TYPE_PCI_PERR, "PCI parity error" }, + { ELOG_TYPE_PCI_SERR, "PCI system error" }, + { ELOG_TYPE_CPU_FAIL, "CPU failure" }, + { ELOG_TYPE_EISA_TIMEOUT, "EISA FailSafe Timer time-out" }, + { ELOG_TYPE_CORRECTABLE_MEMLOG_DIS, "Correctable memory log disable" }, + { ELOG_TYPE_LOG_DISABLED, "Event log disabled for type" }, + { ELOG_TYPE_UNDEFINED_EVENT2, "UNDEFINED EVENT 2" }, + { ELOG_TYPE_SYS_LIMIT_EXCEED, "System limit exceeded" }, + { ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED, "Asynchronous hardware timer expired and issued a system reset" }, + { ELOG_TYPE_SYS_CONFIG_INFO, "System configuration information" }, + { ELOG_TYPE_HDD_INFO, "Hard-disk information" }, + { ELOG_TYPE_SYS_RECONFIG, "System reconfigured" }, + { ELOG_TYPE_CPU_ERROR, "Uncorrectable CPU-complex error" }, + { ELOG_TYPE_LOG_CLEAR, "Log Area reset/cleared" }, + { ELOG_TYPE_BOOT, "System boot" }, + { ELOG_TYPE_OS_EVENT, "Operating system event" }, + { ELOG_TYPE_OS_BOOT, "Boot operating system" }, + { ELOG_TYPE_POWER_FAIL, "Power failure" }, + { ELOG_TYPE_SUS_POWER_FAIL, "Suspend power failure" }, + { ELOG_TYPE_PWROK_FAIL, "Power OK failure" }, + { ELOG_TYPE_SYS_PWROK_FAIL, "System power OK failure" }, + { ELOG_TYPE_POWER_ON, "Power on" }, + { ELOG_TYPE_POWER_BUTTON, "Power button pressed" }, + { ELOG_TYPE_POWER_BUTTON_OVERRIDE, "Power button override" }, + { ELOG_TYPE_RESET_BUTTON, "Reset button pressed" }, + { ELOG_TYPE_SYSTEM_RESET, "System reset" }, + { ELOG_TYPE_RTC_RESET, "Real Time Clock reset" }, + { ELOG_TYPE_TCO_RESET, "TCO timer reset" }, + { ELOG_TYPE_ACPI_ENTER, "Entered ACPI state" }, + { ELOG_TYPE_ACPI_WAKE, "ACPI wake event" }, + { ELOG_TYPE_WAKE_SOURCE, "ACPI wake source" }, + { ELOG_TYPE_CROS_DEVELOPER_MODE, "Entered ChromeOS developer mode" }, + { ELOG_TYPE_CROS_RECOVERY_MODE, "Entered ChromeOS recovery mode" }, + { ELOG_TYPE_MANAGEMENT_ENGINE, "Intel Management Engine event" }, + { ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Intel Management Engine extended event" }, + { ELOG_TYPE_LAST_POST_CODE, "Post code from last boot" }, + { ELOG_TYPE_POST_EXTRA, "Post code extra" }, + { ELOG_TYPE_EC_SHUTDOWN, "Embedded Controller shutdown" }, + { ELOG_TYPE_SLEEP, "Entered sleep mode", }, + { ELOG_TYPE_WAKE, "Wake event" }, + { ELOG_TYPE_FW_WAKE, "Firmware wake event" }, + { ELOG_TYPE_MEM_CACHE_UPDATE, "MRC cache update" }, + { ELOG_TYPE_THERM_TRIP, "Thermal trip occurred" }, + { ELOG_TYPE_CR50_UPDATE, "CR50 TPM update event" }, + { ELOG_TYPE_ACPI_DEEP_WAKE, "ACPI deep wake event" }, + { ELOG_TYPE_EC_DEVICE_EVENT, "Embedded controller device event" }, + { ELOG_TYPE_S0IX_ENTER, "Entered S0ix state" }, + { ELOG_TYPE_S0IX_EXIT, "Exited from S0ix state" }, + { ELOG_TYPE_EXTENDED_EVENT, "Extended event" }, + { ELOG_TYPE_CR50_NEED_RESET, "CR50 TPM configuration needs reset" }, + { ELOG_TYPE_INTRUDER_DETECTION, "Intrusion detection " } +}; + +static const struct elog_event_name elog_ec_event_to_name[] = { + { EC_EVENT_LID_CLOSED, "Lid closed" }, + { EC_EVENT_LID_OPEN, "Lid open" }, + { EC_EVENT_POWER_BUTTON, "Power button pressed" }, + { EC_EVENT_AC_CONNECTED, "AC power supply connected" }, + { EC_EVENT_AC_DISCONNECTED, "AC power supply disconnected" }, + { EC_EVENT_BATTERY_LOW, "Battery low" }, + { EC_EVENT_BATTERY_CRITICAL, "Battery critical" }, + { EC_EVENT_BATTERY, "Battery event" }, + { EC_EVENT_THERMAL_THRESHOLD, "Thermal threshold reached" }, + { EC_EVENT_DEVICE_EVENT, "Device event" }, + { EC_EVENT_THERMAL, "Thermal event" }, + { EC_EVENT_USB_CHARGER, "USB charger" }, + { EC_EVENT_KEY_PRESSED, "Key pressed" }, + { EC_EVENT_INTERFACE_READY, "Interface ready" }, + { EC_EVENT_KEYBOARD_RECOVERY, "Keyboard recovery" }, + { EC_EVENT_THERMAL_SHUTDOWN, "Thermal shutdown" }, + { EC_EVENT_BATTERY_SHUTDOWN, "Battery shutdown" }, + { EC_EVENT_FAN_ERROR, "Fan error" }, + { EC_EVENT_THROTTLE_STOP, "Throttling stopeed" }, + { EC_EVENT_HANG_DETECT, "Hang detected" }, + { EC_EVENT_HANG_REBOOT, "Reboot hang" }, + { EC_EVENT_PD_MCU, "PD processor" }, + { EC_EVENT_BATTERY_STATUS, "Battery status" }, + { EC_EVENT_PANIC, "Panic" }, + { EC_EVENT_KEYBOARD_FASTBOOT, "Keyboard fastboot" }, + { EC_EVENT_RTC, "Real Time Clock" }, + { EC_EVENT_MKBP, "Matrix Keyboard Protocol" }, + { EC_EVENT_USB_MUX, "USB multiplexer" }, + { EC_EVENT_MODE_CHANGE, "Mode change" }, + { EC_EVENT_KEYBOARD_RECOVERY_HWREINIT, "Keyboard recovery hardware reinitialization" }, + { EC_EVENT_EXTENDED, "Extended event" } +}; + +static const struct elog_event_name elog_wake_event_to_name[] = { + { ELOG_WAKE_SOURCE_PCIE, "PCI Express" }, + { ELOG_WAKE_SOURCE_PME, "PME" }, + { ELOG_WAKE_SOURCE_PME_INTERNAL, "Internal PME" }, + { ELOG_WAKE_SOURCE_RTC, "Real Time Clock" }, + { ELOG_WAKE_SOURCE_GPIO, "GPIO" }, + { ELOG_WAKE_SOURCE_SMBUS, "SMBus" }, + { ELOG_WAKE_SOURCE_PWRBTN, "Power Button" }, + { ELOG_WAKE_SOURCE_PME_HDA, "HD Audio PME" }, + { ELOG_WAKE_SOURCE_PME_GBE, "Gigabit Ethernet PME" }, + { ELOG_WAKE_SOURCE_PME_EMMC, "Embedded MMC PME" }, + { ELOG_WAKE_SOURCE_PME_SDCARD, "SD card PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE1, "PCI Express 1 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE2, "PCI Express 2 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE3, "PCI Express 3 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE4, "PCI Express 4 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE5, "PCI Express 5 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE6, "PCI Express 6 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE7, "PCI Express 7 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE8, "PCI Express 8 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE9, "PCI Express 9 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, + { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, + { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, + { ELOG_WAKE_SOURCE_PME_CSE3, "CSE 3 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI, "xHCI PME" }, + { ELOG_WAKE_SOURCE_PME_XDCI, "xDCI PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_2, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_3, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_WIFI, "WiFi PME" } +}; + +static const struct elog_event_name elog_ec_device_event_to_name[] = { + { ELOG_EC_DEVICE_EVENT_TRACKPAD, "Trackpad" }, + { ELOG_EC_DEVICE_EVENT_DSP, "DSP" }, + { ELOG_EC_DEVICE_EVENT_WIFI, "WiFi" } +}; + +static const struct elog_event_name mrc_upd_slots[] = { + { ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, "NORMAL" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, "RECOVERY" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, "VARIABLE" } +}; + +static const char *const me_bios_paths[] = { + "ME normal BIOS path", + "ME S3 wake BIOS path", + "ME error BIOS path", + "ME recovery BIOS path", + "ME disable BIOS path", + "ME firmware update BIOS path", +}; + +#endif /* ELOG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda Gerrit-Change-Number: 40343 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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