coreboot-gerrit April 2020

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Change in coreboot[master]: HACK sc7180: BL31 config change to 3MB in memlayout HACK
by Manideep Kurumella (Code Review) 07 Aug '23

07 Aug '23

Manideep Kurumella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39858 ) Change subject: HACK sc7180: BL31 config change to 3MB in memlayout HACK ...................................................................... HACK sc7180: BL31 config change to 3MB in memlayout HACK Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39858/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 67a372a..c8a9232 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -62,8 +62,8 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x300000, 0x1000) - BL31(0x80C00000, 2M) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 3M) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/39858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied204c63a8cf4055cb429e4e5e1dfa2cdccc734f Gerrit-Change-Number: 39858 Gerrit-PatchSet: 1 Gerrit-Owner: Manideep Kurumella <mkurumel(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40203 ) Change subject: mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB ...................................................................... mb/asus/p5gc-mx: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 8.720370] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input2 [ 8.729081] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device (gigabyte/ga-945gcm-s2l, intel/d945gclf).. Fixes: 6390e525 ("mb/asus/p5gc-mx: Add mainboard") Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/p5gc-mx/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40203/1 diff --git a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl index 5187b2a..bb86c6c 100644 --- a/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl +++ b/src/mainboard/asus/p5gc-mx/acpi/mainboard.asl @@ -12,14 +12,6 @@ * GNU General Public License for more details. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2dbeb9238cbfe41f0f46f473000ac3629250fda Gerrit-Change-Number: 40203 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/arch/x86/acpi: Increase Max PCI bus count support
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40335 ) Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ...................................................................... src/arch/x86/acpi: Increase Max PCI bus count support This patch increase maximum bus end variable type to match latest SoC specification [Ice Lake EDS vol 1 chapter 3.18] Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40335/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6eded1d..ccc24db 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -104,7 +104,7 @@ } int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) + u16 seg_nr, u8 start, u16 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 644f52f..82faa8f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -871,7 +871,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u16 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -- To view, visit https://review.coreboot.org/c/coreboot/+/40335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Gerrit-Change-Number: 40335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: x86/smm: add mainboard intruder detection SMI handler prototype
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40341 ) Change subject: x86/smm: add mainboard intruder detection SMI handler prototype ...................................................................... x86/smm: add mainboard intruder detection SMI handler prototype Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 --- M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/40341/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 3169ace..eff512f 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -191,3 +191,4 @@ void __weak mainboard_smi_gpi(u32 gpi_sts) {} int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} +void __weak mainboard_smi_intruder(u32 tco_sts) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 0b76708..7a78268 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -44,6 +44,7 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); +void mainboard_smi_intruder(u32 tco_sts); /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; -- To view, visit https://review.coreboot.org/c/coreboot/+/40341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60d834e99dd7f4ed90b86fbc3590e1d5fb1be821 Gerrit-Change-Number: 40341 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/elog: add event log parsing tables
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40343 ) Change subject: commonlib/elog: add event log parsing tables ...................................................................... commonlib/elog: add event log parsing tables Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda --- A src/commonlib/include/commonlib/elog.h 1 file changed, 402 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/40343/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9034579 --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,402 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef ELOG_H_ +#define ELOG_H_ + +#include <stdint.h> + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +struct elog_event_name { + uint8_t event_type; + char *event_name; +}; + +static const struct elog_event_name elog_event_to_name[] = { + { ELOG_TYPE_UNDEFINED_EVENT, "UNDEFINED EVENT" }, + { ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR, "Single-Bit ECC memory error" }, + { ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR, "Multi-Bit ECC memory error" }, + { ELOG_TYPE_MEM_PARITY_ERR, "Memory parity error" }, + { ELOG_TYPE_BUS_TIMEOUT, "Bus time-out" }, + { ELOG_TYPE_IO_CHECK, "IO channel check" }, + { ELOG_TYPE_SW_NMI, "Software NMI" }, + { ELOG_TYPE_POST_MEM_RESIZE, "Post memory resize" }, + { ELOG_TYPE_POST_ERR, "Post error" }, + { ELOG_TYPE_PCI_PERR, "PCI parity error" }, + { ELOG_TYPE_PCI_SERR, "PCI system error" }, + { ELOG_TYPE_CPU_FAIL, "CPU failure" }, + { ELOG_TYPE_EISA_TIMEOUT, "EISA FailSafe Timer time-out" }, + { ELOG_TYPE_CORRECTABLE_MEMLOG_DIS, "Correctable memory log disable" }, + { ELOG_TYPE_LOG_DISABLED, "Event log disabled for type" }, + { ELOG_TYPE_UNDEFINED_EVENT2, "UNDEFINED EVENT 2" }, + { ELOG_TYPE_SYS_LIMIT_EXCEED, "System limit exceeded" }, + { ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED, "Asynchronous hardware timer expired and issued a system reset" }, + { ELOG_TYPE_SYS_CONFIG_INFO, "System configuration information" }, + { ELOG_TYPE_HDD_INFO, "Hard-disk information" }, + { ELOG_TYPE_SYS_RECONFIG, "System reconfigured" }, + { ELOG_TYPE_CPU_ERROR, "Uncorrectable CPU-complex error" }, + { ELOG_TYPE_LOG_CLEAR, "Log Area reset/cleared" }, + { ELOG_TYPE_BOOT, "System boot" }, + { ELOG_TYPE_OS_EVENT, "Operating system event" }, + { ELOG_TYPE_OS_BOOT, "Boot operating system" }, + { ELOG_TYPE_POWER_FAIL, "Power failure" }, + { ELOG_TYPE_SUS_POWER_FAIL, "Suspend power failure" }, + { ELOG_TYPE_PWROK_FAIL, "Power OK failure" }, + { ELOG_TYPE_SYS_PWROK_FAIL, "System power OK failure" }, + { ELOG_TYPE_POWER_ON, "Power on" }, + { ELOG_TYPE_POWER_BUTTON, "Power button pressed" }, + { ELOG_TYPE_POWER_BUTTON_OVERRIDE, "Power button override" }, + { ELOG_TYPE_RESET_BUTTON, "Reset button pressed" }, + { ELOG_TYPE_SYSTEM_RESET, "System reset" }, + { ELOG_TYPE_RTC_RESET, "Real Time Clock reset" }, + { ELOG_TYPE_TCO_RESET, "TCO timer reset" }, + { ELOG_TYPE_ACPI_ENTER, "Entered ACPI state" }, + { ELOG_TYPE_ACPI_WAKE, "ACPI wake event" }, + { ELOG_TYPE_WAKE_SOURCE, "ACPI wake source" }, + { ELOG_TYPE_CROS_DEVELOPER_MODE, "Entered ChromeOS developer mode" }, + { ELOG_TYPE_CROS_RECOVERY_MODE, "Entered ChromeOS recovery mode" }, + { ELOG_TYPE_MANAGEMENT_ENGINE, "Intel Management Engine event" }, + { ELOG_TYPE_MANAGEMENT_ENGINE_EXT, "Intel Management Engine extended event" }, + { ELOG_TYPE_LAST_POST_CODE, "Post code from last boot" }, + { ELOG_TYPE_POST_EXTRA, "Post code extra" }, + { ELOG_TYPE_EC_SHUTDOWN, "Embedded Controller shutdown" }, + { ELOG_TYPE_SLEEP, "Entered sleep mode", }, + { ELOG_TYPE_WAKE, "Wake event" }, + { ELOG_TYPE_FW_WAKE, "Firmware wake event" }, + { ELOG_TYPE_MEM_CACHE_UPDATE, "MRC cache update" }, + { ELOG_TYPE_THERM_TRIP, "Thermal trip occurred" }, + { ELOG_TYPE_CR50_UPDATE, "CR50 TPM update event" }, + { ELOG_TYPE_ACPI_DEEP_WAKE, "ACPI deep wake event" }, + { ELOG_TYPE_EC_DEVICE_EVENT, "Embedded controller device event" }, + { ELOG_TYPE_S0IX_ENTER, "Entered S0ix state" }, + { ELOG_TYPE_S0IX_EXIT, "Exited from S0ix state" }, + { ELOG_TYPE_EXTENDED_EVENT, "Extended event" }, + { ELOG_TYPE_CR50_NEED_RESET, "CR50 TPM configuration needs reset" }, + { ELOG_TYPE_INTRUDER_DETECTION, "Intrusion detection " } +}; + +static const struct elog_event_name elog_ec_event_to_name[] = { + { EC_EVENT_LID_CLOSED, "Lid closed" }, + { EC_EVENT_LID_OPEN, "Lid open" }, + { EC_EVENT_POWER_BUTTON, "Power button pressed" }, + { EC_EVENT_AC_CONNECTED, "AC power supply connected" }, + { EC_EVENT_AC_DISCONNECTED, "AC power supply disconnected" }, + { EC_EVENT_BATTERY_LOW, "Battery low" }, + { EC_EVENT_BATTERY_CRITICAL, "Battery critical" }, + { EC_EVENT_BATTERY, "Battery event" }, + { EC_EVENT_THERMAL_THRESHOLD, "Thermal threshold reached" }, + { EC_EVENT_DEVICE_EVENT, "Device event" }, + { EC_EVENT_THERMAL, "Thermal event" }, + { EC_EVENT_USB_CHARGER, "USB charger" }, + { EC_EVENT_KEY_PRESSED, "Key pressed" }, + { EC_EVENT_INTERFACE_READY, "Interface ready" }, + { EC_EVENT_KEYBOARD_RECOVERY, "Keyboard recovery" }, + { EC_EVENT_THERMAL_SHUTDOWN, "Thermal shutdown" }, + { EC_EVENT_BATTERY_SHUTDOWN, "Battery shutdown" }, + { EC_EVENT_FAN_ERROR, "Fan error" }, + { EC_EVENT_THROTTLE_STOP, "Throttling stopeed" }, + { EC_EVENT_HANG_DETECT, "Hang detected" }, + { EC_EVENT_HANG_REBOOT, "Reboot hang" }, + { EC_EVENT_PD_MCU, "PD processor" }, + { EC_EVENT_BATTERY_STATUS, "Battery status" }, + { EC_EVENT_PANIC, "Panic" }, + { EC_EVENT_KEYBOARD_FASTBOOT, "Keyboard fastboot" }, + { EC_EVENT_RTC, "Real Time Clock" }, + { EC_EVENT_MKBP, "Matrix Keyboard Protocol" }, + { EC_EVENT_USB_MUX, "USB multiplexer" }, + { EC_EVENT_MODE_CHANGE, "Mode change" }, + { EC_EVENT_KEYBOARD_RECOVERY_HWREINIT, "Keyboard recovery hardware reinitialization" }, + { EC_EVENT_EXTENDED, "Extended event" } +}; + +static const struct elog_event_name elog_wake_event_to_name[] = { + { ELOG_WAKE_SOURCE_PCIE, "PCI Express" }, + { ELOG_WAKE_SOURCE_PME, "PME" }, + { ELOG_WAKE_SOURCE_PME_INTERNAL, "Internal PME" }, + { ELOG_WAKE_SOURCE_RTC, "Real Time Clock" }, + { ELOG_WAKE_SOURCE_GPIO, "GPIO" }, + { ELOG_WAKE_SOURCE_SMBUS, "SMBus" }, + { ELOG_WAKE_SOURCE_PWRBTN, "Power Button" }, + { ELOG_WAKE_SOURCE_PME_HDA, "HD Audio PME" }, + { ELOG_WAKE_SOURCE_PME_GBE, "Gigabit Ethernet PME" }, + { ELOG_WAKE_SOURCE_PME_EMMC, "Embedded MMC PME" }, + { ELOG_WAKE_SOURCE_PME_SDCARD, "SD card PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE1, "PCI Express 1 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE2, "PCI Express 2 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE3, "PCI Express 3 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE4, "PCI Express 4 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE5, "PCI Express 5 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE6, "PCI Express 6 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE7, "PCI Express 7 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE8, "PCI Express 8 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE9, "PCI Express 9 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, + { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, + { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, + { ELOG_WAKE_SOURCE_PME_CSE3, "CSE 3 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI, "xHCI PME" }, + { ELOG_WAKE_SOURCE_PME_XDCI, "xDCI PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_2, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_XHCI_USB_3, "xHCI USB2 PME" }, + { ELOG_WAKE_SOURCE_PME_WIFI, "WiFi PME" } +}; + +static const struct elog_event_name elog_ec_device_event_to_name[] = { + { ELOG_EC_DEVICE_EVENT_TRACKPAD, "Trackpad" }, + { ELOG_EC_DEVICE_EVENT_DSP, "DSP" }, + { ELOG_EC_DEVICE_EVENT_WIFI, "WiFi" } +}; + +static const struct elog_event_name mrc_upd_slots[] = { + { ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, "NORMAL" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY, "RECOVERY" }, + { ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, "VARIABLE" } +}; + +static const char *const me_bios_paths[] = { + "ME normal BIOS path", + "ME S3 wake BIOS path", + "ME error BIOS path", + "ME recovery BIOS path", + "ME disable BIOS path", + "ME firmware update BIOS path", +}; + +#endif /* ELOG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8f92f4aaf0e91244fcdec5a4da0ff843bbacda Gerrit-Change-Number: 40343 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: commonlib/elog: move the event definitions to commonlib
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40416 ) Change subject: commonlib/elog: move the event definitions to commonlib ...................................................................... commonlib/elog: move the event definitions to commonlib Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 --- A src/commonlib/include/commonlib/elog.h M src/drivers/elog/elog.c D src/drivers/elog/elog_internal.h M src/include/elog.h 4 files changed, 261 insertions(+), 238 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/40416/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h new file mode 100644 index 0000000..9c10beb --- /dev/null +++ b/src/commonlib/include/commonlib/elog.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef COMMONLIB_ELOG_H_ +#define COMMONLIB_ELOG_H_ + +/* ELOG header */ +struct elog_header { + uint32_t magic; + uint8_t version; + uint8_t header_size; + uint8_t reserved[2]; +} __packed; + +/* ELOG related constants */ +#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ +#define ELOG_VERSION 1 +#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ +#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ + +/* SMBIOS event log header */ +struct event_header { + uint8_t type; + uint8_t length; + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t second; +} __packed; + +/* SMBIOS Type 15 related constants */ +#define ELOG_HEADER_TYPE_OEM 0x88 + +#define MAX_EVENT_SIZE 0x7F + +/* End of log */ +#define ELOG_TYPE_EOL 0xFF + +/* + * Standard SMBIOS event log types below 0x80 + */ +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17 + +/* + * Extended defined OEM event types start at 0x80 + */ + +/* OS/kernel events */ +#define ELOG_TYPE_OS_EVENT 0x81 + +/* Last event from coreboot */ +#define ELOG_TYPE_OS_BOOT 0x90 + +/* Embedded controller event */ +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_DEVICE_EVENT 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12 +#define EC_EVENT_THROTTLE_STOP 0x13 +#define EC_EVENT_HANG_DETECT 0x14 +#define EC_EVENT_HANG_REBOOT 0x15 +#define EC_EVENT_PD_MCU 0x16 +#define EC_EVENT_BATTERY_STATUS 0x17 +#define EC_EVENT_PANIC 0x18 +#define EC_EVENT_KEYBOARD_FASTBOOT 0x19 +#define EC_EVENT_RTC 0x1a +#define EC_EVENT_MKBP 0x1b +#define EC_EVENT_USB_MUX 0x1c +#define EC_EVENT_MODE_CHANGE 0x1d +#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e +#define EC_EVENT_EXTENDED 0x1f + +/* Power */ +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 + +/* Reset */ +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c + +/* Sleep/Wake */ +#define ELOG_TYPE_ACPI_ENTER 0x9d +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 + */ + +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e +#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f + +struct elog_event_data_wake { + uint8_t source; + uint32_t instance; +} __packed; + +/* Chrome OS related events */ +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 + +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 + +struct elog_event_data_me_extended { + uint8_t current_working_state; + uint8_t operation_state; + uint8_t operation_mode; + uint8_t error_code; + uint8_t progress_code; + uint8_t current_pmevent; + uint8_t current_state; +} __packed; + +/* Last post code from previous boot */ +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6 + +/* EC Shutdown Reason */ +#define ELOG_TYPE_EC_SHUTDOWN 0xa5 + +/* + * ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. + */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 + +struct elog_event_mem_cache_update { + uint8_t slot; + uint8_t status; +} __packed; + +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + +/* Cr50 */ +#define ELOG_TYPE_CR50_UPDATE 0xac + +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + +/* EC Device Event */ +#define ELOG_TYPE_EC_DEVICE_EVENT 0xae +#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 +#define ELOG_EC_DEVICE_EVENT_DSP 0x02 +#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 + +/* S0ix sleep/wake */ +#define ELOG_TYPE_S0IX_ENTER 0xaf +#define ELOG_TYPE_S0IX_EXIT 0xb0 + +/* Extended events */ +#define ELOG_TYPE_EXTENDED_EVENT 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +/* Cr50 reset to enable TPM */ +#define ELOG_TYPE_CR50_NEED_RESET 0xb2 + +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + +struct elog_event_extended_event { + uint8_t event_type; + uint32_t event_complement; +} __packed; + +#endif /* COMMONLIB_ELOG_H_ */ diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c353d59..2313ff1 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -20,8 +20,6 @@ #include <stdint.h> #include <string.h> #include <elog.h> -#include "elog_internal.h" - #if CONFIG(ELOG_DEBUG) #define elog_debug(STR...) printk(BIOS_DEBUG, STR) diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h deleted file mode 100644 index 3c58ee2..0000000 --- a/src/drivers/elog/elog_internal.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#ifndef ELOG_INTERNAL_H_ -#define ELOG_INTERNAL_H_ - -/* ELOG header */ -struct elog_header { - u32 magic; - u8 version; - u8 header_size; - u8 reserved[2]; -} __packed; - -/* ELOG related constants */ -#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */ -#define ELOG_VERSION 1 -#define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ -#define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ - -/* SMBIOS event log header */ -struct event_header { - u8 type; - u8 length; - u8 year; - u8 month; - u8 day; - u8 hour; - u8 minute; - u8 second; -} __packed; - -/* SMBIOS Type 15 related constants */ -#define ELOG_HEADER_TYPE_OEM 0x88 - -#endif /* ELOG_INTERNAL_H_ */ diff --git a/src/include/elog.h b/src/include/elog.h index 5a7632d..de642ae 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -4,206 +4,7 @@ #ifndef ELOG_H_ #define ELOG_H_ -#define MAX_EVENT_SIZE 0x7F - -/* End of log */ -#define ELOG_TYPE_EOL 0xFF - -/* - * Standard SMBIOS event log types below 0x80 - */ -#define ELOG_TYPE_UNDEFINED_EVENT 0x00 -#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 -#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 -#define ELOG_TYPE_MEM_PARITY_ERR 0x03 -#define ELOG_TYPE_BUS_TIMEOUT 0x04 -#define ELOG_TYPE_IO_CHECK 0x05 -#define ELOG_TYPE_SW_NMI 0x06 -#define ELOG_TYPE_POST_MEM_RESIZE 0x07 -#define ELOG_TYPE_POST_ERR 0x08 -#define ELOG_TYPE_PCI_PERR 0x09 -#define ELOG_TYPE_PCI_SERR 0x0A -#define ELOG_TYPE_CPU_FAIL 0x0B -#define ELOG_TYPE_EISA_TIMEOUT 0x0C -#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D -#define ELOG_TYPE_LOG_DISABLED 0x0E -#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F -#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 -#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 -#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 -#define ELOG_TYPE_HDD_INFO 0x13 -#define ELOG_TYPE_SYS_RECONFIG 0x14 -#define ELOG_TYPE_CPU_ERROR 0x15 -#define ELOG_TYPE_LOG_CLEAR 0x16 -#define ELOG_TYPE_BOOT 0x17 - -/* - * Extended defined OEM event types start at 0x80 - */ - -/* OS/kernel events */ -#define ELOG_TYPE_OS_EVENT 0x81 - -/* Last event from coreboot */ -#define ELOG_TYPE_OS_BOOT 0x90 - -/* Embedded controller event */ -#define ELOG_TYPE_EC_EVENT 0x91 - -/* Power */ -#define ELOG_TYPE_POWER_FAIL 0x92 -#define ELOG_TYPE_SUS_POWER_FAIL 0x93 -#define ELOG_TYPE_PWROK_FAIL 0x94 -#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 -#define ELOG_TYPE_POWER_ON 0x96 -#define ELOG_TYPE_POWER_BUTTON 0x97 -#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 - -/* Reset */ -#define ELOG_TYPE_RESET_BUTTON 0x99 -#define ELOG_TYPE_SYSTEM_RESET 0x9a -#define ELOG_TYPE_RTC_RESET 0x9b -#define ELOG_TYPE_TCO_RESET 0x9c - -/* Sleep/Wake */ -#define ELOG_TYPE_ACPI_ENTER 0x9d -/* - * Deep Sx wake variant is provided below - 0xad - * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02 - */ - -#define ELOG_TYPE_ACPI_WAKE 0x9e -#define ELOG_TYPE_WAKE_SOURCE 0x9f -#define ELOG_WAKE_SOURCE_PCIE 0x00 -#define ELOG_WAKE_SOURCE_PME 0x01 -#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 -#define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 -#define ELOG_WAKE_SOURCE_SMBUS 0x05 -#define ELOG_WAKE_SOURCE_PWRBTN 0x06 -#define ELOG_WAKE_SOURCE_PME_HDA 0x07 -#define ELOG_WAKE_SOURCE_PME_GBE 0x08 -#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 -#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a -#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b -#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c -#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d -#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e -#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f -#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 -#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 -#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 -#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 -#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 -#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 -#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 -#define ELOG_WAKE_SOURCE_PME_SATA 0x17 -#define ELOG_WAKE_SOURCE_PME_CSE 0x18 -#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 -#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a -#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b -#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d -#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e -#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f -#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 -#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 -#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 -#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 -#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 -#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 -#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 -#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 -#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 -#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 -#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a -#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b - -struct elog_event_data_wake { - u8 source; - u32 instance; -} __packed; - -/* Chrome OS related events */ -#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 -#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 -#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 - -/* Management Engine Events */ -#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 -#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 -struct elog_event_data_me_extended { - u8 current_working_state; - u8 operation_state; - u8 operation_mode; - u8 error_code; - u8 progress_code; - u8 current_pmevent; - u8 current_state; -} __packed; - -/* Last post code from previous boot */ -#define ELOG_TYPE_LAST_POST_CODE 0xa3 -#define ELOG_TYPE_POST_EXTRA 0xa6 - -/* EC Shutdown Reason */ -#define ELOG_TYPE_EC_SHUTDOWN 0xa5 - -/* ARM/generic versions of sleep/wake - These came from another firmware - * apparently, but not all the firmware sources were updated so that the - * elog namespace was coherent. */ -#define ELOG_TYPE_SLEEP 0xa7 -#define ELOG_TYPE_WAKE 0xa8 -#define ELOG_TYPE_FW_WAKE 0xa9 - -/* Memory Cache Update */ -#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa -#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 -#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 -#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 -#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 -#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 -struct elog_event_mem_cache_update { - u8 slot; - u8 status; -} __packed; - -/* CPU Thermal Trip */ -#define ELOG_TYPE_THERM_TRIP 0xab - -/* Cr50 */ -#define ELOG_TYPE_CR50_UPDATE 0xac - -/* Deep Sx wake variant */ -#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad - -/* EC Device Event */ -#define ELOG_TYPE_EC_DEVICE_EVENT 0xae -#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01 -#define ELOG_EC_DEVICE_EVENT_DSP 0x02 -#define ELOG_EC_DEVICE_EVENT_WIFI 0x03 - -/* S0ix sleep/wake */ -#define ELOG_TYPE_S0IX_ENTER 0xaf -#define ELOG_TYPE_S0IX_EXIT 0xb0 - -/* Extended events */ -#define ELOG_TYPE_EXTENDED_EVENT 0xb1 -#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 -#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 - -/* Cr50 reset to enable TPM */ -#define ELOG_TYPE_CR50_NEED_RESET 0xb2 - -/* Intruder detection */ -#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 -#define ELOG_CASE_OPENED 0x01 -#define ELOG_CASE_CLOSED 0x02 - -struct elog_event_extended_event { - u8 event_type; - u32 event_complement; -} __packed; +#include <commonlib/elog.h> #if CONFIG(ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I791ede6f2d88ba4686d11b34686fedc6c3401f07 Gerrit-Change-Number: 40416 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

9 29

Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 ) Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed ...................................................................... drivers/amd/agesa/romstage: Only mark cbmem as UC if needed Now cbmem is flushed to dram before calling postcar stage. UNTESTED. Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/mtrr_fixme.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..9e63425 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -51,6 +51,10 @@ if (s3resume) return; + /* We worry about cbmem hitting dram later */ + if (clflush_supported()) + return; + /* For normal path, INIT_POST has returned with all * memory set WB cacheable. But we need CBMEM as UC * to make CAR teardown with invalidation without -- To view, visit https://review.coreboot.org/c/coreboot/+/37197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Gerrit-Change-Number: 37197 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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