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Change in coreboot[master]: libpayload: Improve rtc functions
by Patrick Georgi (Code Review) 09 Mar '20

09 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/18498 ) Change subject: libpayload: Improve rtc functions ...................................................................... libpayload: Improve rtc functions On Lenovo T500 the RTC readings where wrong, as RTC has different encodings, depending on the statusB register. Support BCD vs binary RTC format and AM/PM vs 24h RTC format. Fixes wrong date and time on Lenovo 500. Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18498 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/drivers/nvram.c M payloads/libpayload/include/libpayload.h 2 files changed, 41 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index a116d1b..34ee033 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -111,23 +112,51 @@ */ void rtc_read_clock(struct tm *time) { + u16 timeout = 10000; + u8 statusB; + u8 reg8; + memset(time, 0, sizeof(*time)); - while(nvram_updating()); + while (nvram_updating()) + if (!timeout--) + return; - time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; - time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); - time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); - time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); - time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + statusB = nvram_read(NVRAM_RTC_STATUSB); + + if (!(statusB & NVRAM_RTC_FORMAT_BINARY)) { + time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; + time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); + time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); + time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); + + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = bcd2dec(reg8 & 0x7f); + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); + } else { + time->tm_mon = nvram_read(NVRAM_RTC_MONTH) - 1; + time->tm_sec = nvram_read(NVRAM_RTC_SECONDS); + time->tm_min = nvram_read(NVRAM_RTC_MINUTES); + time->tm_mday = nvram_read(NVRAM_RTC_DAY); + if (!(statusB & NVRAM_RTC_FORMAT_24HOUR)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = reg8 & 0x7f; + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = nvram_read(NVRAM_RTC_HOURS); + time->tm_year = nvram_read(NVRAM_RTC_YEAR); + } /* Instead of finding the century register, we just make an assumption that if the year value is less then 80, then it is 2000+ */ - - time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); - if (time->tm_year < 80) time->tm_year += 100; } diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 4b6a250..7496972 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -130,6 +130,9 @@ #define NVRAM_RTC_YEAR 9 /**< RTC Year offset in CMOS */ #define NVRAM_RTC_FREQ_SELECT 10 /**< RTC Update Status Register */ #define NVRAM_RTC_UIP 0x80 +#define NVRAM_RTC_STATUSB 11 /**< RTC Status Register B */ +#define NVRAM_RTC_FORMAT_24HOUR 0x02 +#define NVRAM_RTC_FORMAT_BINARY 0x04 /** Broken down time structure */ struct tm { -- To view, visit https://review.coreboot.org/c/coreboot/+/18498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Gerrit-Change-Number: 18498 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Documentation: Add GM45 ThinkPads common page
by Evgeny Zinoviev (Code Review) 09 Mar '20

09 Mar '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38926 ) Change subject: Documentation: Add GM45 ThinkPads common page ...................................................................... Documentation: Add GM45 ThinkPads common page - Add a common page about X200/T400/T500 ThinkPads. - Describe how to remove ME on these models. - Describe default flash layouts. Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/xx00_series.md 2 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38926/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index ce30ee2..3b5903b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -77,6 +77,7 @@ ### GM45 series +- [X200 / T400 / T500 common](lenovo/xx00_series.md) - [X301](lenovo/x301.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/xx00_series.md b/Documentation/mainboard/lenovo/xx00_series.md new file mode 100644 index 0000000..3ac7c87 --- /dev/null +++ b/Documentation/mainboard/lenovo/xx00_series.md @@ -0,0 +1,114 @@ +# Lenovo X200 / T400 / T500 common + +These models can have 8 MB or 4 MB flash chip installed. You can identify the +chip in your machine through flashrom: +``` +flashrom -p internal +``` + +## Installing without ME firmware + +On GM45 machines it's possible to disable and remove ME by modifying the flash +descriptor. This also make it possible to use the flash region the ME used for +`bios` region, allowing for much larger payloads. + +First of all create a backup of your ROM with an external programmer: +``` +flashrom -p YOUR_PROGRAMMER -r backup.rom +``` + +Then extract FD modules to a separate files. Your will need +`flashregion_3_gbe.bin` later. +``` +ifdtool -x backup.rom +``` + +There is a tool to generate modified flash descriptor called **bincfg**. Go to +`util/bincfg` and build it: +``` +cd util/bincfg +make +``` + +If your flash is 4 MB, edit the `ifd-x200.set` file as shown: + +```diff +diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set +--- a/util/blobtool/ifd-x200.set ++++ b/util/blobtool/ifd-x200.set +@@ -35,7 +35,7 @@ + "flmap2_msl" = 0x1, + "flmap2_reserved" = 0x0, + +- "flcomp_density1" = 0x4, ++ "flcomp_density1" = 0x3, + "flcomp_density2" = 0x2, + "flcomp_reserved0" = 0x0, + "flcomp_reserved1" = 0x0, +@@ -56,7 +56,7 @@ + "flreg0_reserved1" = 0x0, + "flreg1_base" = 0x3, + "flreg1_reserved0" = 0x0, +- "flreg1_limit" = 0x7ff, ++ "flreg1_limit" = 0x3ff, + "flreg1_reserved1" = 0x0, + "flreg2_base" = 0x1fff, + "flreg2_reserved0" = 0x0, +``` + +Create the flash descriptor: +``` +./bincfg ifd-x200.spec ifd-x200.set ifd.bin +``` + +Now configure coreboot. You need to select correct chip size and specify paths +to flash descriptor and gbe dump. +``` +Mainboard ---> + ROM chip size (8192 KB (8 MB)) # According to your chip + (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip + +Chipset ---> + [*] Add Intel descriptor.bin file + (/path/to/util/bincfg/ifd.bin) Path and filename of the descriptor.bin file + + [*] Add gigabit ethernet configuration + (/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration +``` + +Then build coreboot and flash whole `build/coreboot.rom` to the chip. + +## Installing with ME firmware + +To install coreboot and keep ME, you don't need to do anything special. Just +flash only `bios` and don't touch other regions: +``` +flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios +``` + +## Flash layout + +The flash layout of the OEM firmware on 8 MB chips is as follows: +``` +00000000:00000fff descriptor +00001000:005f5fff me +005f6000:005f7fff gbe +005f8000:005fffff platform +00600000:007fffff bios +00690000:006affff ec +007e0000:007fffff bootblock +``` + +On 4 MB chips: +``` +00000000:00000fff descriptor +00001000:001f5fff me +001f6000:001f7fff gbe +001f8000:001fffff platform +00200000:003fffff bios +00290000:002affff ec +003e0000:003fffff bootblock +``` + +The `ec` region is not where EC firmware is stored. It's where EC firmware +updates are stored for PhoenixBIOS to write them to EC once. -- To view, visit https://review.coreboot.org/c/coreboot/+/38926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Gerrit-Change-Number: 38926 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/corebootfb: Add option to center a 80x25 console
by Nico Huber (Code Review) 09 Mar '20

09 Mar '20

Hello Julius Werner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38538 to review the following change. Change subject: libpayload/corebootfb: Add option to center a 80x25 console ...................................................................... libpayload/corebootfb: Add option to center a 80x25 console This makes payloads which are hardcoded to a 80x25 console look much better, e.g. FILO with its "GRUB" user interface. Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/video/corebootfb.c 2 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/38538/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e3..36f4af5 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -315,6 +315,13 @@ Say Y here if coreboot switched to a graphics mode and your payload wants to use it. +config COREBOOT_VIDEO_CENTERED + bool "Center a classic 80x25 console on bigger screens" + depends on COREBOOT_VIDEO_CONSOLE + help + Say 'y' here if your payload is hardcoded to a 80x25 console. Otherwise + its output would look squeezed into the upper-left corner of the screen. + config FONT_SCALE_FACTOR int "Scale factor for the included font" depends on GEODELX_VIDEO_CONSOLE || COREBOOT_VIDEO_CONSOLE diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index c4b5048..8e7ac11 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -236,8 +236,16 @@ font_init(FI->x_resolution); - coreboot_video_console.columns = FI->x_resolution / font_width; - coreboot_video_console.rows = FI->y_resolution / font_height; + /* Draw centered on the framebuffer if requested and feasible, */ + const int center = + IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CENTERED) + && coreboot_video_console.columns * font_width <= FI->x_resolution + && coreboot_video_console.rows * font_height <= FI->y_resolution; + /* adapt to the framebuffer size, otherwise. */ + if (!center) { + coreboot_video_console.columns = FI->x_resolution / font_width; + coreboot_video_console.rows = FI->y_resolution / font_height; + } chars = malloc(coreboot_video_console.rows * coreboot_video_console.columns * 2); @@ -246,6 +254,17 @@ // clear boot splash screen if there is one. corebootfb_clear(); + + if (center) { + FI->physical_address += + (FI->x_resolution - coreboot_video_console.columns * font_width) + / 2 * FI->bits_per_pixel / 8 + + (FI->y_resolution - coreboot_video_console.rows * font_height) + / 2 * FI->bytes_per_line; + FI->x_resolution = coreboot_video_console.columns * font_width; + FI->y_resolution = coreboot_video_console.rows * font_height; + } + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Gerrit-Change-Number: 38538 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: libpayload/corebootfb: Keep local copy of framebuffer info
by Nico Huber (Code Review) 09 Mar '20

09 Mar '20

Hello Julius Werner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38537 to review the following change. Change subject: libpayload/corebootfb: Keep local copy of framebuffer info ...................................................................... libpayload/corebootfb: Keep local copy of framebuffer info Keeping a local copy of the framebuffer info allows us to make changes, e.g. add offsets. It also avoids trouble with relocation. Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/drivers/video/corebootfb.c 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38537/1 diff --git a/payloads/libpayload/drivers/video/corebootfb.c b/payloads/libpayload/drivers/video/corebootfb.c index 11397ba..c4b5048 100644 --- a/payloads/libpayload/drivers/video/corebootfb.c +++ b/payloads/libpayload/drivers/video/corebootfb.c @@ -61,13 +61,12 @@ (0xFF << 16) | (0xFF << 8) | 0xFF, }; -/* Addresses for the various components */ -static unsigned long fbinfo; -static unsigned long fbaddr; +struct cb_framebuffer fbinfo; static unsigned short *chars; -#define FI ((struct cb_framebuffer *) phys_to_virt(fbinfo)) -#define FB ((unsigned char *) phys_to_virt(fbaddr)) +/* Addresses for the various components */ +#define FI (&fbinfo) +#define FB ((unsigned char *) phys_to_virt(FI->physical_address)) #define CHARS (chars) static void corebootfb_scroll_up(void) @@ -230,12 +229,9 @@ if (lib_sysinfo.framebuffer == NULL) return -1; - /* We might have been called before relocation (like FILO does). So - just keep the physical address which won't break on relocation. */ - fbinfo = virt_to_phys(lib_sysinfo.framebuffer); + fbinfo = *lib_sysinfo.framebuffer; - fbaddr = FI->physical_address; - if (fbaddr == 0) + if (FI->physical_address == 0) return -1; font_init(FI->x_resolution); -- To view, visit https://review.coreboot.org/c/coreboot/+/38537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64 Gerrit-Change-Number: 38537 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/superiotool: Drop one SCH5317 entry
by Angel Pons (Code Review) 09 Mar '20

09 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39376 ) Change subject: util/superiotool: Drop one SCH5317 entry ...................................................................... util/superiotool: Drop one SCH5317 entry The SCH5317 can have either 0x85 or 0x8c as device ID. However, the former results in false positives on any ITE IT85xx series embedded controller, which has led some people to think that chip was actually in their laptops. Moreover, there is no register dump for the SCH5317. Since nobody has touched this in over a decade, avoid further confusion by dropping the misleading definition. Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/superiotool/smsc.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39376/1 diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index ab61ba4..7e50548 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -860,9 +860,6 @@ {EOT}}}, {0x83, "SCH5514D", { /* From sensors-detect */ {EOT}}}, - {0x85, "SCH5317", { /* From sensors-detect */ - /* The SCH5317 can have either 0x85 or 0x8c as device ID. */ - {EOT}}}, {0x86, "SCH5127", { /* From sensors-detect, dump from datasheet */ {NOLDN, NULL, {0x02,0x03,0x21,0x22,0x23,0x24,0x26,0x27, -- To view, visit https://review.coreboot.org/c/coreboot/+/39376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d Gerrit-Change-Number: 39376 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/intel/tglrvp: Add memory config for Tiger Lake UP4
by Srinidhi N Kaushik (Code Review) 09 Mar '20

09 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39365 ) Change subject: mb/intel/tglrvp: Add memory config for Tiger Lake UP4 ...................................................................... mb/intel/tglrvp: Add memory config for Tiger Lake UP4 Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e --- M src/mainboard/intel/tglrvp/board_id.h M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c 3 files changed, 31 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39365/1 diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h old mode 100644 new mode 100755 index 364f4f7..2e3a7ff --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -22,9 +22,14 @@ #define EC_FAB_ID_CMD 0x0D /* TGL-U Board IDs */ -#define TGL_U_LP4_SAMSUNG 0x3 -#define TGL_U_LP4_HYNIX 0xB -#define TGL_U_LP4_MICRON 0x13 +#define TGL_UP3_LP4_SAMSUNG 0x3 +#define TGL_UP3_LP4_HYNIX 0xB +#define TGL_UP3_LP4_MICRON 0x13 + +/* TGL-Y Board IDs */ +#define TGL_UP4_LP4_SAMSUNG 0x5 +#define TGL_UP4_LP4_HYNIX 0xD +#define TGL_UP4_LP4_MICRON 0x15 /* * Returns board information (board id[15:8] and diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c old mode 100644 new mode 100755 index 89ae0ab..eb8fde0 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -32,13 +32,16 @@ printk(BIOS_INFO, "board id is 0x%x\n", board_id); switch (board_id) { - case TGL_U_LP4_MICRON: + case TGL_UP3_LP4_MICRON: + case TGL_UP4_LP4_MICRON: spd_index = SPD_ID_MICRON; break; - case TGL_U_LP4_SAMSUNG: + case TGL_UP3_LP4_SAMSUNG: + case TGL_UP4_LP4_SAMSUNG: spd_index = SPD_ID_SAMSUNG; break; - case TGL_U_LP4_HYNIX: + case TGL_UP3_LP4_HYNIX: + case TGL_UP4_LP4_HYNIX: spd_index = SPD_ID_HYNIX; break; default: diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 67979b6..bdeb842 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -25,28 +25,28 @@ static const struct mb_lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ - 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ - { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ - 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ - { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ - 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ - { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ - 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ - { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ - 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ - { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ - 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ - { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ - 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ - { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ - 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + { 8, 9, 12, 11, 13, 15, 10, 14, /* Byte 0 */ + 4, 6, 0, 2, 5, 7, 1, 3 }, /* Byte 1 */ + { 2, 3, 0, 6, 1, 7, 5, 4, /* Byte 2 */ + 15, 14, 13, 8, 12, 11, 9, 10 }, /* Byte 3 */ + { 1, 0, 3, 2, 5, 4, 7, 6, /* Byte 4 */ + 14, 15, 12, 13, 8, 10, 9, 11 }, /* Byte 5 */ + { 8, 10, 11, 9, 15, 12, 14, 13, /* Byte 6 */ + 4, 7, 6, 5, 2, 0, 1, 3 }, /* Byte 7 */ + { 8, 9, 10, 11, 13, 12, 15, 14, /* Byte 0 */ + 7, 6, 4, 5, 0, 2, 1, 3 }, /* Byte 1 */ + { 1, 3, 0, 2, 6, 4, 5, 7, /* Byte 2 */ + 14, 15, 10, 12, 8, 13, 11, 9 }, /* Byte 3 */ + { 1, 0, 2, 4, 5, 3, 7, 6, /* Byte 4 */ + 12, 14, 15, 13, 9, 10, 8, 11 }, /* Byte 5 */ + { 11, 9, 8, 13, 12, 14, 15, 10, /* Byte 6 */ + 4, 7, 5, 1, 2, 6, 3, 0 } /* Byte 7 */ }, /* DQS CPU<>DRAM map */ .dqs_map = { /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/39365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Gerrit-Change-Number: 39365 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Add TGL UP4 RVP
by Wonkyu Kim (Code Review) 09 Mar '20

09 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39363 ) Change subject: mb/intel/tglrvp: Add TGL UP4 RVP ...................................................................... mb/intel/tglrvp: Add TGL UP4 RVP Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc A src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb A src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c A src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c 6 files changed, 402 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/39363/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 5eec51e..2051a05 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_TGLRVP_UP3 +if BOARD_INTEL_TGLRVP_UP3 || BOARD_INTEL_TGLRVP_UP4 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,11 +28,13 @@ config VARIANT_DIR string default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3 + default "tglrvp_up4" if BOARD_INTEL_TGLRVP_UP4 config GBB_HWID string depends on CHROMEOS - default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3 + default "TGLRVPUP3" if BOARD_INTEL_TGLRVP_UP3 + default "TGLRVPUP4" if BOARD_INTEL_TGLRVP_UP4 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name index a2271f3..eb8e796 100644 --- a/src/mainboard/intel/tglrvp/Kconfig.name +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_INTEL_TGLRVP_UP3 - bool "Tigerlake UP3 DDR4/LPDDR4 RVP" + bool "Tigerlake UP3 RVP" + +config BOARD_INTEL_TGLRVP_UP4 + bool "Tigerlake UP4 RVP" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc new file mode 100644 index 0000000..c272607 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019-2020 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb new file mode 100644 index 0000000..e61690e --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -0,0 +1,207 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + register "SmbusEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[10]" = "1" + + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + + register "PcieClkSrcUsage[1]" = "0x2" + register "PcieClkSrcUsage[2]" = "0x3" + register "PcieClkSrcUsage[3]" = "0x8" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + + # enabling EDP in PortA + register "DdiPortAConfig" = "1" + + register "DdiPort1Hpd" = "1" + register "DdiPort1Ddc" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + #HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[0]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 on end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 off end # TBT_PCIe0 0x9A23 + device pci 07.1 off end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 on end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 on end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/max98373 + register "vmon_slot_no" = "4" + register "imon_slot_no" = "5" + register "uid" = "0" + register "desc" = ""RIGHT SPEAKER AMP"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "6" + register "imon_slot_no" = "7" + register "uid" = "1" + register "desc" = ""LEFT SPEAKER AMP"" + register "name" = ""MAXL"" + device i2c 32 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)" + register "probed" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 on end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 on end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 off end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c new file mode 100644 index 0000000..46ed5a2 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* PCH M.2 SSD */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* Camera */ + PAD_CFG_GPO(GPP_B23, 0, PLTRST), + PAD_CFG_GPO(GPP_C15, 0, PLTRST), + PAD_CFG_GPO(GPP_R6, 0, PLTRST), + PAD_CFG_GPO(GPP_H12, 0, PLTRST), + + /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + + /* ISH UART0 RX/TX */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + + /* ISH I2C0 */ + PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + + /* ISH GPI 0-6 */ + PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + + /*Audio */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /*Audio */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ + + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c new file mode 100644 index 0000000..67979b6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <baseboard/variants.h> +#include <intelblocks/mp_init.h> + +size_t __weak variant_memory_sku(void) +{ + return 0; +} + +static const struct mb_lpddr4x_cfg mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ + 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ + { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ + 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ + { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ + 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ + { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ + 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ + { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ + 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ + { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ + 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ + { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ + 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ + { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ + 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &mem_config; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Gerrit-Change-Number: 39363 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Patrick Georgi (Code Review) 09 Mar '20

09 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39364 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 1 file changed, 16 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 24cbd6e..8ab5878 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -635,7 +635,18 @@ /** Offset 0x091A - Reserved **/ - UINT8 Reserved33[438]; + UINT8 Reserved33[3]; + +/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration +**/ + UINT8 HybridStorageMode; + +/** Offset 0x091E - Reserved +**/ + UINT8 Reserved34[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -643,7 +654,7 @@ /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved34[101]; + UINT8 Reserved35[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -661,7 +672,7 @@ /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved35[264]; + UINT8 Reserved36[264]; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -675,7 +686,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved36[269]; + UINT8 Reserved37[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -683,7 +694,7 @@ /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved37[80]; + UINT8 Reserved38[80]; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/39364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Gerrit-Change-Number: 39364 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake
by Patrick Georgi (Code Review) 09 Mar '20

09 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39364 ) Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Gerrit-Change-Number: 39364 Gerrit-PatchSet: 2 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Mar 2020 08:07:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/puff: Enable cros_ec_keyb device
by Edward O'Callaghan (Code Review) 08 Mar '20

08 Mar '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39391 ) Change subject: mainboard/google/puff: Enable cros_ec_keyb device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d Gerrit-Change-Number: 39391 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Mar 2020 04:57:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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