coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: add support to read spd data from SMBUS
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39401 ) Change subject: soc/intel/tigerlake: add support to read spd data from SMBUS ...................................................................... Patch Set 3: (4 comments) > Patch Set 3: > > (1 comment) https://review.coreboot.org/c/coreboot/+/39401/1/src/soc/intel/tigerlake/me… File src/soc/intel/tigerlake/meminit_jsl.c: https://review.coreboot.org/c/coreboot/+/39401/1/src/soc/intel/tigerlake/me… PS1, Line 50: memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); > two instances not needed, we can keep it as original place, the sbmus would re-initialize it anyway. I will do change so get_spd_data() will no change. https://review.coreboot.org/c/coreboot/+/39401/1/src/soc/intel/tigerlake/me… PS1, Line 120: spd_data_ptr > this is not getting initialized now, meminit_channels would set the invalid values for MemorySpdPtrX […] I will do change so get_spd_data() will no change. https://review.coreboot.org/c/coreboot/+/39401/1/src/soc/intel/tigerlake/me… PS1, Line 122: get_spd_data > We can handle the SMBUS case here instead of changing the func to accommodate SMBUS, get_spd_data, s […] go it https://review.coreboot.org/c/coreboot/+/39401/3/src/soc/intel/tigerlake/me… File src/soc/intel/tigerlake/meminit_jsl.c: https://review.coreboot.org/c/coreboot/+/39401/3/src/soc/intel/tigerlake/me… PS3, Line 122: get_spd_data > can u do something like this ? in that way u don't need to change assumptions of get_spd_data() […] got your point will change this. -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:21:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has uploaded a new patch set (#11) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for JSLRVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for JSLRVP Add memory initialization parameters for JSLRVP board JSLRVP supports two variants, one with memory LPDDR4 and another with DDR4. Based on board id, mainboard will pass correct memory parameters to the soc. BUG=None BRANCH=None TEST=Check compilation for jslrvp and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_ddr4.c A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_lp4x.c 9 files changed, 216 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for JSLRVP ...................................................................... Patch Set 10: (13 comments) https://review.coreboot.org/c/coreboot/+/39195/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39195/3//COMMIT_MSG@7 PS3, Line 7: mb/intel/jasperlake_rvp: memory config for JSLRVP > Please make it a statement by adding a verb (in imperative mood). Done https://review.coreboot.org/c/coreboot/+/39195/3//COMMIT_MSG@8 PS3, Line 8: > Please write a commit message. Done https://review.coreboot.org/c/coreboot/+/39195/3/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/3/src/mainboard/intel/jasper… PS3, Line 30: {.spd_smbus_address[1] = 0xA0, : .spd_smbus_address[2] = 0xA2, : .spd_smbus_address[3] = 0xA4, : .spd_smbus_address[1] = 0xA6} > Please add appropriate spaces. Ack https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 41: }; > code indent should use tabs where possible Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 41: }; > please, no spaces at the start of a line Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 45: if ( board_id == jsl_ddr4 ) > space prohibited before that close parenthesis ')' Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 45: if ( board_id == jsl_ddr4 ) > space prohibited after that open parenthesis '(' Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 47: else if ( board_id == jsl_lpddr4 ) > space prohibited before that close parenthesis ')' Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 47: else if ( board_id == jsl_lpddr4 ) > space prohibited after that open parenthesis '(' Done https://review.coreboot.org/c/coreboot/+/39195/4/src/mainboard/intel/jasper… PS4, Line 50: die(" Unsupported Board id : 0x%x \n", board_id); > unnecessary whitespace before a quoted newline Done https://review.coreboot.org/c/coreboot/+/39195/5/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/5/src/mainboard/intel/jasper… PS5, Line 50: die("Unsupported Board id : 0x%x \n", board_id); > unnecessary whitespace before a quoted newline Done https://review.coreboot.org/c/coreboot/+/39195/9/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/9/src/mainboard/intel/jasper… PS9, Line 40: 1 > 4? Ack https://review.coreboot.org/c/coreboot/+/39195/3/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_ddr4.c: https://review.coreboot.org/c/coreboot/+/39195/3/src/mainboard/intel/jasper… PS3, Line 58: */ > One line, and remove the dot/period at the end. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has uploaded a new patch set (#10) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for JSLRVP ...................................................................... mb/intel/jasperlake_rvp: Add memory config for JSLRVP Add memory initialization parameters for JSLRVP board JSLRVP supports two variants, one with memory LPDDR4 and another with DDR4. Based on board id, mainboard will pass correct memory parameters to the soc. BUG=None BRANCH=None TEST=Check compilation for jslrvp and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_ddr4.c A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_lp4x.c 9 files changed, 215 insertions(+), 143 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/jasperlake_rvp: add JSLRVP DDR4 variant
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39400 ) Change subject: mb/intel/jasperlake_rvp: add JSLRVP DDR4 variant ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/39400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d25fc13a4e6e2b6a58615e7ef58dd3c118089 Gerrit-Change-Number: 39400 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/intel/jasperlake_rvp: add JSLRVP DDR4 variant
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39400 ) Change subject: mb/intel/jasperlake_rvp: add JSLRVP DDR4 variant ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/39400/1/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/Kconfig: https://review.coreboot.org/c/coreboot/+/39400/1/src/mainboard/intel/jasper… PS1, Line 1: BOARD_INTEL_JASPERLAKE_RVP_DDR4 > can we do it based on board_id read? […] change is already pushed in other memory CL -- To view, visit https://review.coreboot.org/c/coreboot/+/39400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96d25fc13a4e6e2b6a58615e7ef58dd3c118089 Gerrit-Change-Number: 39400 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:13:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: add memory config for JSLRVP
by Subrata Banik (Code Review) 17 Mar '20

17 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: add memory config for JSLRVP ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/39195/9/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/9/src/mainboard/intel/jasper… PS9, Line 40: 1 4? -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:12:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: add memory config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has uploaded a new patch set (#9) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: add memory config for JSLRVP ...................................................................... mb/intel/jasperlake_rvp: add memory config for JSLRVP Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex D src/mainboard/intel/jasperlake_rvp/spd/spd_util.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_ddr4.c A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory_lp4x.c 9 files changed, 215 insertions(+), 143 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39195/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: jasperlake_rvp: Add UART config for JSLRVP
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Hello Varshit B Pandya, build bot (Jenkins), Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39196 to look at the new patch set (#9). Change subject: jasperlake_rvp: Add UART config for JSLRVP ...................................................................... jasperlake_rvp: Add UART config for JSLRVP Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/39196/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: add support to read spd data from SMBUS
by Subrata Banik (Code Review) 17 Mar '20

17 Mar '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39401 ) Change subject: soc/intel/tigerlake: add support to read spd data from SMBUS ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/39401/3/src/soc/intel/tigerlake/me… File src/soc/intel/tigerlake/meminit_jsl.c: https://review.coreboot.org/c/coreboot/+/39401/3/src/soc/intel/tigerlake/me… PS3, Line 122: get_spd_data can u do something like this ? in that way u don't need to change assumptions of get_spd_data() /* Initialize onboard memory configurations for lpddr4x */ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg, const struct spd_info *spd_info, bool half_populated) { if (spd_info->read_type == READ_SMBUS) { for (int i = 0; i < NUM_DIMM_SLOT; i++) mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i]; } else { size_t spd_data_len = 0; uintptr_t spd_data_ptr = 0; memset (&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable)); get_spd_data(spd_info, &spd_data_ptr, &spd_data_len); mem_cfg->MemorySpdDataLen = spd_data_len; meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); } mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2020