coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/tigerlake: add support to read spd data from SMBUS
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Hello V Sowmya, Varshit B Pandya, build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39401 to look at the new patch set (#4). Change subject: soc/intel/tigerlake: add support to read spd data from SMBUS ...................................................................... soc/intel/tigerlake: add support to read spd data from SMBUS JSLRVP has DDR4 variant which uses SMBUS address to read SPD data. So, add support to read SPD data from SMBUS Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/tigerlake/include/soc/meminit_jsl.h M src/soc/intel/tigerlake/meminit_jsl.c 2 files changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39401/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/39401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Gerrit-Change-Number: 39401 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/lynxpoint/gpio: fix interrupt storm
by Matt DeVillier (Code Review) 17 Mar '20

17 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39578 ) Change subject: sb/lynxpoint/gpio: fix interrupt storm ...................................................................... sb/lynxpoint/gpio: fix interrupt storm On newer kernels (> 4.9 LTS), the GPIO ACPI device's interrupt resource causes an interrupt storm which prevents the CPU from properly idling, significantly increasing power consumption. This was fixed for soc/broadwell (which also supports lynxpoint-lp) by removing the interrupt resource, so apply the same fix here. Original fix: https://chromium-review.googlesource.com/203645 Test: build/boot google/wolf, verify CPU0 idles correctly and power consumption drop via powertop in kernels 4.16.18 and 5.x. Change-Id: Ic4963f2f0225b5f44a7604b0107911640345c855 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/39578/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 88138a1..2a3c096 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -551,8 +551,9 @@ , // ResourceSourceIndex , // ResourceSource BAR0) - Interrupt (ResourceConsumer, - Level, ActiveHigh, Shared, , ,) {14} + // Disabled due to IRQ storm: http://crosbug.com/p/29548 + //Interrupt (ResourceConsumer, + // Level, ActiveHigh, Shared, , , ) {14} }) Method (_CRS, 0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/39578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4963f2f0225b5f44a7604b0107911640345c855 Gerrit-Change-Number: 39578 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add waddledee variant
by Karthik Ramasubramanian (Code Review) 17 Mar '20

17 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39580 ) Change subject: mb/google/dedede: Add waddledee variant ...................................................................... mb/google/dedede: Add waddledee variant Add initial support for waddledee variant BUG=b:151576904 TEST=Build the mainboard and variant board. Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledee/Makefile.inc A src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h A src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h A src/mainboard/google/dedede/variants/waddledee/overridetree.cb 6 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39580/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 36b42bf..e2afc66 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -53,6 +53,7 @@ string default "Dedede" if BOARD_GOOGLE_DEDEDE default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "Waddledee" if BOARD_GOOGLE_WADDLEDEE config MAX_CPUS int @@ -74,5 +75,6 @@ string default "dedede" if BOARD_GOOGLE_DEDEDE default "waddledoo" if BOARD_GOOGLE_WADDLEDOO + default "waddledee" if BOARD_GOOGLE_WADDLEDEE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index ae5df66..d083d2d 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -9,3 +9,9 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + +config BOARD_GOOGLE_WADDLEDEE + bool "Waddledee" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc new file mode 100644 index 0000000..c55051b --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc @@ -0,0 +1,11 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_SOURCES = empty #0b0000 +SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001 +SPD_SOURCES += samsung-K4U6E3S4AA-MGCL #0b0010 diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h new file mode 100644 index 0000000..cc897dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h new file mode 100644 index 0000000..bf23f6e --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/waddledee/overridetree.cb b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb new file mode 100644 index 0000000..23db34e --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/overridetree.cb @@ -0,0 +1,40 @@ +chip soc/intel/tigerlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c Gerrit-Change-Number: 39580 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/early_init: Add static PHY init
by Paul Menzel (Code Review) 17 Mar '20

17 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20926 ) Change subject: nb/intel/sandybridge/early_init: Add static PHY init ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/20926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If66eba3d717c579228876467096bbada20732533 Gerrit-Change-Number: 20926 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 08:48:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for JSLRVP
by Aamir Bohra (Code Review) 17 Mar '20

17 Mar '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39195 ) Change subject: mb/intel/jasperlake_rvp: Add memory config for JSLRVP ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/39195/7/src/mainboard/intel/jasper… File src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/39195/7/src/mainboard/intel/jasper… PS7, Line 30: const struct spd_info lpddr4_spd_info = { : .read_type = READ_SPD_CBFS, : .spd_spec.spd_index = 0x0, : }; : : const struct spd_info ddr4_spd_info = { : .read_type = READ_SMBUS, : .spd_spec = {.spd_smbus_address[1] = 0xA0, : .spd_smbus_address[2] = 0xA2, : .spd_smbus_address[3] = 0xA4, : .spd_smbus_address[1] = 0xA6} : }; can we initialize it within the boardid checks below https://review.coreboot.org/c/coreboot/+/39195/11/src/mainboard/intel/jaspe… File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/39195/11/src/mainboard/intel/jaspe… PS11, Line 17: romstage-$(CONFIG_BOARD_INTEL_JASPERLAKE_RVP) += memory_lp4x.c : romstage-$(CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC) += memory_lp4x.c : romstage-$(CONFIG_BOARD_INTEL_JASPERLAKE_RVP_DDR4) += memory_ddr4.c since we are using the board id function to differentiate on the board type, can we eliminate the extra variant, maintain the lpprd4 and ddr4 mem config in memory.c and board id as parameter to variant_mem_config and return the baseboard_mem_cfg(drr4/lpddr4 configs ) -- To view, visit https://review.coreboot.org/c/coreboot/+/39195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Gerrit-Change-Number: 39195 Gerrit-PatchSet: 11 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 08:39:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/intel/tglrvp: Update camera ACPI configuration
by Daniel Kang (Code Review) 17 Mar '20

17 Mar '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39529 ) Change subject: src/mb/intel/tglrvp: Update camera ACPI configuration ...................................................................... src/mb/intel/tglrvp: Update camera ACPI configuration * Change power sequence to make closer to sensor data sheet * Handle different PWREN GPIO pin for up3 and up4 * Add link frequencies definitions to sensor side * Clean up format BUG=None BRANCH=None TEST=Build and boot TGLRVP U or Y. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 --- M src/mainboard/intel/tglrvp/acpi/mipi_camera.asl 1 file changed, 115 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39529/1 diff --git a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl old mode 100644 new mode 100755 index 5d42a29..98861b0 --- a/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/tglrvp/acpi/mipi_camera.asl @@ -15,7 +15,7 @@ Scope (\_SB.PCI0.IPU0) { - Name (_DSD, Package (0x02) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x02) @@ -25,7 +25,6 @@ "port0", "PRT0" }, - Package (0x02) { "port1", @@ -45,7 +44,6 @@ One } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -81,7 +79,7 @@ }) } -Scope (_SB.PCI0.IPU0) +Scope (\_SB.PCI0.IPU0) { Name (EP00, Package (0x02) { @@ -93,13 +91,11 @@ "endpoint", Zero }, - Package (0x02) { "clock-lanes", Zero }, - Package (0x02) { "data-lanes", @@ -111,7 +107,6 @@ 0x04 } }, - Package (0x02) { "remote-endpoint", @@ -134,13 +129,11 @@ "endpoint", Zero }, - Package (0x02) { "clock-lanes", Zero }, - Package (0x02) { "data-lanes", @@ -172,40 +165,45 @@ PowerResource (RCPR, 0x00, 0x0000) { Name (STA, Zero) - Method (_ON, 0, Serialized) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ { If ((STA == Zero)) { - /* Enable CLK0 with 19.2MHz */ - MCON(0,1) - /* Pull PWREN(GPIO B23) high */ - STXS(GPP_B23) - Sleep(5) - /* Pull RST(GPIO C15) low */ + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + + /* Pull RST low */ CTXS(GPP_C15) - Sleep(5) + + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + /* Pull RST high */ STXS(GPP_C15) - Sleep(5) + Sleep(1) /* t2 */ + Store(1,STA) } } - - Method (_OFF, 0, Serialized) + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ { If ((STA == One)) { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + /* Pull RST low */ CTXS(GPP_C15) + /* Pull PWREN low */ CTXS(GPP_B23) - /* Disable CLK0 */ - MCOF(0) + Store(0,STA) } } - - Method (_STA, 0, NotSerialized) + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (STA) } @@ -213,33 +211,29 @@ Device (CAM0) { - Name (_HID, "OVTI8856") - Name (_UID, Zero) - Name (_DDN, "Ov 8856 Camera") - Method (_STA, 0, NotSerialized) + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C3", 0x00, ResourceConsumer, , ) }) - - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { RCPR }) - - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { RCPR }) - - Name (_DSD, Package (0x04) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) @@ -250,7 +244,6 @@ "PRT0" } }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x02) { @@ -269,7 +262,6 @@ } } }) - Name (PRT0, Package (0x04) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), @@ -281,7 +273,6 @@ Zero } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -292,24 +283,39 @@ } } }) - Name (EP00, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x03) + Package (0x05) { Package (0x02) { "endpoint", Zero }, - + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, Package (0x02) { "link-frequencies", - Package (0x01) + Package (0x02) { - 0x325AA000 + 0x15752A00, + 0xABA9500 } }, Package (0x02) @@ -328,34 +334,33 @@ Device (VCM0) { - Name (_HID, "PRP0001") - Name (_UID, 0x03) - Name (_DDN, "DW9714 VCM") - Method (_STA, 0, NotSerialized) + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C3", 0x00, ResourceConsumer, , ) }) - Name (_DEP, Package (0x01) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ { CAM0 }) - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { RCPR }) - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { RCPR }) - Name (_DSD, Package (0x02) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) @@ -375,40 +380,53 @@ PowerResource (FCPR, 0x00, 0x0000) { Name (STA, Zero) - Method (_ON, 0, Serialized) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ { If ((STA == Zero)) { - /* Enable CLK1 with 19.2MHz */ - MCON(1,1) - /* Pull PWREN(GPIO R6) high */ - STXS(GPP_R6) - Sleep(5) - /* Pull RST(GPIO H12) low */ + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + + /* Pull RST low */ CTXS(GPP_H12) - Sleep(5) + + /* Pull PWREN high */ +#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY + STXS(GPP_E22) +#else + STXS(GPP_R6) +#endif + Sleep(2) /* reset pulse width */ + /* Pull RST high */ STXS(GPP_H12) - Sleep(5) + Sleep(1) /* t2 */ + Store(1,STA) } } - - Method (_OFF, 0, Serialized) + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ { If ((STA == One)) { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + /* Pull RST low */ CTXS(GPP_H12) + /* Pull PWREN low */ +#if CONFIG_BOARD_INTEL_TIGERLAKE_RVPY + CTXS(GPP_E22) +#else CTXS(GPP_R6) - /* Disable CLK1 */ - MCOF(1) +#endif + Store(0,STA) } } - - Method (_STA, 0, NotSerialized) // _STA: Status + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (STA) } @@ -416,33 +434,29 @@ Device (CAM1) { - Name (_HID, "OVTI8856") - Name (_UID, Zero) - Name (_DDN, "Ov 8856 Camera") - Method (_STA, 0, NotSerialized) + Name (_HID, "OVTI8856") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 8856 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ { Return (0x0F) } - - Name (_CRS, ResourceTemplate () + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ { I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C5", 0x00, ResourceConsumer, , ) }) - - Name (_PR0, Package (0x01) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ { FCPR }) - - Name (_PR3, Package (0x01) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ { FCPR }) - - Name (_DSD, Package (0x04) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ { ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) @@ -453,7 +467,6 @@ "PRT0" } }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package (0x01) { @@ -464,7 +477,6 @@ } } }) - Name (PRT0, Package (0x04) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), @@ -476,7 +488,6 @@ Zero } }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { @@ -487,24 +498,39 @@ } } }) - Name (EP00, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x03) + Package (0x05) { Package (0x02) { "endpoint", Zero }, - + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x04) + { + One, + 0x02, + 0x03, + 0x04 + } + }, Package (0x02) { "link-frequencies", - Package (0x01) + Package (0x02) { - 0x325AA000 + 0x15752A00, + 0xABA9500 } }, Package (0x02) -- To view, visit https://review.coreboot.org/c/coreboot/+/39529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11a36f1f82fe425c1a5796847ce020007064403 Gerrit-Change-Number: 39529 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL
by Rizwan Qureshi (Code Review) 17 Mar '20

17 Mar '20

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39498 ) Change subject: src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL ...................................................................... src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL In method RAOW is assumin that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sendign the exact address of the register to be updated. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 --- M src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl 1 file changed, 15 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39498/1 diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index ab1097e..d9d6e0b 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -17,23 +17,15 @@ #define R_ICLK_PCR_CAMERA1 0x8000 #define B_ICLK_PCR_FREQUENCY 0x1 #define B_ICLK_PCR_REQUEST 0x2 +#define B_ICLK_PCR_OFFSET 0xC Scope (\_SB.PCI0) { - /* IsCLK PCH register for clock settings */ - OperationRegion (ICLK, SystemMemory, PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, 0x40) - Field (ICLK, AnyAcc, Lock, Preserve) + Name (ICKB, 0) + Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) + + Method (OFST, 0x1, NotSerialized) { - CLK1, 8, - Offset(0x0C), - CLK2, 8, - Offset(0x18), - CLK3, 8, - Offset(0x24), - CLK4, 8, - Offset(0x30), - CLK5, 8, - Offset(0x3C), - CLK6, 8, + Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)) } /* @@ -44,8 +36,13 @@ */ Method (RAOW, 0x3, NotSerialized) { - Local0 = Arg0 - Arg0 = Local0 & Arg1 | Arg2 + OperationRegion (ICLK, SystemMemory, Arg0, 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 } /* @@ -56,33 +53,7 @@ Method(CLKC, 0x2, NotSerialized) { - Switch (ToInteger (Arg0)) - { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_REQUEST, Arg1 << 1) - } - } + RAOW (OFST(Arg0), ~B_ICLK_PCR_REQUEST, Arg1 << 1) } /* @@ -92,33 +63,7 @@ */ Method (CLKF, 0x2, NotSerialized) { - Switch (ToInteger (Arg0)) - { - Case (0) - { - RAOW (CLK1, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (1) - { - RAOW (CLK2, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (2) - { - RAOW (CLK3, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (3) - { - RAOW (CLK4, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (4) - { - RAOW (CLK5, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - Case (5) - { - RAOW (CLK6, ~B_ICLK_PCR_FREQUENCY, Arg1) - } - } + RAOW (OFST(Arg0), ~B_ICLK_PCR_FREQUENCY, Arg1) } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/39498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Gerrit-Change-Number: 39498 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: src/include/device: Add Intel Tiger Lake Thunderbolt device Id
by John Zhao (Code Review) 17 Mar '20

17 Mar '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39526 ) Change subject: src/include/device: Add Intel Tiger Lake Thunderbolt device Id ...................................................................... src/include/device: Add Intel Tiger Lake Thunderbolt device Id Tiger Lake Thunderbolt(TBT) has 4 root ports. Add those TBT root port devices Id. Change-Id: Ia117d63daa15dfb21db28fd76723e97ab030da92 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39526/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ccbfe40..712210f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3623,6 +3623,12 @@ #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 #define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 +/* Intel Thunderbolt device Ids */ +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23 +#define PCI_DEVICE_ID_INTLE_TGL_TBT_RP1 0x9a25 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 + /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 #define PCI_DEVICE_ID_6005_SERIES_WIFI 0x0085 -- To view, visit https://review.coreboot.org/c/coreboot/+/39526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia117d63daa15dfb21db28fd76723e97ab030da92 Gerrit-Change-Number: 39526 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...
by Jeremy Soller (Code Review) 17 Mar '20

17 Mar '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536 Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE ...................................................................... soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..3716640 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -172,6 +172,13 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..c95a68f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -246,6 +246,12 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + params->PchSirqMode = 1; + else + params->PchSirqMode = 0; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Gerrit-Change-Number: 31536 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: src/device/pci_rom.c: Show device IDs on oprom failure
by Felix Held (Code Review) 17 Mar '20

17 Mar '20

Hello Raul Rangel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39586 to review the following change. Change subject: src/device/pci_rom.c: Show device IDs on oprom failure ...................................................................... src/device/pci_rom.c: Show device IDs on oprom failure On a device/option-rom ID mismatch, the option rom's IDs would get shown twice instead of showing the actual device's IDs. This was very confusing because the error showed matching IDs. BUG=None TEST=Shows mismatched IDs when option rom doesn't match the hardware Change-Id: I5a06d6a7319aa653c8a5e32ec3c5afb651d83140 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/device/pci_rom.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/39586/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 816255d..27f2d8d 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -98,7 +98,7 @@ || dev->device != rom_data->device) && (vendev == mapped_vendev)) { printk(BIOS_ERR, "ID mismatch: vendor ID %04x, " - "device ID %04x\n", rom_data->vendor, rom_data->device); + "device ID %04x\n", dev->vendor, dev->device); return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a06d6a7319aa653c8a5e32ec3c5afb651d83140 Gerrit-Change-Number: 39586 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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