coreboot-gerrit March 2020

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Change in coreboot[master]: mb/google/octopus: Add custom SAR values for Foob360
by Peichao Li (Code Review) 17 Mar '20

17 Mar '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39424 ) Change subject: mb/google/octopus: Add custom SAR values for Foob360 ...................................................................... mb/google/octopus: Add custom SAR values for Foob360 Foob360 would prefer to use different SAR values. Since Foob360 sku id is 9. BUG=b:149362272 BRANCH=octopus TEST=build Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e --- M src/mainboard/google/octopus/variants/foob/Makefile.inc A src/mainboard/google/octopus/variants/foob/mainboard.c 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/39424/1 diff --git a/src/mainboard/google/octopus/variants/foob/Makefile.inc b/src/mainboard/google/octopus/variants/foob/Makefile.inc index a291304..a800275 100644 --- a/src/mainboard/google/octopus/variants/foob/Makefile.inc +++ b/src/mainboard/google/octopus/variants/foob/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/foob/mainboard.c b/src/mainboard/google/octopus/variants/foob/mainboard.c new file mode 100644 index 0000000..2619162 --- /dev/null +++ b/src/mainboard/google/octopus/variants/foob/mainboard.c @@ -0,0 +1,32 @@ +/* + *thiss file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + return NULL; + + if (sku_id == 9) + filename = "wifi_sar-foob360.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e Gerrit-Change-Number: 39424 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: jasperlake_rvp: Update UART config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: Update UART config for JSLRVP ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 08:22:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: jasperlake_rvp: Update UART config for JSLRVP
by Maulik V Vaghela (Code Review) 17 Mar '20

17 Mar '20

Maulik V Vaghela has uploaded a new patch set (#10) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: Update UART config for JSLRVP ...................................................................... jasperlake_rvp: Update UART config for JSLRVP Update UART config for JSLRVP variants. jslrvp board uses 8250IO UART while board with external EC support uses LPSS uart on port 2. BUG=None BRANCH=None TEST=code compiles for JSLRVP and JSLRVP_EXT_EC Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/39196/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 10 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/broadwell: remove unused function init_one_gpio()
by Matt DeVillier (Code Review) 17 Mar '20

17 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39576 ) Change subject: soc/broadwell: remove unused function init_one_gpio() ...................................................................... soc/broadwell: remove unused function init_one_gpio() Function was copied as part of upstreaming from Chromium tree, but isn't used and has never been used best I can tell. Change-Id: I53b8702c97d7a694450aa05ba49da6c26c30f725 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/gpio.c M src/soc/intel/broadwell/include/soc/gpio.h 2 files changed, 0 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39576/1 diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c index 81ad9d4..8975f5e 100644 --- a/src/soc/intel/broadwell/gpio.c +++ b/src/soc/intel/broadwell/gpio.c @@ -49,54 +49,6 @@ }; } -void init_one_gpio(int gpio_num, struct gpio_config *config) -{ - u32 owner, route, irqen, reset; - int set, bit; - - if (gpio_num > MAX_GPIO_NUMBER || !config) - return; - - outl(config->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); - outl(config->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio_num)); - - /* Determine set and bit based on GPIO number */ - set = gpio_num >> 5; - bit = gpio_num % 32; - - /* Save settings from current GPIO config */ - owner = inl(GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - route = inl(GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - irqen = inl(GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - reset = inl(GPIO_BASE_ADDRESS + GPIO_RESET(set)); - - owner |= config->owner << bit; - route |= config->route << bit; - irqen |= config->irqen << bit; - reset |= config->reset << bit; - - outl(owner, GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - outl(route, GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - outl(irqen, GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - outl(reset, GPIO_BASE_ADDRESS + GPIO_RESET(set)); - - if (set == 0) { - u32 blink = inl(GPIO_BASE_ADDRESS + GPIO_BLINK); - blink |= config->blink << bit; - outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); - } - - /* PIRQ to IO-APIC map */ - if (config->pirq == GPIO_PIRQ_APIC_ROUTE) { - u32 pirq2apic = inl(GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); - set = gpio_to_pirq(gpio_num); - if (set >= 0) { - pirq2apic |= 1 << set; - outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); - } - } -} - void init_gpios(const struct gpio_config config[]) { const struct gpio_config *entry; diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index c0ac134..3c7f08a 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -175,7 +175,6 @@ } __packed; /* Configure GPIOs with mainboard provided settings */ -void init_one_gpio(int gpio_num, struct gpio_config *config); void init_gpios(const struct gpio_config config[]); /* Get GPIO pin value */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b8702c97d7a694450aa05ba49da6c26c30f725 Gerrit-Change-Number: 39576 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism: remove duplicate ACPI power button
by Matt DeVillier (Code Review) 17 Mar '20

17 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39577 ) Change subject: mb/purism: remove duplicate ACPI power button ...................................................................... mb/purism: remove duplicate ACPI power button These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_bdw/acpi/mainboard.asl M src/mainboard/purism/librem_skl/acpi/mainboard.asl 2 files changed, 0 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39577/1 diff --git a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl index f0b2c1d..0e4842d 100644 --- a/src/mainboard/purism/librem_bdw/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_bdw/acpi/mainboard.asl @@ -30,18 +30,6 @@ } } - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - - Method (_STA) - { - Return (0xF) - } - - Name (_PRW, Package () { 27, 4 }) - } - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) diff --git a/src/mainboard/purism/librem_skl/acpi/mainboard.asl b/src/mainboard/purism/librem_skl/acpi/mainboard.asl index f0b2c1d..0e4842d 100644 --- a/src/mainboard/purism/librem_skl/acpi/mainboard.asl +++ b/src/mainboard/purism/librem_skl/acpi/mainboard.asl @@ -30,18 +30,6 @@ } } - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - - Method (_STA) - { - Return (0xF) - } - - Name (_PRW, Package () { 27, 4 }) - } - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) -- To view, visit https://review.coreboot.org/c/coreboot/+/39577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17c85e43493530d04f4fa13f33bec6d027cb3147 Gerrit-Change-Number: 39577 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: memrange: Add a helper function to determine if memranges is empty
by Furquan Shaikh (Code Review) 17 Mar '20

17 Mar '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39485 ) Change subject: memrange: Add a helper function to determine if memranges is empty ...................................................................... memrange: Add a helper function to determine if memranges is empty This change adds a helper function memranges_is_empty() which returns true if there are no entries in memranges. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: If841c42a9722cbc73ef321568928bc175bf88fd5 --- M src/include/memrange.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39485/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index 9b1d1d2..8406237 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -81,6 +81,11 @@ r->tag = new_tag; } +static inline bool memranges_is_empty(struct memranges *ranges) +{ + return ranges->entries == NULL; +} + /* Iterate over each entry in a memranges structure. Ranges cannot * be deleted while processing each entry as the list cannot be safely * traversed after such an operation. -- To view, visit https://review.coreboot.org/c/coreboot/+/39485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If841c42a9722cbc73ef321568928bc175bf88fd5 Gerrit-Change-Number: 39485 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: memrange: Enable memranges to support different alignments
by Furquan Shaikh (Code Review) 17 Mar '20

17 Mar '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39483 ) Change subject: memrange: Enable memranges to support different alignments ...................................................................... memrange: Enable memranges to support different alignments This change enables memranges library to support addresses with different alignments. Before this change, memranges library supported aligning addresses to 4KiB only. Though this works for most cases, it might not be the right alignment for every use case. Example: There are some resource allocator changes coming up that require a different alignment when handling the range list. This change adds a align parameter to struct memranges that determines the alignment of all range lists in that memrange. In order to continue supporting current users of memranges, default alignment is maintained as 4KiB. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I1da0743ff89da734c9a0972e3c56d9f512b3d1e8 --- M src/include/memrange.h M src/lib/memrange.c 2 files changed, 34 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/39483/1 diff --git a/src/include/memrange.h b/src/include/memrange.h index 7f42aa2..fba77af 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -24,6 +24,8 @@ /* coreboot doesn't have a free() function. Therefore, keep a cache of * free'd entries. */ struct range_entry *free_list; + /* Alignment for base and end addresses of the range. */ + size_t align; }; /* Each region within a memranges structure is represented by a @@ -86,17 +88,32 @@ #define memranges_each_entry(r, ranges) \ for (r = (ranges)->entries; r != NULL; r = r->next) + /* Initialize memranges structure providing an optional array of range_entry - * to use as the free list. */ -void memranges_init_empty(struct memranges *ranges, struct range_entry *free, - size_t num_free); + * to use as the free list. Additionally, it accepts an align parameter that + * determines the alignment of addresses. */ +void memranges_init_empty_with_alignment(struct memranges *ranges, + struct range_entry *free, + size_t num_free, size_t align); /* Initialize and fill a memranges structure according to the * mask and match type for all memory resources. Tag each entry with the - * specified type. */ -void memranges_init(struct memranges *ranges, + * specified type. Additionally, it accepts an align parameter that + * determines the alignment of addresses. */ +void memranges_init_with_alignment(struct memranges *ranges, unsigned long mask, unsigned long match, - unsigned long tag); + unsigned long tag, size_t align); + +/* Initialize memranges structure providing an optional array of range_entry + * to use as the free list. Addresses are default aligned to 4KiB. */ +#define memranges_init_empty(__ranges, __free, __num_free) \ + memranges_init_empty_with_alignment(__ranges, __free, __num_free, 4 * KiB) + +/* Initialize and fill a memranges structure according to the + * mask and match type for all memory resources. Tag each entry with the + * specified type. Addresses are default aligned to 4KiB. */ +#define memranges_init(__ranges, __mask, __match, __tag) \ + memranges_init_with_alignment(__ranges, __mask, __match, __tag, 4 * KiB) /* Clone a memrange. The new memrange has the same entries as the old one. */ void memranges_clone(struct memranges *newranges, struct memranges *oldranges); diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 79a1b0e..a76f24c 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -231,9 +231,9 @@ /* The addresses are aligned to 4096 bytes: the begin address is * aligned down while the end address is aligned up to be conservative * about the full range covered. */ - begin = ALIGN_DOWN(base, 4096); + begin = ALIGN_DOWN(base, ranges->align); end = begin + size + (base - begin); - end = ALIGN_UP(end, 4096) - 1; + end = ALIGN_UP(end, ranges->align) - 1; action(ranges, begin, end, tag); } @@ -290,23 +290,25 @@ memranges_add_resources_filter(ranges, mask, match, tag, NULL); } -void memranges_init_empty(struct memranges *ranges, struct range_entry *to_free, - size_t num_free) +void memranges_init_empty_with_alignment(struct memranges *ranges, + struct range_entry *to_free, + size_t num_free, size_t align) { size_t i; ranges->entries = NULL; ranges->free_list = NULL; + ranges->align = align; for (i = 0; i < num_free; i++) range_entry_link(&ranges->free_list, &to_free[i]); } -void memranges_init(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) +void memranges_init_with_alignment(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, size_t align) { - memranges_init_empty(ranges, NULL, 0); + memranges_init_empty_with_alignment(ranges, NULL, 0, align); memranges_add_resources(ranges, mask, match, tag); } @@ -316,7 +318,7 @@ struct range_entry *r, *cur; struct range_entry **prev_ptr; - memranges_init_empty(newranges, NULL, 0); + memranges_init_empty_with_alignment(newranges, NULL, 0, oldranges->align); prev_ptr = &newranges->entries; memranges_each_entry(r, oldranges) { -- To view, visit https://review.coreboot.org/c/coreboot/+/39483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1da0743ff89da734c9a0972e3c56d9f512b3d1e8 Gerrit-Change-Number: 39483 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Temp full gpio.c and devicetree.cb
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has restored this change. ( https://review.coreboot.org/c/coreboot/+/39426 ) Change subject: Temp full gpio.c and devicetree.cb ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/39426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfdd1bbb0865d57161c6fba23d0543fd4619ddc0 Gerrit-Change-Number: 39426 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: restore

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Change in coreboot[master]: temp error fix
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has restored this change. ( https://review.coreboot.org/c/coreboot/+/39404 ) Change subject: temp error fix ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/39404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib078eb27d1c7e046d42b371d1aa6834fae12c57b Gerrit-Change-Number: 39404 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: restore

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Change in coreboot[master]: jasperlake_rvp: Add UART config for JSLRVP
by Ronak Kanabar (Code Review) 17 Mar '20

17 Mar '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39196 ) Change subject: jasperlake_rvp: Add UART config for JSLRVP ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/39196/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39196/5//COMMIT_MSG@7 PS5, Line 7: jasperlake_rvp: UART config for JSLRVP > Please make it a statement by adding a verb (in imperative mood). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic042cdc449b77c2d9bdd7a63777328e47f910654 Gerrit-Change-Number: 39196 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 07:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit March 2020