coreboot-gerrit March 2020

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Change in coreboot[master]: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake
by Franklin (Yanjin) He (Code Review) 16 Mar '20

16 Mar '20

Franklin (Yanjin) He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39579 ) Change subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake ...................................................................... Patch Set 2: Code-Review+1 Addressed code review comments -- To view, visit https://review.coreboot.org/c/coreboot/+/39579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Gerrit-Change-Number: 39579 Gerrit-PatchSet: 2 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 05:10:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Selma Bensaid (Code Review) 16 Mar '20

16 Mar '20

Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 3: > Patch Set 3: > > Should we create deltaue in variants as well? Or just let it in baseboard? I think it is different variants. The plan is to add deltaur once we have the GPIO config. for the moment we focus on Deltan -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 04:19:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by EricR Lai (Code Review) 16 Mar '20

16 Mar '20

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 3: Should we create deltaue in variants as well? Or just let it in baseboard? I think it is different variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 04:16:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... Patch Set 11: (5 comments) https://review.coreboot.org/c/coreboot/+/39538/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39538/6//COMMIT_MSG@9 PS6, Line 9: Port of CB:39412 for Skylake. > Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for PCH Root ports), CB:39412) to S […] Done https://review.coreboot.org/c/coreboot/+/39538/6//COMMIT_MSG@10 PS6, Line 10: to devicetree to allow boards to set these options > Please add a dot/period at the end of sentences please. Done https://review.coreboot.org/c/coreboot/+/39538/6//COMMIT_MSG@12 PS6, Line 12: Chip config parameter PcieRpL1Substates uses (UPD value + 1) : because UPD value of 0 for PcieRpL1Substates means disabled for FSP. : In order to ensure that mainboard setting does not disable L1 substates : incorrectly, chip config parameter values are offset by 1 with 0 meaning : use FSP UPD default. > Please re-flow for 72 characters. Done https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip… PS6, Line 135: * Chip config parameter PcieRpL1Substates uses (UPD value + 1) : * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. : * In order to ensure that mainboard setting does not disable L1 substates : * incorrectly, chip config parameter values are offset by 1 with 0 meaning : * use FSP UPD default. get_l1_substate_control() ensures that the right UPD : * value is set in fsp_params. > Please re-flow for 96 characters. Done https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip… PS6, Line 224: get_l1_substate_control(config->PcieRpL1Substates[i]); > Why not combine both loops? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 01:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#11). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options. get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#10). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port commit 84b4882b (soc/intel/tigerlake: Configure L1Substates for PCH Root ports), CB:39412) to Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#9). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#8). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options get_{aspm,l1_substate}_control() ensure that the right UPD value is set in fsp_params. Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by build bot (Jenkins) (Code Review) 16 Mar '20

16 Mar '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/39538/7/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/39538/7/src/soc/intel/skylake/chip… PS7, Line 135: * Chip config parameters PcieRpAspm and PcieRpL1Substates use (UPD value + 1) because UPD values line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 01:16:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
by Benjamin Doron (Code Review) 16 Mar '20

16 Mar '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#7). Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates to devicetree to allow boards to set these options Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2020