coreboot-gerrit March 2020

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Change in coreboot[master]: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl
by 9elements QA (Code Review) 16 Mar '20

16 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39563 ) Change subject: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1386 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1385 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1384 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Gerrit-Change-Number: 39563 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Mar 2020 01:10:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39563 ) Change subject: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl ...................................................................... util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl Add a bunch of missing chipsets to print_bioscntl. Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/inteltool/spi.c 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index e8289ac..ca29fcc 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -175,6 +175,20 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: -- To view, visit https://review.coreboot.org/c/coreboot/+/39563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Gerrit-Change-Number: 39563 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39563 ) Change subject: util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Gerrit-Change-Number: 39563 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 00:58:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping LPC registers
by 9elements QA (Code Review) 16 Mar '20

16 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39517 ) Change subject: util/inteltool: add code for dumping LPC registers ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1383 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1382 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1381 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Gerrit-Change-Number: 39517 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Mar 2020 00:33:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add code for dumping LPC registers
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39517 ) Change subject: util/inteltool: add code for dumping LPC registers ...................................................................... util/inteltool: add code for dumping LPC registers This adds the implementation for dumping LPC registers Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39517 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/Makefile M util/inteltool/inteltool.c M util/inteltool/inteltool.h A util/inteltool/lpc.c 4 files changed, 179 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 23ea8a6..b15ae8e 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -29,7 +29,7 @@ OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o lpc.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 0e84b55..8d5d994 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -494,7 +494,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrplmedPMaAsfSRx]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -505,6 +505,7 @@ " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" " -p | --pmbase: dump southbridge Power Management registers\n\n" + " -l | --lpc: dump southbridge LPC/eSPI Interface registers\n\n" " -m | --mchbar: dump northbridge Memory Controller registers\n" " -S FILE | --spd=FILE: create a file storing current timings (implies -m)\n" " -e | --epbar: dump northbridge EPBAR registers\n" @@ -574,6 +575,7 @@ int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; + int dump_lpc = 0; int show_gpio_diffs = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -586,6 +588,7 @@ {"mchbar", 0, 0, 'm'}, {"rcba", 0, 0, 'r'}, {"pmbase", 0, 0, 'p'}, + {"lpc", 0, 0, 'l'}, {"epbar", 0, 0, 'e'}, {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, @@ -601,7 +604,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrplmedPMaAsfRS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -633,6 +636,9 @@ case 'p': dump_pmbase = 1; break; + case 'l': + dump_lpc = 1; + break; case 'e': dump_epbar = 1; break; @@ -651,6 +657,7 @@ dump_mchbar = 1; dump_rcba = 1; dump_pmbase = 1; + dump_lpc = 1; dump_epbar = 1; dump_dmibar = 1; dump_pciexbar = 1; @@ -816,6 +823,11 @@ printf("\n\n"); } + if (dump_lpc) { + print_lpc(sb, pacc); + printf("\n\n"); + } + if (dump_mchbar) { print_mchbar(nb, pacc, dump_spd_file); printf("\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 2bd2afc..85f29fd 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -396,6 +396,7 @@ int print_intel_core_msrs(void); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); +int print_lpc(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); const struct gpio_community *const *get_gpio_communities(struct pci_dev *const sb, diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c new file mode 100644 index 0000000..247c37a --- /dev/null +++ b/util/inteltool/lpc.c @@ -0,0 +1,163 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2008-2010 by coresystems GmbH + * written by Stefan Reinauer <stepan(a)coresystems.de> + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2020 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <inttypes.h> +#include <commonlib/helpers.h> +#include "inteltool.h" + +#define SUNRISE_LPC_BC 0xdc + +static const io_register_t sunrise_lpc_cfg_registers[] = { + {0x00, 4, "ID"}, + {0x04, 2, "CMD"}, + {0x06, 2, "STS"}, + {0x08, 1, "RID"}, + {0x09, 1, "CC[3]"}, + {0x0A, 1, "CC[2]"}, + {0x0B, 1, "CC[1]"}, + {0x0C, 1, "CC[0]"}, + {0x0E, 1, "HTYPE"}, + {0x2C, 4, "SS"}, + {0x34, 1, "CAPP"}, + {0x64, 1, "SCNT"}, + {0x80, 2, "IOD"}, + {0x82, 2, "IOE"}, + {0x84, 4, "LGIR1"}, + {0x88, 4, "LGIR2"}, + {0x8C, 4, "LGIR3"}, + {0x90, 4, "LGIR4"}, + {0x94, 4, "ULKMC"}, + {0x98, 4, "LGMR"}, + {0xD0, 2, "FS1"}, + {0xD4, 2, "FS2"}, + {0xD8, 2, "BDE"}, + {0xDC, 1, "BC"}, + {0xE0, 4, "PCCTL"}, +}; + +static const io_register_t sunrise_espi_cfg_registers[] = { + {0x00, 4, "ESPI_DID_VID"}, + {0x04, 4, "ESPI_STS_CMD"}, + {0x08, 4, "ESPI_CC_RID"}, + {0x0C, 4, "ESPI_BIST_HTYPE_PLT_CLS"}, + {0x2C, 4, "ESPI_SS"}, + {0x34, 4, "ESPI_CAPP"}, + {0x80, 4, "ESPI_IOD_IOE"}, + {0x84, 4, "ESPI_LGIR1"}, + {0x88, 4, "ESPI_LGIR2"}, + {0x8C, 4, "ESPI_LGIR3"}, + {0x90, 4, "ESPI_LGIR4"}, + {0x94, 4, "ESPI_ULKMC"}, + {0x98, 4, "ESPI_LGMR"}, + {0xD0, 4, "ESPI_FS1"}, + {0xD4, 4, "ESPI_FS2"}, + {0xD8, 4, "ESPI_BDE"}, + {0xDC, 4, "ESPI_BC"}, +}; + +int print_lpc(struct pci_dev *sb, struct pci_access *pacc) +{ + size_t i, cfg_registers_size = 0; + const io_register_t *cfg_registers; + struct pci_dev *dev = NULL; + uint32_t bc; + + printf("\n========== LPC/eSPI =========\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC/eSPI interface not found.\n"); + return 1; + } + bc = pci_read_long(dev, SUNRISE_LPC_BC); + if (bc & (1 << 2)) { + printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); + cfg_registers = sunrise_espi_cfg_registers; + cfg_registers_size = ARRAY_SIZE(sunrise_espi_cfg_registers); + + } else { + printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n"); + cfg_registers = sunrise_lpc_cfg_registers; + cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); + } + break; + + default: + printf("Error: Dumping LPC/eSPI on this southbridge is not (yet) supported.\n"); + return 1; + } + + for (i = 0; i < cfg_registers_size; i++) { + switch (cfg_registers[i].size) { + case 4: + printf("0x%04x: 0x%08x (%s)\n", + cfg_registers[i].addr, + pci_read_long(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + cfg_registers[i].addr, + pci_read_word(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + cfg_registers[i].addr, + pci_read_byte(dev, cfg_registers[i].addr), + cfg_registers[i].name); + break; + default: + printf("Error: register size %d not implemented.\n", + cfg_registers[i].size); + break; + } + } + + if (dev) + pci_free_dev(dev); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Gerrit-Change-Number: 39517 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: Makefile: add src/arch to includes
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39525 ) Change subject: util/inteltool: Makefile: add src/arch to includes ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/39525/5/util/inteltool/Makefile File util/inteltool/Makefile: https://review.coreboot.org/c/coreboot/+/39525/5/util/inteltool/Makefile@48 PS5, Line 48: ARCH = $(subst _64,,$(shell uname -m)) > Dynamically determining the architecture seems superfluous to me. […] yeah, ARCH will always be x86 here, since all targets for inteltool are x86 devices. so only "CPPFLAGS += -I$(top)/src/arch/x86/include" would be sufficient here. no need to copy the macros imho; i can see both pros and cons for that, but i'm totally fine with just including them here don't have a particularly strong opinion on those two though -- To view, visit https://review.coreboot.org/c/coreboot/+/39525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96 Gerrit-Change-Number: 39525 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 16 Mar 2020 22:53:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: ahci: add Sunrise Point config and SIR registers
by 9elements QA (Code Review) 16 Mar '20

16 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39506 ) Change subject: util/inteltool: ahci: add Sunrise Point config and SIR registers ...................................................................... Patch Set 12: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1380 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1379 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1378 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Gerrit-Change-Number: 39506 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Mar 2020 22:52:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: ahci: add code for dumping config and SIR registers
by 9elements QA (Code Review) 16 Mar '20

16 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39560 ) Change subject: util/inteltool: ahci: add code for dumping config and SIR registers ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1377 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1376 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1375 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Gerrit-Change-Number: 39560 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Mar 2020 22:48:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: ahci: add Sunrise Point config and SIR registers
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39506 ) Change subject: util/inteltool: ahci: add Sunrise Point config and SIR registers ...................................................................... util/inteltool: ahci: add Sunrise Point config and SIR registers This adds the Sunrise Point AHCI config and SIR registers from doc#332691-003EN. Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/ahci.c 1 file changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 3a18993..90a1617 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -34,6 +34,53 @@ "PxFBS", "PxDEVSLP", "Reserved" }; +static const io_register_t sunrise_ahci_cfg_registers[] = { + {0x0, 4, "ID"}, + {0x4, 2, "CMD"}, + {0x6, 2, "STS"}, + {0x8, 1, "RID"}, + {0x9, 1, "PI"}, + {0xa, 2, "CC"}, + {0xc, 1, "CLS"}, + {0xd, 1, "MLT"}, + {0xe, 1, "HTYPE"}, + {0x10, 4, "MXTBA"}, + {0x14, 4, "MXPBA"}, + {0x20, 4, "AIDPBA"}, + {0x24, 4, "ABAR"}, + {0x2c, 4, "SS"}, + {0x34, 1, "CAP"}, + {0x3c, 2, "INTR"}, + {0x70, 2, "PID"}, + {0x72, 2, "PC"}, + {0x74, 2, "PMCS"}, + {0x80, 2, "MID"}, + {0x82, 2, "MC"}, + {0x84, 4, "MA"}, + {0x88, 2, "MD"}, + {0x90, 4, "MAP"}, + {0x94, 4, "PCS"}, + {0x9c, 4, "SATAGC"}, + {0xa0, 1, "SIRI"}, + {0xa4, 4, "SIRD"}, + {0xa8, 4, "SATACR0"}, + {0xac, 4, "SATACR1"}, + {0xc0, 4, "SP"}, + {0xd0, 2, "MXID"}, + {0xd2, 2, "MXC"}, + {0xd4, 4, "MXT"}, + {0xd8, 4, "MXP"}, + {0xe0, 4, "BFCS"}, + {0xe4, 4, "BFTD1"}, + {0xe8, 4, "BFTD2"}, +}; + +static const io_register_t sunrise_ahci_sir_registers[] = { + {0x80, 4, "SQUELCH"}, + {0x90, 4, "SATA_MPHY_PG"}, + {0xa4, 4, "OOBRETR"}, +}; + #define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0])) #define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0])) @@ -76,6 +123,11 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA: ahci_registers_size = 0x800; + ahci_sir_offset = 0xa0; + ahci_cfg_registers = sunrise_ahci_cfg_registers; + ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers); + ahci_sir_registers = sunrise_ahci_sir_registers; + ahci_sir_registers_size = ARRAY_SIZE(sunrise_ahci_sir_registers); break; default: ahci_registers_size = 0x400; -- To view, visit https://review.coreboot.org/c/coreboot/+/39506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Gerrit-Change-Number: 39506 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: ahci: add code for dumping config and SIR registers
by Felix Held (Code Review) 16 Mar '20

16 Mar '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39560 ) Change subject: util/inteltool: ahci: add code for dumping config and SIR registers ...................................................................... util/inteltool: ahci: add code for dumping config and SIR registers This adds the code required to dump config and SIR registers. Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/ahci.c 1 file changed, 54 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 09f6427..3a18993 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -60,6 +60,11 @@ int print_ahci(struct pci_dev *ahci) { size_t ahci_registers_size = 0, i; + size_t ahci_cfg_registers_size = 0; + const io_register_t *ahci_cfg_registers; + size_t ahci_sir_offset = 0; + size_t ahci_sir_registers_size = 0; + const io_register_t *ahci_sir_registers; if (!ahci) { puts("No SATA device found"); @@ -76,6 +81,55 @@ ahci_registers_size = 0x400; } + printf("\n============= AHCI Configuration Registers ==============\n\n"); + for (i = 0; i < ahci_cfg_registers_size; i++) { + switch (ahci_cfg_registers[i].size) { + case 4: + printf("0x%04x: 0x%08x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_long(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + case 2: + printf("0x%04x: 0x%04x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_word(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + case 1: + printf("0x%04x: 0x%02x (%s)\n", + ahci_cfg_registers[i].addr, + pci_read_byte(ahci, ahci_cfg_registers[i].addr), + ahci_cfg_registers[i].name); + break; + } + } + + printf("\n============= SATA Initialization Registers ==============\n\n"); + for (i = 0; i < ahci_sir_registers_size; i++) { + pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr); + switch (ahci_sir_registers[i].size) { + case 4: + printf("0x%02x: 0x%08x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_long(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + case 2: + printf("0x%02x: 0x%04x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_word(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + case 1: + printf("0x%02x: 0x%02x (%s)\n", + ahci_sir_registers[i].addr, + pci_read_byte(ahci, ahci_sir_offset), + ahci_sir_registers[i].name); + break; + } + } + const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL; printf("\n============= ABAR ==============\n\n"); printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys); -- To view, visit https://review.coreboot.org/c/coreboot/+/39560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Gerrit-Change-Number: 39560 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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