9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39568 )
Change subject: util/inteltool: add 6th gen. mobile core u/y series
......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1366
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1365
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1364
Please note: This test is under development and might not be accurate at all!
--
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Gerrit-Branch: master
Gerrit-Change-Id: I7d802452353afe568e3880765dcd340f0437b392
Gerrit-Change-Number: 39568
Gerrit-PatchSet: 2
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com>
Gerrit-Comment-Date: Mon, 16 Mar 2020 15:06:43 +0000
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Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39480 )
Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................
soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
BRANCH=none
BUG=b:145946347
TEST=none
Signed-off-by: Hu, Hebo <hebo.hu(a)intel.com>
Signed-off-by: li feng <li1.feng(a)intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/1
diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
new file mode 100644
index 0000000..186a147
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+ Name (_ADR, 0x00120000)
+ Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 8593d07..8e17abb 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -46,6 +46,9 @@
/* SMBus 0:1f.4 */
#include "smbus.asl"
+/* ISH 0:12.0 */
+#include "ish.asl"
+
/* USB XHCI 0:14.0 */
#include "xhci.asl"
--
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Gerrit-Branch: master
Gerrit-Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Gerrit-Change-Number: 39480
Gerrit-PatchSet: 1
Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39571 )
Change subject: Revert "crossgcc: Upgrade GCC to 9.2.0"
......................................................................
Revert "crossgcc: Upgrade GCC to 9.2.0"
Revert the upgrade as it breaks at least the devicetree parser on
aarch64, tested on qemu aarch64 target.
This reverts commit dfd3f211740be4cf0d234bf4621ac384758a24ce.
Change-Id: I65607817188db21533014caa6d15be9a2004d498
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch
A util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch
R util/crossgcc/patches/gcc-8.3.0_gnat.patch
R util/crossgcc/patches/gcc-8.3.0_libgcc.patch
A util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch
A util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum
D util/crossgcc/sum/gcc-9.2.0.tar.xz.cksum
M util/xcompile/xcompile
9 files changed, 21,174 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39571/1
--
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Gerrit-Branch: master
Gerrit-Change-Id: I65607817188db21533014caa6d15be9a2004d498
Gerrit-Change-Number: 39571
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39575 )
Change subject: util/crossgcc: Temporarily disable GDB build test on server
......................................................................
util/crossgcc: Temporarily disable GDB build test on server
The latest debian builder image doesn't compile GDB correctly. Disable
the build test until I can get it working again.
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083
---
M util/crossgcc/Makefile.inc
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39575/1
diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc
index 108612f..ed8d66e 100644
--- a/util/crossgcc/Makefile.inc
+++ b/util/crossgcc/Makefile.inc
@@ -79,7 +79,9 @@
# This target controls what the jenkins builder tests
jenkins-build-toolchain: BUILDGCC_OPTIONS ?= -y --nocolor
jenkins-build-toolchain:
- $(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)'
+ $(MAKE) crossgcc clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)'
+ #TODO: Re-enable gdb build after the builders can build it again.
+ #$(MAKE) crosstools clang KEEP_SOURCES=1 BUILDGCC_OPTIONS='$(BUILDGCC_OPTIONS)'
rm -f .xcompile
PATH=$(if $(DEST),$(DEST)/bin,$(top)/util/crossgcc/xgcc/bin):$$PATH; $(MAKE) what-jenkins-does
-cat .xcompile
--
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Gerrit-Branch: master
Gerrit-Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083
Gerrit-Change-Number: 39575
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39106 )
Change subject: mb/51nb/x210: merge harrykipper's changes
......................................................................
mb/51nb/x210: merge harrykipper's changes
merge in changes from https://github.com/harrykipper/coreboot
at commit 709cf02. Split out macOS-specific changes into
subsequent commit.
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
Change-Id: Ie2b79b236a458ebd243c992d6e615e41930eeb50
---
M src/mainboard/51nb/x210/Kconfig
M src/mainboard/51nb/x210/Makefile.inc
M src/mainboard/51nb/x210/acpi/battery.asl
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/51nb/x210/dsdt.asl
A src/mainboard/51nb/x210/gma-mainboard.ads
A src/mainboard/51nb/x210/ramstage.c
7 files changed, 83 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39106/1
diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig
index 072cf42..1a02cc5 100644
--- a/src/mainboard/51nb/x210/Kconfig
+++ b/src/mainboard/51nb/x210/Kconfig
@@ -2,16 +2,15 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select SYSTEM_TYPE_LAPTOP
select BOARD_ROMSIZE_KB_8192
+ select EC_51NB_NPCE985LA0DX
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select SOC_INTEL_KABYLAKE
+ select MAINBOARD_HAS_LIBGFXINIT
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
- select NO_POST
- select MAINBOARD_USES_FSP2_0
+ select SOC_INTEL_KABYLAKE
select SPD_READ_BY_WORD
- select EC_51NB_NPCE985LA0DX
+ select SYSTEM_TYPE_LAPTOP
config MAINBOARD_VENDOR
string
@@ -53,15 +52,11 @@
int
default 512
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x18000
-
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xFFE115A0
-
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config NO_POST
+ default y
+
endif
diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc
index f8136e0..c3f2ea9 100644
--- a/src/mainboard/51nb/x210/Makefile.inc
+++ b/src/mainboard/51nb/x210/Makefile.inc
@@ -14,3 +14,4 @@
##
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl
index 9a3a361..6689c83 100644
--- a/src/mainboard/51nb/x210/acpi/battery.asl
+++ b/src/mainboard/51nb/x210/acpi/battery.asl
@@ -50,16 +50,16 @@
Method (_BIF, 0, Serialized)
{
/* Design Capacity */
- Store (DGCP, Index (PBIF, 1))
+ Store (DGCP * 10000 / DGVO, Index (PBIF, 1))
/* Last Full Charge Capacity */
- Store (FLCP, Index (PBIF, 2))
+ Store (FLCP * 10000 / DGVO, Index (PBIF, 2))
/* Design Voltage */
Store (DGVO, Index (PBIF, 4))
/* Design Capacity of Warning */
- Store (BDW, Index (PBIF, 5))
+ Store (BDW * 10000 / DGVO, Index (PBIF, 5))
/* Design Capacity of Low */
Store (BDL, Index (PBIF, 6))
@@ -93,7 +93,7 @@
/*
* 2: BATTERY REMAINING CAPACITY
*/
- Store (BRC, Index (PBST, 2))
+ Store (BRC * 10000 / DGVO, Index (PBST, 2))
/*
* 3: BATTERY PRESENT VOLTAGE
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index cc95aa0..162fa33 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -1,5 +1,12 @@
chip soc/intel/skylake
+ # Enable Panel as eDP and configure power delays
+ register "gpu_pp_up_delay_ms" = "210" # T3
+ register "gpu_pp_down_delay_ms" = "500" # T10
+ register "gpu_pp_cycle_delay_ms" = "5000" # T12
+ register "gpu_pp_backlight_on_delay_ms" = "1" # T7
+ register "gpu_pp_backlight_off_delay_ms" = "200" # T9
+
# Enable deep Sx states
register "deep_s3_enable_ac" = "1"
register "deep_s3_enable_dc" = "1"
@@ -148,6 +155,7 @@
.dc_loadline = 310,
}"
+ # Enable CLKRUN logic to stop the PCI clocks when idle
register "PmConfigPciClockRun" = "1"
# Enable Root Ports 3, 4 and 9
@@ -164,17 +172,19 @@
register "PcieRpClkSrcNumber[3]" = "1"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
- register "PcieRpHotPlug[3]" = "1"
register "PcieRpEnable[8]" = "1" # NVMe controller
- register "PcieRpClkReqSupport[8]" = "0"
- register "PcieRpClkReqNumber[8]" = "2"
- register "PcieRpClkSrcNumber[8]" = "2"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4"
+ register "PcieRpClkSrcNumber[8]" = "4"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR
+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam
register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB
diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl
index a8a693a..dac04f2 100644
--- a/src/mainboard/51nb/x210/dsdt.asl
+++ b/src/mainboard/51nb/x210/dsdt.asl
@@ -44,7 +44,7 @@
}
// Chipset specific sleep states
- #include <soc/intel/skylake/acpi/sleepstates.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
diff --git a/src/mainboard/51nb/x210/gma-mainboard.ads b/src/mainboard/51nb/x210/gma-mainboard.ads
new file mode 100644
index 0000000..8a72a31
--- /dev/null
+++ b/src/mainboard/51nb/x210/gma-mainboard.ads
@@ -0,0 +1,30 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ HDMI1,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/51nb/x210/ramstage.c b/src/mainboard/51nb/x210/ramstage.c
new file mode 100644
index 0000000..7888c39
--- /dev/null
+++ b/src/mainboard/51nb/x210/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015-2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--
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Gerrit-Change-Number: 39106
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